more debugging tile read (c8076f57) · Commits · Elphel / x393

memctrl/cmd_encod_tiled_rd.v

+26 −93

Original line number	Original line	Diff line number	Diff line
	@@ -34,9 +34,10 @@ Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank
	Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)		Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
	Can read less if just one column		Can read less if just one column
	TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary		TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary

	number fo rows>1!		number fo rows>1!

			Need to insert pauses if activate in the first row and next column is too early

	*/		*/

	module cmd_encod_tiled_rd #(		module cmd_encod_tiled_rd #(
	@@ -151,9 +152,10 @@ module cmd_encod_tiled_rd #(


	assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;		assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
	assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)		// assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
			assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2]; // & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
	assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];		assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
	assign full_cmd= rom_cmd[1]?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);		assign full_cmd= (enable_act && rom_cmd[1])?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);

	assign last_row= (scan_row==num_rows_m1);		assign last_row= (scan_row==num_rows_m1);
	assign enable_act= first_col \|\| !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)		assign enable_act= first_col \|\| !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)
	@@ -235,7 +237,8 @@ module cmd_encod_tiled_rd #(

	if (rst) enable_autopre <= 0;		if (rst) enable_autopre <= 0;
	else if (start_d) enable_autopre <= 0;		else if (start_d) enable_autopre <= 0;
	else if (pre_act) enable_autopre <= last_col_d \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column		// else if (pre_act) enable_autopre <= last_col_d \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
			else if (pre_act) enable_autopre <= last_col \|\| !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column

	//pre_col_bank		//pre_col_bank
	/*		/*
	@@ -262,7 +265,7 @@ module cmd_encod_tiled_rd #(
	col <= start_col;		col <= start_col;
	bank <= start_bank;		bank <= start_bank;
	rowcol_inc <= rowcol_inc_in;		rowcol_inc <= rowcol_inc_in;
	keep_open <= keep_open_in && (\|num_cols_in_m1[5:3]!=0);		keep_open <= keep_open_in && (\|num_cols_in_m1[5:3] == 0);
	skip_next_page <= skip_next_page_in;		skip_next_page <= skip_next_page_in;
	end		end

	@@ -270,7 +273,7 @@ module cmd_encod_tiled_rd #(
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) rom_r <= 0;		if (rst) rom_r <= 0;
	else case (gen_addr)		else case (gen_addr)
	4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_NOP);		4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
	4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);		4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
	4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	@@ -297,21 +300,8 @@ module cmd_encod_tiled_rd #(
	else enc_done <= enc_wr && !gen_run_d;		else enc_done <= enc_wr && !gen_run_d;

	if (rst) enc_cmd <= 0;		if (rst) enc_cmd <= 0;
	else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause		// else if ((rom_cmd==0) \|\| (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
	{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)		else if (rom_cmd[0] \|\| (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
	done, // end of sequence
	3'b0, // bank (here OK to be any)
	1'b0, // odt_en; // enable ODT
	1'b0, // cke; // disable CKE
	rom_r[ENC_SEL], // sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
	1'b0, // dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
	1'b0, // dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
	1'b0, // dqs_toggle; // enable toggle DQS according to the pattern
	rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
	1'b0, // buf_rd; // connect to external buffer (but only if not paused)
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	else enc_cmd <= func_encode_cmd ( // encode non-NOP command
	rom_cmd[1]? // activate		rom_cmd[1]? // activate
	row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act		row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
	{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},		{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
	@@ -333,6 +323,20 @@ module cmd_encod_tiled_rd #(
	1'b0, // buf_rd; // connect to external buffer (but only if not paused)		1'b0, // buf_rd; // connect to external buffer (but only if not paused)
	rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
	rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
			else enc_cmd <= func_encode_skip ( // encode pause
			{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
			done, // end of sequence
			3'b0, // bank (here OK to be any)
			1'b0, // odt_en; // enable ODT
			1'b0, // cke; // disable CKE
			rom_r[ENC_SEL], // sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
			1'b0, // dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
			1'b0, // dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
			1'b0, // dqs_toggle; // enable toggle DQS according to the pattern
			rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
			rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
			1'b0, // buf_rd; // connect to external buffer (but only if not paused)
			rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
	end		end
	fifo_2regs #(		fifo_2regs #(
	.WIDTH(COLADDR_NUMBER)		.WIDTH(COLADDR_NUMBER)
	@@ -346,77 +350,6 @@ module cmd_encod_tiled_rd #(
	.dout(col_bank) // output[15:0]		.dout(col_bank) // output[15:0]
	);		);

	// move to include?, Yes, after fixing problem with paths
	// move to include?
	`include "includes/x393_mcontr_encode_cmd.vh"		`include "includes/x393_mcontr_encode_cmd.vh"
	/*
	function [31:0] func_encode_skip;
	input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
	input done; // end of sequence
	input [2:0] bank; // bank (here OK to be any)
	input odt_en; // enable ODT
	input cke; // disable CKE
	input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
	input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
	input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
	input dqs_toggle; // enable toggle DQS according to the pattern
	input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)
	input buf_rst; // connect to external buffer (but only if not paused)
	begin
	func_encode_skip= func_encode_cmd (
	{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
	bank[2:0], // bank (here OK to be any)
	3'b0, // RAS/CAS/WE, positive logic
	odt_en, // enable ODT
	cke, // disable CKE
	sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
	dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
	dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
	dqs_toggle, // enable toggle DQS according to the pattern
	dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // connect to external buffer (but only if not paused)
	1'b0, // nop
	buf_rst);
	end
	endfunction

	function [31:0] func_encode_cmd;
	input [14:0] addr; // 15-bit row/column adderss
	input [2:0] bank; // bank (here OK to be any)
	input [2:0] rcw; // RAS/CAS/WE, positive logic
	input odt_en; // enable ODT
	input cke; // disable CKE
	input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
	input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
	input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
	input dqs_toggle; // enable toggle DQS according to the pattern
	input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)
	input nop; // add NOP after the current command, keep other data
	input buf_rst; // connect to external buffer (but only if not paused)
	begin
	func_encode_cmd={
	addr[14:0], // 15-bit row/column adderss
	bank [2:0], // bank
	rcw[2:0], // RAS/CAS/WE
	odt_en, // enable ODT
	cke, // may be optimized (removed from here)?
	sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
	dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
	dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
	dqs_toggle, // enable toggle DQS according to the pattern
	dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
	nop, // add NOP after the current command, keep other data
	buf_rst // Reserved for future use
	};
	end
	endfunction
	*/
	endmodule		endmodule

memctrl/mcntrl393.v

+4 −1

memctrl/mcntrl393_test01.v

+19 −3

Original line number	Original line	Diff line number	Diff line
	@@ -108,6 +108,9 @@ module mcntrl393_test01#(
	reg frame_busy_chn2;		reg frame_busy_chn2;
	reg frame_busy_chn3;		reg frame_busy_chn3;
	reg frame_busy_chn4;		reg frame_busy_chn4;
			reg frame_finished_chn2;
			reg frame_finished_chn3;
			reg frame_finished_chn4;

	assign frame_start_chn2 = frame_start_chn2_r;		assign frame_start_chn2 = frame_start_chn2_r;
	assign frame_start_chn3 = frame_start_chn3_r;		assign frame_start_chn3 = frame_start_chn3_r;
	@@ -118,9 +121,9 @@ module mcntrl393_test01#(
	assign suspend_chn2 = suspend_chn2_r;		assign suspend_chn2 = suspend_chn2_r;
	assign suspend_chn3 = suspend_chn3_r;		assign suspend_chn3 = suspend_chn3_r;
	assign suspend_chn4 = suspend_chn4_r;		assign suspend_chn4 = suspend_chn4_r;
	assign status_chn2={page_chn2,line_unfinished_chn2,frame_busy_chn2, frame_busy_chn2};		assign status_chn2={page_chn2,line_unfinished_chn2,frame_finished_chn2, frame_busy_chn2};
	assign status_chn3={page_chn3,line_unfinished_chn3,frame_busy_chn3, frame_busy_chn3};		assign status_chn3={page_chn3,line_unfinished_chn3,frame_finished_chn3, frame_busy_chn3};
	assign status_chn4={page_chn4,line_unfinished_chn4,frame_busy_chn4, frame_busy_chn4};		assign status_chn4={page_chn4,line_unfinished_chn4,frame_finished_chn4, frame_busy_chn4};

	always @ (posedge mclk) begin		always @ (posedge mclk) begin
	frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;		frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
	@@ -164,6 +167,19 @@ module mcntrl393_test01#(
	if (rst) frame_busy_chn4 <= 0;		if (rst) frame_busy_chn4 <= 0;
	else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;		else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;
	else if (!frame_start_chn4_r && frame_done_chn4) frame_busy_chn4 <= 0;		else if (!frame_start_chn4_r && frame_done_chn4) frame_busy_chn4 <= 0;

			if (rst) frame_finished_chn2 <= 0;
			else if ( frame_start_chn2_r && !frame_done_chn2) frame_finished_chn2 <= 0;
			else if (!frame_start_chn2_r && frame_done_chn2) frame_finished_chn2 <= 1;

			if (rst) frame_finished_chn3 <= 0;
			else if ( frame_start_chn3_r && !frame_done_chn3) frame_finished_chn3 <= 0;
			else if (!frame_start_chn3_r && frame_done_chn3) frame_finished_chn3 <= 1;

			if (rst) frame_finished_chn4 <= 0;
			else if ( frame_start_chn4_r && !frame_done_chn4) frame_finished_chn4 <= 0;
			else if (!frame_start_chn4_r && frame_done_chn4) frame_finished_chn4 <= 1;

	end		end

	always @ (posedge mclk) begin		always @ (posedge mclk) begin

memctrl/mcntrl_linear_rw.v

+13 −9

Original line number	Original line	Diff line number	Diff line
	@@ -60,6 +60,7 @@ module mcntrl_linear_rw #(
	input next_page, // page was read/written from/to 4*1kB on-chip buffer		input next_page, // page was read/written from/to 4*1kB on-chip buffer
	// output page_ready, // == xfer_done, connect externally \| Single-cycle pulse indicating that a page was read/written from/to DDR3 memory		// output page_ready, // == xfer_done, connect externally \| Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
	output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory		output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
			output frame_finished,// turns on and stays on after frame_done
	// optional I/O for channel synchronization		// optional I/O for channel synchronization
	output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.		output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
	input suspend, // suspend transfers (from external line number comparator)		input suspend, // suspend transfers (from external line number comparator)
	@@ -124,6 +125,7 @@ module mcntrl_linear_rw #(
	reg want_r;		reg want_r;
	reg need_r;		reg need_r;
	reg frame_done_r;		reg frame_done_r;
			reg frame_finished_r;
	wire last_in_row_w;		wire last_in_row_w;
	wire last_row_w;		wire last_row_w;
	reg last_block;		reg last_block;
	@@ -172,7 +174,7 @@ module mcntrl_linear_rw #(
	assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_WH);		assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_WH);
	assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_X0Y0);		assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_X0Y0);
	assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_STARTXY);		assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_STARTXY);
	// Sett parameter registers		// Set parameter registers
	always @(posedge rst or posedge mclk) begin		always @(posedge rst or posedge mclk) begin
	if (rst) mode_reg <= 0;		if (rst) mode_reg <= 0;
	else if (set_mode_w) mode_reg <= cmd_data[3:0]; // [4:0];		else if (set_mode_w) mode_reg <= cmd_data[3:0]; // [4:0];
	@@ -217,6 +219,8 @@ module mcntrl_linear_rw #(
	assign xfer_partial= xfer_limited_by_mem_page_r;		assign xfer_partial= xfer_limited_by_mem_page_r;

	assign frame_done= frame_done_r;		assign frame_done= frame_done_r;
			assign frame_finished= frame_finished_r;

	assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;		assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
	// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;		// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;
	//		//
	@@ -232,7 +236,7 @@ module mcntrl_linear_rw #(
	assign chn_rst = ~mode_reg[0]; // resets command, including fifo;		assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
	assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page		assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
	// assign cmd_wrmem = mode_reg[4];// 0: read from memory, 1:write to memory		// assign cmd_wrmem = mode_reg[4];// 0: read from memory, 1:write to memory
	assign status_data= {frame_done, busy_r}; // TODO: Add second bit?		assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
	assign pgm_param_w= cmd_we;		assign pgm_param_w= cmd_we;
	localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;		localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
	assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;		assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
	@@ -347,14 +351,14 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
	else if (frame_start) continued_xfer <= 1'b0;		else if (frame_start) continued_xfer <= 1'b0;
	else if (xfer_start_r[0]) continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change		else if (xfer_start_r[0]) continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change

			// single cycle (sent out)
	if (rst) frame_done_r <= 0;		if (rst) frame_done_r <= 0;
	else if (chn_rst \|\| frame_start) frame_done_r <= 0;		else frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
	else if (busy_r && last_block && xfer_done_d && (pending_xfers==0)) frame_done_r <= 1;

	// if (rst) frame_done_r <= 0;
	// else frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);


			// turns and stays on (used in status)
			if (rst) frame_finished_r <= 0;
			else if (chn_rst \|\| frame_start) frame_finished_r <= 0;
			else if (frame_done_r) frame_finished_r <= 1;

	if (rst) xfer_start_r <= 0;		if (rst) xfer_start_r <= 0;
	else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};		else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};

Original line number	Original line	Diff line number	Diff line
	@@ -673,6 +673,7 @@ module mcntrl393 #(
	.frame_start (frame_start_chn4), // input		.frame_start (frame_start_chn4), // input
	.next_page (next_page_chn4), // input		.next_page (next_page_chn4), // input
	.frame_done (frame_done_chn4), // output		.frame_done (frame_done_chn4), // output
			.frame_finished (), // output
	.line_unfinished (line_unfinished_chn4), // output[15:0]		.line_unfinished (line_unfinished_chn4), // output[15:0]
	.suspend (suspend_chn4), // input		.suspend (suspend_chn4), // input
	.xfer_want (want_rq4), // output		.xfer_want (want_rq4), // output
	@@ -830,6 +831,7 @@ module mcntrl393 #(
	.frame_start (frame_start_chn2), // input		.frame_start (frame_start_chn2), // input
	.next_page (next_page_chn2), // input		.next_page (next_page_chn2), // input
	.frame_done (frame_done_chn2), // output		.frame_done (frame_done_chn2), // output
			.frame_finished (), // output
	.line_unfinished (line_unfinished_chn2), // output[15:0]		.line_unfinished (line_unfinished_chn2), // output[15:0]
	.suspend (suspend_chn2), // input		.suspend (suspend_chn2), // input
	.xfer_want (want_rq2), // output		.xfer_want (want_rq2), // output
	@@ -874,6 +876,7 @@ module mcntrl393 #(
	.frame_start (frame_start_chn3), // input		.frame_start (frame_start_chn3), // input
	.next_page (next_page_chn3), // input		.next_page (next_page_chn3), // input
	.frame_done (frame_done_chn3), // output		.frame_done (frame_done_chn3), // output
			.frame_finished (), // output
	.line_unfinished (line_unfinished_chn3), // output[15:0]		.line_unfinished (line_unfinished_chn3), // output[15:0]
	.suspend (suspend_chn3), // input		.suspend (suspend_chn3), // input
	.xfer_want (want_rq3), // output		.xfer_want (want_rq3), // output

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