more debugging tile read

memctrl/cmd_encod_tiled_rd.v

@@ -34,9 +34,10 @@ Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank
 Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
 Can read less if just one column
 TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary
-
 number fo rows>1!
 
+Need to insert pauses if activate in the first row and  next column is too early
+
 */
 
 module  cmd_encod_tiled_rd #(
@@ -151,9 +152,10 @@ module  cmd_encod_tiled_rd #(
                                 
 
     assign     pre_done=rom_r[ENC_PRE_DONE] && gen_run;
-    assign     rom_cmd=  rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
+//    assign     rom_cmd=  rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
+    assign     rom_cmd=  rom_r[ENC_CMD_SHIFT+:2]; //  & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
     assign     rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
-    assign     full_cmd= rom_cmd[1]?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);
+    assign     full_cmd= (enable_act && rom_cmd[1])?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);
     
     assign last_row=       (scan_row==num_rows_m1);
     assign enable_act=     first_col || !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)
@@ -235,7 +237,8 @@ module  cmd_encod_tiled_rd #(
 
         if (rst)                      enable_autopre <= 0;
         else if (start_d)             enable_autopre <= 0;
-        else if (pre_act)             enable_autopre <=  last_col_d || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
+//        else if (pre_act)             enable_autopre <=  last_col_d || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
+        else if (pre_act)             enable_autopre <=  last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
         
 //pre_col_bank   
 /*     
@@ -262,7 +265,7 @@ module  cmd_encod_tiled_rd #(
         col <= start_col;
         bank <= start_bank;
         rowcol_inc <= rowcol_inc_in;
-        keep_open <= keep_open_in && (|num_cols_in_m1[5:3]!=0);
+        keep_open <= keep_open_in && (|num_cols_in_m1[5:3] == 0);
         skip_next_page <= skip_next_page_in;
     end
     
@@ -270,7 +273,7 @@ module  cmd_encod_tiled_rd #(
     always @ (posedge rst or posedge clk) begin
         if (rst)           rom_r <= 0;
         else case (gen_addr)
-            4'h0: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT)  | (1 << ENC_NOP);
+            4'h0: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT)  | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
             4'h1: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT); 
             4'h2: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                                              | (1 << ENC_DCI) | (1 << ENC_SEL); 
             4'h3: rom_r <= (ENC_CMD_ACTIVATE <<  ENC_CMD_SHIFT)                                              | (1 << ENC_DCI) | (1 << ENC_SEL); 
@@ -297,21 +300,8 @@ module  cmd_encod_tiled_rd #(
         else               enc_done <= enc_wr && !gen_run_d;
         
         if (rst)             enc_cmd <= 0;
-        else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
-            {{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip;   // number of extra cycles to skip (and keep all the other outputs)
-            done,                                     // end of sequence 
-            3'b0,                    // bank (here OK to be any)
-            1'b0,                    //   odt_en;     // enable ODT
-            1'b0,                    //   cke;        // disable CKE
-            rom_r[ENC_SEL],          //   sel;        // first/second half-cycle, other will be nop (cke+odt applicable to both)
-            1'b0,                    //   dq_en;      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
-            1'b0,                    //   dqs_en;     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
-            1'b0,                    //   dqs_toggle; // enable toggle DQS according to the pattern
-            rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-            rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
-            1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)
-            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
-       else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
+//        else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
+        else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]? // activate
             row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
                     {{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
@@ -333,7 +323,21 @@ module  cmd_encod_tiled_rd #(
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)     
             rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
             rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
-    end    
+        else enc_cmd <= func_encode_skip ( // encode pause
+            {{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip;   // number of extra cycles to skip (and keep all the other outputs)
+            done,                                     // end of sequence 
+            3'b0,                    // bank (here OK to be any)
+            1'b0,                    //   odt_en;     // enable ODT
+            1'b0,                    //   cke;        // disable CKE
+            rom_r[ENC_SEL],          //   sel;        // first/second half-cycle, other will be nop (cke+odt applicable to both)
+            1'b0,                    //   dq_en;      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
+            1'b0,                    //   dqs_en;     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
+            1'b0,                    //   dqs_toggle; // enable toggle DQS according to the pattern
+            rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+            rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
+            1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
+          end    
     fifo_2regs #(
         .WIDTH(COLADDR_NUMBER)
     ) fifo_2regs_i (
@@ -346,77 +350,6 @@ module  cmd_encod_tiled_rd #(
         .dout(col_bank) // output[15:0] 
     );
 
-// move to include?, Yes, after fixing problem with paths
-// move to include?
 `include "includes/x393_mcontr_encode_cmd.vh" 
-/*
-    function [31:0] func_encode_skip;
-        input [CMD_PAUSE_BITS-1:0] skip;       // number of extra cycles to skip (and keep all the other outputs)
-        input                      done;       // end of sequence 
-        input [2:0]                bank;       // bank (here OK to be any)
-        input                      odt_en;     // enable ODT
-        input                      cke;        // disable CKE
-        input                      sel;        // first/second half-cycle, other will be nop (cke+odt applicable to both)
-        input                      dq_en;      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
-        input                      dqs_en;     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
-        input                      dqs_toggle; // enable toggle DQS according to the pattern
-        input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-        input                      buf_wr;     // connect to external buffer (but only if not paused)
-        input                      buf_rd;     // connect to external buffer (but only if not paused)
-        input                      buf_rst;    // connect to external buffer (but only if not paused)
-        begin
-            func_encode_skip= func_encode_cmd (
-                {{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]},       // 15-bit row/column adderss
-                bank[2:0],  // bank (here OK to be any)
-                3'b0,       // RAS/CAS/WE, positive logic
-                odt_en,     // enable ODT
-                cke,        // disable CKE
-                sel,        // first/second half-cycle, other will be nop (cke+odt applicable to both)
-                dq_en,      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
-                dqs_en,     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
-                dqs_toggle, // enable toggle DQS according to the pattern
-                dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-                buf_wr,     // connect to external buffer (but only if not paused)
-                buf_rd,     // connect to external buffer (but only if not paused)
-                1'b0,       // nop
-                buf_rst);
-        end
-    endfunction
-
-    function [31:0] func_encode_cmd;
-        input               [14:0] addr;       // 15-bit row/column adderss
-        input                [2:0] bank;       // bank (here OK to be any)
-        input                [2:0] rcw;        // RAS/CAS/WE, positive logic
-        input                      odt_en;     // enable ODT
-        input                      cke;        // disable CKE
-        input                      sel;        // first/second half-cycle, other will be nop (cke+odt applicable to both)
-        input                      dq_en;      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
-        input                      dqs_en;     // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
-        input                      dqs_toggle; // enable toggle DQS according to the pattern
-        input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-        input                      buf_wr;     // connect to external buffer (but only if not paused)
-        input                      buf_rd;     // connect to external buffer (but only if not paused)
-        input                      nop;        // add NOP after the current command, keep other data
-        input                      buf_rst;    // connect to external buffer (but only if not paused)
-        begin
-            func_encode_cmd={
-            addr[14:0], // 15-bit row/column adderss
-            bank [2:0], // bank
-            rcw[2:0],   // RAS/CAS/WE
-            odt_en,     // enable ODT
-            cke,        // may be optimized (removed from here)?
-            sel,        // first/second half-cycle, other will be nop (cke+odt applicable to both)
-            dq_en,      // enable (not tristate) DQ  lines (internal timing sequencer for 0->1 and 1->0)
-            dqs_en,     // enable (not tristate) DQS  lines (internal timing sequencer for 0->1 and 1->0)
-            dqs_toggle, // enable toggle DQS according to the pattern
-            dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-            buf_wr,     // phy_buf_wr,   // connect to external buffer (but only if not paused)
-            buf_rd,     // phy_buf_rd,    // connect to external buffer (but only if not paused)
-            nop,        // add NOP after the current command, keep other data
-            buf_rst     // Reserved for future use
-           };
-        end
-    endfunction
-*/
 endmodule
 

memctrl/mcntrl393.v

@@ -662,7 +662,7 @@ module  mcntrl393 #(
         .MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
         .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
         .MCNTRL_TILED_WRITE_MODE       (1'b0)
-    ) mcntrl_tiled_rw_chn4_i (
+    ) mcntrl_tiled_rw_chn4_i ( 
         .rst(rst), // input
         .mclk(mclk), // input
         .cmd_ad               (cmd_tiled_chn4_ad), // input[7:0] 
@@ -673,6 +673,7 @@ module  mcntrl393 #(
         .frame_start          (frame_start_chn4), // input
         .next_page            (next_page_chn4), // input
         .frame_done           (frame_done_chn4), // output
+        .frame_finished       (), // output
         .line_unfinished      (line_unfinished_chn4), // output[15:0] 
         .suspend              (suspend_chn4), // input
         .xfer_want            (want_rq4), // output
@@ -830,6 +831,7 @@ module  mcntrl393 #(
         .frame_start       (frame_start_chn2), // input
         .next_page         (next_page_chn2), // input
         .frame_done        (frame_done_chn2), // output
+        .frame_finished    (), // output
         .line_unfinished   (line_unfinished_chn2), // output[15:0] 
         .suspend           (suspend_chn2), // input
         .xfer_want       (want_rq2), // output
@@ -874,6 +876,7 @@ module  mcntrl393 #(
         .frame_start      (frame_start_chn3), // input
         .next_page        (next_page_chn3), // input
         .frame_done       (frame_done_chn3), // output
+        .frame_finished       (), // output
         .line_unfinished  (line_unfinished_chn3), // output[15:0] 
         .suspend          (suspend_chn3), // input
         .xfer_want       (want_rq3), // output

memctrl/mcntrl393_test01.v

@@ -108,6 +108,9 @@ module  mcntrl393_test01#(
     reg         frame_busy_chn2;
     reg         frame_busy_chn3;
     reg         frame_busy_chn4;
+    reg         frame_finished_chn2;
+    reg         frame_finished_chn3;
+    reg         frame_finished_chn4;
     
     assign frame_start_chn2 = frame_start_chn2_r;    
     assign frame_start_chn3 = frame_start_chn3_r;    
@@ -118,9 +121,9 @@ module  mcntrl393_test01#(
     assign suspend_chn2 = suspend_chn2_r;
     assign suspend_chn3 = suspend_chn3_r;
     assign suspend_chn4 = suspend_chn4_r;
-    assign status_chn2={page_chn2,line_unfinished_chn2,frame_busy_chn2, frame_busy_chn2};
-    assign status_chn3={page_chn3,line_unfinished_chn3,frame_busy_chn3, frame_busy_chn3};
-    assign status_chn4={page_chn4,line_unfinished_chn4,frame_busy_chn4, frame_busy_chn4};
+    assign status_chn2={page_chn2,line_unfinished_chn2,frame_finished_chn2, frame_busy_chn2};
+    assign status_chn3={page_chn3,line_unfinished_chn3,frame_finished_chn3, frame_busy_chn3};
+    assign status_chn4={page_chn4,line_unfinished_chn4,frame_finished_chn4, frame_busy_chn4};
 
     always @ (posedge mclk) begin
         frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
@@ -164,6 +167,19 @@ module  mcntrl393_test01#(
         if      (rst)                                     frame_busy_chn4 <= 0;
         else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;
         else if (!frame_start_chn4_r &&  frame_done_chn4) frame_busy_chn4 <= 0;
+        
+        if      (rst)                                     frame_finished_chn2 <= 0;
+        else if ( frame_start_chn2_r && !frame_done_chn2) frame_finished_chn2 <= 0;
+        else if (!frame_start_chn2_r &&  frame_done_chn2) frame_finished_chn2 <= 1;
+
+        if      (rst)                                     frame_finished_chn3 <= 0;
+        else if ( frame_start_chn3_r && !frame_done_chn3) frame_finished_chn3 <= 0;
+        else if (!frame_start_chn3_r &&  frame_done_chn3) frame_finished_chn3 <= 1;
+
+        if      (rst)                                     frame_finished_chn4 <= 0;
+        else if ( frame_start_chn4_r && !frame_done_chn4) frame_finished_chn4 <= 0;
+        else if (!frame_start_chn4_r &&  frame_done_chn4) frame_finished_chn4 <= 1;
+        
     end
     
     always @ (posedge mclk) begin

memctrl/mcntrl_linear_rw.v

@@ -60,6 +60,7 @@ module  mcntrl_linear_rw #(
     input                          next_page,     // page was read/written from/to 4*1kB on-chip buffer
 //    output                         page_ready,    // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
     output                         frame_done,    // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
+    output                         frame_finished,// turns on and stays on after frame_done
 // optional I/O for channel synchronization
     output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?. 
     input                          suspend,       // suspend transfers (from external line number comparator)
@@ -124,6 +125,7 @@ module  mcntrl_linear_rw #(
     reg                           want_r;
     reg                           need_r;
     reg                           frame_done_r;
+    reg                           frame_finished_r;    
     wire                          last_in_row_w;
     wire                          last_row_w;
     reg                           last_block;
@@ -172,7 +174,7 @@ module  mcntrl_linear_rw #(
     assign set_window_wh_w =    cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_WH);
     assign set_window_x0y0_w =  cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_X0Y0);
     assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_STARTXY);
-    // Sett parameter registers
+    // Set parameter registers
     always @(posedge rst or posedge mclk) begin
         if      (rst)                mode_reg <= 0;
         else if (set_mode_w)         mode_reg <= cmd_data[3:0]; // [4:0];
@@ -217,6 +219,8 @@ module  mcntrl_linear_rw #(
     assign xfer_partial=      xfer_limited_by_mem_page_r;
     
     assign frame_done=  frame_done_r;
+    assign frame_finished=  frame_finished_r;
+    
     assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
 //    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;
     //
@@ -232,7 +236,7 @@ module  mcntrl_linear_rw #(
     assign chn_rst =        ~mode_reg[0]; // resets command, including fifo;
     assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
 //    assign cmd_wrmem =       mode_reg[4];// 0: read from memory, 1:write to memory
-    assign status_data= {frame_done, busy_r};     // TODO: Add second bit?
+    assign status_data= {frame_finished_r, busy_r};     // TODO: Add second bit?
     assign pgm_param_w=      cmd_we;
     localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
     assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
@@ -347,14 +351,14 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
         else if (frame_start)      continued_xfer <= 1'b0;
         else if (xfer_start_r[0])  continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
 
-        if      (rst)                                                       frame_done_r <= 0;
-        else if (chn_rst || frame_start)                                    frame_done_r <= 0;
-        else if (busy_r && last_block && xfer_done_d && (pending_xfers==0)) frame_done_r <= 1;
+        // single cycle (sent out)
+        if (rst)          frame_done_r <= 0;
+        else              frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
 
-//        if (rst)          frame_done_r <= 0;
-//        else              frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
-        
-        
+        // turns and stays on (used in status)
+        if (rst)                         frame_finished_r <= 0;
+        else if (chn_rst || frame_start) frame_finished_r <= 0;
+        else if (frame_done_r)           frame_finished_r <= 1;
         
         if (rst) xfer_start_r <= 0;
         else     xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};

memctrl/mcntrl_tiled_rw.v

@@ -64,6 +64,7 @@ module  mcntrl_tiled_rw#(
     input                          next_page,     // page was read/written from/to 4*1kB on-chip buffer
 //    output                         page_ready,    // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
     output                         frame_done,    // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
+    output                         frame_finished,// turns on and stays on after frame_done
 // optional I/O for channel synchronization
     output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?. 
     input                          suspend,       // suspend transfers (from external line number comparator)
@@ -82,6 +83,8 @@ module  mcntrl_tiled_rw#(
     input                          xfer_page_done,     // transfer to/from the buffer finished (partial transfers should not generate), use rpage_nxt_chn@mclk
     output                         xfer_page_rst // reset buffer internal page - at each frame start or when specifically reset
 );
+// FIXME: not all tile heights are valid (because of the banks)
+
 //MAX_TILE_WIDTH
     localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3;  //to spcify row and col8 == 22
     localparam MPY_WIDTH=        NUM_RC_BURST_BITS; // 22
@@ -126,6 +129,7 @@ module  mcntrl_tiled_rw#(
     reg                           want_r;
     reg                           need_r;
     reg                           frame_done_r;
+    reg                           frame_finished_r;    
     wire                          last_in_row_w;
     wire                          last_row_w;
     reg                           last_block;
@@ -174,6 +178,7 @@ module  mcntrl_tiled_rw#(
     reg   [FRAME_HEIGHT_BITS-1:0] window_y0;      // (programmed) window top
     reg    [FRAME_WIDTH_BITS-1:0] start_x;        // (programmed) normally 0, copied to curr_x on frame_start  
     reg   [FRAME_HEIGHT_BITS-1:0] start_y;        // (programmed) normally 0, copied to curr_y on frame_start 
+    reg                           xfer_page_done_d;   // next cycle after xfer_page_done
     
     
     assign set_mode_w =         cmd_we && (cmd_a== MCNTRL_TILED_MODE);
@@ -234,11 +239,15 @@ module  mcntrl_tiled_rw#(
     assign mul_rslt_w=  frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
     assign xfer_start=  xfer_start_r[0];
     assign calc_valid=  par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
-    assign frame_done=  frame_done_r;
+    assign frame_done=      frame_done_r;
+    assign frame_finished=  frame_finished_r;
     assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
     assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
 //    assign last_row_w=  next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors
-    assign last_row_w=  next_y > window_m_tile_height; // (next_y==window_height) is faster, but will not forgive software errors
+// tiles must completely fit window
+//    assign last_row_w=  next_y > window_m_tile_height; // (next_y==window_height) is faster, but will not forgive software errors
+// all window should be covered (tiles may extend):    
+    assign last_row_w=  next_y>=window_height;
     //window_m_tile_height
     assign xfer_want=   want_r;
     assign xfer_need=   need_r;
@@ -252,7 +261,7 @@ module  mcntrl_tiled_rw#(
     assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
     assign keep_open=        mode_reg[4]; // keep banks open (will be used only if number of rows <= 8 
 //    assign cmd_wrmem =       mode_reg[5];// 0: read from memory, 1:write to memory
-    assign status_data=      {frame_done, busy_r}; 
+    assign status_data=      {frame_finished_r, busy_r}; 
     assign pgm_param_w=      cmd_we;
     assign rowcol_inc=       frame_full_width;
     assign num_cols_m1_w=    num_cols_r-1;
@@ -263,14 +272,14 @@ module  mcntrl_tiled_rw#(
     
 //    assign buf_skip_reset=   continued_tile; // buf_skip_reset_r;
     assign xfer_page_rst=   xfer_page_rst_r;
-    assign xfer_partial=      xfer_limited_by_mem_page_r;
+    assign xfer_partial=    xfer_limited_by_mem_page_r;
     
     integer i;
 //    localparam EXTRA_BITS={COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}};
     localparam [COLADDR_NUMBER-3-MAX_TILE_WIDTH-1:0] EXTRA_BITS=0;
     wire xfer_limited_by_mem_page;
     reg  xfer_limited_by_mem_page_r;
-    assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_tile_width};
+    assign xfer_limited_by_mem_page= keep_open && (mem_page_left < {EXTRA_BITS,lim_by_tile_width}); // if not keep_open - no need to break
     always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
     // cycle 1
         if (recalc_r[0]) begin
@@ -297,10 +306,7 @@ module  mcntrl_tiled_rw#(
             bank_reg[i+1] <= bank_reg[i];
      
         if (recalc_r[6]) begin    // cycle 7
-//            mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
             mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];
-            
-//            lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH])?(1<<MAX_TILE_WIDTH):row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
             lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH] || (row_left[MAX_TILE_WIDTH:0]>= tile_cols))?
                                     tile_cols:
                                     row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
@@ -312,11 +318,7 @@ module  mcntrl_tiled_rw#(
                 {EXTRA_BITS,leftover_cols}:
                 (xfer_limited_by_mem_page? mem_page_left[MAX_TILE_WIDTH:0]:lim_by_tile_width[MAX_TILE_WIDTH:0]);
                 leftover_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
-//            remainder_tile_width <= {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
         end
-// VDT bug? next line gives a warning        
-//        xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
-   // cycle 4
         if (recalc_r[8]) begin    // cycle 9
             last_in_row <= last_in_row_w;
         end
@@ -345,6 +347,9 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
         else if (frame_start)  busy_r <= 1;
         else if (frame_done_r) busy_r <= 0;
         
+        if (rst) xfer_page_done_d <= 0;
+        else     xfer_page_done_d <= xfer_page_done;
+        
         if (rst) xfer_start_r <= 0;
         else     xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
         
@@ -365,8 +370,8 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
         else if (frame_start)                      page_cntr <= cmd_wrmem?0:4;
 //        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;     
 //        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr - 1;
-        else if ( start_not_partial && !next_page) page_cntr <= page_cntr + 1;     
-        else if (!start_not_partial &&  next_page) page_cntr <= page_cntr - 1;
+        else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;     
+        else if (!start_not_partial &&  next_page) page_cntr <= page_cntr + 1;
         
         if (rst) xfer_page_rst_r <= 1;
         else     xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? frame_start:1'b0);
@@ -394,8 +399,14 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
 //        else if ( start_not_partial && !xfer_page_done) pending_xfers <= pending_xfers + 1;     
 //        else if (!start_not_partial &&  xfer_page_done) pending_xfers <= pending_xfers - 1; // page done is not generated on partial (first) pages
         
+        // single cycle (sent out)
         if (rst)          frame_done_r <= 0;
-        else              frame_done_r <= busy_r && last_block && xfer_page_done && (pending_xfers==0);
+        else              frame_done_r <= busy_r && last_block && xfer_page_done_d && (pending_xfers==0);
+
+        // turns and stays on (used in status)
+        if (rst)                         frame_finished_r <= 0;
+        else if (chn_rst || frame_start) frame_finished_r <= 0;
+        else if (frame_done_r)           frame_finished_r <= 1;
         
         //line_unfinished_r cmd_wrmem
 /*

x393_testbench01.sav

 [*]
 [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
-[*] Wed Feb 18 07:37:00 2015
+[*] Thu Feb 19 00:22:31 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150218002858125.lxt"
-[dumpfile_mtime] "Wed Feb 18 07:36:06 2015"
-[dumpfile_size] 380535673
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150218163406252.lxt"
+[dumpfile_mtime] "Wed Feb 18 23:51:24 2015"
+[dumpfile_size] 990238054
 [savefile] "/home/andrey/git/x393/x393_testbench01.sav"
-[timestart] 55744200
+[timestart] 46460000
 [size] 1823 1180
 [pos] 1927 0
-*-16.698502 56050000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-21.698502 56251875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench01.
 [treeopen] x393_testbench01.x393_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.
@@ -31,7 +32,7 @@
 [signals_width] 369
 [sst_expanded] 1
 [sst_vpaned_height] 383
-@c00200
+@800200
 -top_simulation
 @28
 x393_testbench01.CLK[0]
@@ -150,6 +151,7 @@ x393_testbench01.wait_status_condition.status_control_address[29:0]
 x393_testbench01.wait_status_condition.status_mode[1:0]
 @1401200
 -WAIT_STATUS_CONDITION
+@1000200
 -top_simulation
 @c00200
 -axi
@@ -1335,7 +1337,11 @@ x393_testbench01.x393_i.mcntrl393_i.axird_rdata[31:0]
 x393_testbench01.x393_i.mcntrl_axird_rdata[31:0]
 @28
 x393_testbench01.x393_i.mcntrl_axird_selected[0]
-@c00201
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_not_partial[0]
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_page[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.page_cntr[2:0]
+@c00200
 -ch4_4
 @22
 x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.data_in[63:0]
@@ -1359,7 +1365,7 @@ x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.wpage_in[1:0]
 x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.wpage_set[0]
 @22
 x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ram_512x64w_1kx32r_i.waddr[8:0]
-@1401201
+@1401200
 -ch4_4
 @28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_en[0]
@@ -1369,6 +1375,11 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
 @28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0]
+@23
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_m_tile_height[16:0]
+@28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pre_want[0]
@@ -1487,6 +1498,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_y[15:0]
 @28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done_r[0]
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_finished[0]
 @22
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width[13:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width_r[13:0]
@@ -1617,6 +1629,8 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0]
 -gtiled_ch4
 @c00200
 -encod_tiled
+@22
+x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
 @28
 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start[0]
 @22
@@ -1634,6 +1648,9 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.skip_next_page[0]
 @28
 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_d[0]
 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_run[0]
+x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col[0]
+x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col_d[0]
+x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enable_autopre[0]
 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_act[0]
 x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_read[0]
 @22

x393_testbench01.tf

@@ -202,7 +202,7 @@ module  x393_testbench01 #(
   localparam       WINDOW_WIDTH=    'h000b; //'h005b; //'h000b;  // 176:  13-bit window width (0->'h4000)
   localparam       WINDOW_HEIGHT=   'h000a;  // 9:    16-bit window height (0->'h10000)
 //  localparam       SCANLINE_X0Y0=       'h00050003;  // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
-  localparam       WINDOW_X0=         'h005c; // 'h7c; // 'h0003;  // X0=3*16=48 - 13-bit window left
+  localparam       WINDOW_X0=     'h5c; //'h7f; //     'h005c; // 'h7c; // 'h0003;  // X0=3*16=48 - 13-bit window left
   localparam       WINDOW_Y0=         'h0005;  // Y0=5: 16-bit window top
 //  localparam       SCANLINE_STARTXY=    'h0;         // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
   localparam       SCANLINE_STARTX=     'h0;         // 13-bit start X (relative to window), high word (normally 0)
@@ -212,9 +212,11 @@ module  x393_testbench01 #(
   localparam       TILED_STARTX=     'h0;         // 13-bit start X (relative to window), high word (normally 0)
   localparam       TILED_STARTY=     'h0;         // 16-bit start y (normally 0)
   localparam [1:0] TILED_EXTRA_PAGES= 0;          // 0..2 - number of pages in the buffer to keep/not write
-  localparam       TILED_KEEP_OPEN=   1'b0;       // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)  
+  
+  localparam       TILED_KEEP_OPEN=   1'b0; //1'b1; // 1'b0;       // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)  
+  
   localparam       TILE_WIDTH=    'h03; //     6-bit tile width  (1..'h40)
-  localparam       TILE_HEIGHT=   'h06;  //    6-bit tile height (1..'h40)
+  localparam       TILE_HEIGHT=   'h05; // 'h04; //'h06;  //    6-bit tile height (1..'h40) // 4 - violation
   localparam       TILE_VSTEP=    'h04;  //    6-bit tile vertical step, with no overlap it is equal to TILE_HEIGHT (1..'h40)