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Commit c7ad1d57 authored by Andrey Filippov's avatar Andrey Filippov
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created test fixture with macro define switch between parallel and HiSPi sensors

parent 8c19274c
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Showing with 386 additions and 392 deletions
fpga_version.vh
View file @ c7ad1d57
parameter FPGA_VERSION = 32'h03930042; parameter FPGA_VERSION = 32'h03930050;
\ No newline at end of file \ No newline at end of file
simulation_modules/par12_hispi_psp4l.v
View file @ c7ad1d57
...@@ -107,11 +107,21 @@ module par12_hispi_psp4l#( ...@@ -107,11 +107,21 @@ module par12_hispi_psp4l#(
// generate output clock (normally multiplier first, but in simulation there will be less calculations if division is first) // generate output clock (normally multiplier first, but in simulation there will be less calculations if division is first)
wire oclk; wire oclk;
wire int_clk; // wire int_clk;
wire next_line_oclk; wire next_line_oclk;
wire next_frame_oclk ; wire next_frame_oclk ;
reg orst_r = 1; reg orst_r = 1;
wire orst = rst || orst_r; wire orst = rst || orst_r;
simul_clk_mult_div #(
.MULTIPLIER(CLOCK_MPY),
.DIVISOR(CLOCK_DIV),
.SKIP_FIRST(5)
) simul_clk_div_mult_i (
.clk_in(pclk), // input
.en(1'b1), // input
.clk_out(oclk) // output
);
/*
simul_clk_mult #( simul_clk_mult #(
.MULTIPLIER(CLOCK_MPY) .MULTIPLIER(CLOCK_MPY)
) simul_clk_mult_i ( ) simul_clk_mult_i (
...@@ -127,7 +137,7 @@ module par12_hispi_psp4l#( ...@@ -127,7 +137,7 @@ module par12_hispi_psp4l#(
.en (1'b1), // input .en (1'b1), // input
.clk_out (oclk) // output .clk_out (oclk) // output
); );
*/
pulse_cross_clock #( pulse_cross_clock #(
.EXTRA_DLY(0) .EXTRA_DLY(0)
) pulse_cross_clock_sof_sol_i ( ) pulse_cross_clock_sof_sol_i (
......
simulation_modules/sim_clk_div.v
View file @ c7ad1d57
...@@ -29,7 +29,7 @@ module sim_clk_div#( ...@@ -29,7 +29,7 @@ module sim_clk_div#(
); );
integer cntr = 0; integer cntr = 0;
reg clk_out_r = 0; reg clk_out_r = 0;
assign clk_out = clk_out_r; assign clk_out = (DIVISOR == 1) ? clk_in: clk_out_r;
always @(clk_in) if (en) begin always @(clk_in) if (en) begin
if (cntr == 0) begin if (cntr == 0) begin
cntr = DIVISOR - 1; cntr = DIVISOR - 1;
......
simulation_modules/simul_clk_div_mult.v 0 → 100644
View file @ c7ad1d57
/*******************************************************************************
* Module: simul_clk_div_mult
* Date:2015-10-12
* Author: andrey
* Description: Simulation clock rational multiplier
*
* Copyright (c) 2015 Elphel, Inc .
* simul_clk_div_mult.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_clk_div_mult.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module simul_clk_div_mult#(
parameter MULTIPLIER = 3,
parameter DIVISOR = 5,
parameter SKIP_FIRST = 5
) (
input clk_in,
input en,
output clk_out
);
wire clk_int;
generate
if (DIVISOR > 1)
sim_clk_div #(
.DIVISOR (DIVISOR)
) sim_clk_div_i (
.clk_in (clk_in), // input
.en (en), // input
.clk_out (clk_int) // output
);
else
assign clk_int = clk_in;
endgenerate
generate
if (MULTIPLIER > 1)
simul_clk_mult #(
.MULTIPLIER (MULTIPLIER),
.SKIP_FIRST (SKIP_FIRST)
) simul_clk_mult_i (
.clk_in (clk_int), // input
.en (en), // input
.clk_out (clk_out) // output
);
else
assign clk_out = clk_int;
endgenerate
endmodule
simulation_modules/simul_clk_mult.v
View file @ c7ad1d57
...@@ -34,7 +34,7 @@ module simul_clk_mult#( ...@@ -34,7 +34,7 @@ module simul_clk_mult#(
integer num_period = 0; integer num_period = 0;
reg en1 = 0; reg en1 = 0;
reg clk_out_r = 0; reg clk_out_r = 0;
assign clk_out = clk_out_r; assign clk_out = (MULTIPLIER == 1)? clk_in: clk_out_r;
always @ (posedge clk_in) begin always @ (posedge clk_in) begin
phase = $realtime; phase = $realtime;
if (num_period >= SKIP_FIRST) begin if (num_period >= SKIP_FIRST) begin
......
simulation_modules/simul_clk_mult_div.v 0 → 100644
View file @ c7ad1d57
/*******************************************************************************
* Module: simul_clk_mult_div
* Date:2015-10-12
* Author: andrey
* Description: Simulation clock rational multiplier
*
* Copyright (c) 2015 Elphel, Inc .
* simul_clk_mult_div.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_clk_mult_div.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module simul_clk_mult_div#(
parameter MULTIPLIER = 3,
parameter DIVISOR = 5,
parameter SKIP_FIRST = 5
) (
input clk_in,
input en,
output clk_out
);
wire clk_int;
generate
if (MULTIPLIER > 1)
simul_clk_mult #(
.MULTIPLIER (MULTIPLIER),
.SKIP_FIRST (SKIP_FIRST)
) simul_clk_mult_i (
.clk_in (clk_in), // input
.en (en), // input
.clk_out (clk_int) // output
);
else
assign clk_int = clk_in;
endgenerate
generate
if (DIVISOR > 1)
sim_clk_div #(
.DIVISOR (DIVISOR)
) sim_clk_div_i (
.clk_in (clk_in), // input
.en (en), // input
.clk_out (clk_out) // output
);
else
assign clk_out = clk_int;
endgenerate
endmodule
system_defines.vh
View file @ c7ad1d57
...@@ -2,6 +2,8 @@ ...@@ -2,6 +2,8 @@
`ifndef SYSTEM_DEFINES `ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES `define SYSTEM_DEFINES
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI
// `define DEBUG_RING 1 // `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1 `define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options // Enviroment-dependent options
......
x393_testbench02.sav
View file @ c7ad1d57
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Oct 12 22:20:36 2015 [*] Tue Oct 13 02:08:59 2015
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151012155137508.fst" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151012161611192.fst"
[dumpfile_mtime] "Mon Oct 12 22:13:21 2015" [dumpfile_mtime] "Mon Oct 12 22:50:38 2015"
[dumpfile_size] 76289545 [dumpfile_size] 172697643
[savefile] "/home/andrey/git/x393/x393_testbench02.sav" [savefile] "/home/andrey/git/x393/x393_testbench02.sav"
[timestart] 107560000 [timestart] 0
[size] 1823 1180 [size] 1823 1180
[pos] 1922 0 [pos] 1922 0
*-18.415243 108503491 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-25.149160 71803197 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench02. [treeopen] x393_testbench02.
[treeopen] x393_testbench02.compressor_control. [treeopen] x393_testbench02.compressor_control.
[treeopen] x393_testbench02.par12_hispi_psp4l_i. [treeopen] x393_testbench02.par12_hispi_psp4l_i.
...@@ -193,7 +193,7 @@ x393_testbench02.TEST_TITLE[639:0] ...@@ -193,7 +193,7 @@ x393_testbench02.TEST_TITLE[639:0]
- -
@1401200 @1401200
-debug_ring -debug_ring
@800200 @c00200
-PX1 -PX1
@28 @28
x393_testbench02.simul_sensor12bits_i.MRST x393_testbench02.simul_sensor12bits_i.MRST
...@@ -225,197 +225,8 @@ x393_testbench02.simul_sensor12bits_i.ARO ...@@ -225,197 +225,8 @@ x393_testbench02.simul_sensor12bits_i.ARO
x393_testbench02.simul_sensor12bits_i.DCLK x393_testbench02.simul_sensor12bits_i.DCLK
@28 @28
x393_testbench02.simul_sensor12bits_i.OFST x393_testbench02.simul_sensor12bits_i.OFST
@1000200
-PX1
@800200
-par12_hispi_sel
@28
x393_testbench02.par12_hispi_psp4l_i.rst
x393_testbench02.par12_hispi_psp4l_i.orst
x393_testbench02.par12_hispi_psp4l_i.pclk
x393_testbench02.par12_hispi_psp4l_i.oclk
@22
x393_testbench02.par12_hispi_psp4l_i.pxd[11:0]
@28
x393_testbench02.par12_hispi_psp4l_i.vact
x393_testbench02.par12_hispi_psp4l_i.hact
x393_testbench02.par12_hispi_psp4l_i.next_sof
@22
x393_testbench02.par12_hispi_psp4l_i.fifo_wa[11:0]
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x393_testbench02.par12_hispi_psp4l_i.fifo_we
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x393_testbench02.par12_hispi_psp4l_i.fifo_di[48:0]
x393_testbench02.par12_hispi_psp4l_i.fifo_ra[11:0]
x393_testbench02.par12_hispi_psp4l_i.rdy[3:0]
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x393_testbench02.par12_hispi_psp4l_i.fifo_dav
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x393_testbench02.par12_hispi_psp4l_i.frames_open[1:0]
@28
(0)x393_testbench02.par12_hispi_psp4l_i.frames_open[1:0]
(1)x393_testbench02.par12_hispi_psp4l_i.frames_open[1:0]
@1001200
-group_end
@200
-
@28
x393_testbench02.par12_hispi_psp4l_i.next_frame_pclk
x393_testbench02.par12_hispi_psp4l_i.next_frame_oclk
x393_testbench02.par12_hispi_psp4l_i.next_line_pclk
x393_testbench02.par12_hispi_psp4l_i.next_line_oclk
@22
x393_testbench02.par12_hispi_psp4l_i.lines_available[1:0]
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x393_testbench02.par12_hispi_psp4l_i.line_available
@22
x393_testbench02.par12_hispi_psp4l_i.fifo_out[48:0]
@1000200
-par12_hispi_sel
@200
-
@800200
-hispi_lane0
@22
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.bcntr[3:0]
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x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.clk
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.dav
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.dav_rdy
@22
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.din[12:0]
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.din_filt[11:0]
@28
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.embed
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.is_sync
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.next_line
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.pause
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.rdy
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.rst
@800022
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eof[3:0]
@28
(0)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eof[3:0]
(1)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eof[3:0]
(2)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eof[3:0]
(3)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eof[3:0]
@1001200
-group_end
@800022
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
@28
(0)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(1)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(2)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(3)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(4)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(5)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(6)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
(7)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_eol_sol[7:0]
@1001200
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@800022
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_sof[3:0]
@28
(0)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_sof[3:0]
(1)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_sof[3:0]
(2)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_sof[3:0]
(3)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.seq_sof[3:0]
@1001200
-group_end
@28
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sof_sol_sent
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x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sout
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x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr_in[11:0]
@800022
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(0)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(1)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(2)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(3)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(4)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(5)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(6)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(7)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(8)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(9)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(10)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
(11)x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr[11:0]
@1001200
-group_end
@28
x393_testbench02.par12_hispi_psp4l_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.sr_in_av
@1000200
-hispi_lane0
@800200
-par12_hspi
@28
x393_testbench02.par12_hispi_psp4l_i.clk_n
x393_testbench02.par12_hispi_psp4l_i.clk_p
x393_testbench02.par12_hispi_psp4l_i.clk_pn
x393_testbench02.par12_hispi_psp4l_i.clk_pn_dly
x393_testbench02.par12_hispi_psp4l_i.eof_sent
x393_testbench02.par12_hispi_psp4l_i.fifo_dav
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x393_testbench02.par12_hispi_psp4l_i.fifo_di[48:0]
x393_testbench02.par12_hispi_psp4l_i.fifo_out[48:0]
x393_testbench02.par12_hispi_psp4l_i.fifo_ra[11:0]
x393_testbench02.par12_hispi_psp4l_i.fifo_wa[11:0]
@28
x393_testbench02.par12_hispi_psp4l_i.fifo_we
x393_testbench02.par12_hispi_psp4l_i.frames_open[1:0]
x393_testbench02.par12_hispi_psp4l_i.hact
x393_testbench02.par12_hispi_psp4l_i.hact_d
x393_testbench02.par12_hispi_psp4l_i.hact_in
x393_testbench02.par12_hispi_psp4l_i.image_lines
x393_testbench02.par12_hispi_psp4l_i.int_clk
@22
x393_testbench02.par12_hispi_psp4l_i.lane_n[3:0]
x393_testbench02.par12_hispi_psp4l_i.lane_p[3:0]
@28
x393_testbench02.par12_hispi_psp4l_i.lane_pcntr[1:0]
x393_testbench02.par12_hispi_psp4l_i.line_available
x393_testbench02.par12_hispi_psp4l_i.lines_available[1:0]
x393_testbench02.par12_hispi_psp4l_i.next_frame_oclk
x393_testbench02.par12_hispi_psp4l_i.next_frame_pclk
x393_testbench02.par12_hispi_psp4l_i.next_line_oclk
x393_testbench02.par12_hispi_psp4l_i.next_line_pclk
x393_testbench02.par12_hispi_psp4l_i.next_sof
x393_testbench02.par12_hispi_psp4l_i.oclk
x393_testbench02.par12_hispi_psp4l_i.orst
x393_testbench02.par12_hispi_psp4l_i.orst_r
x393_testbench02.par12_hispi_psp4l_i.pclk
x393_testbench02.par12_hispi_psp4l_i.pre_fifo_we_data_w
x393_testbench02.par12_hispi_psp4l_i.pre_fifo_we_eof_w
x393_testbench02.par12_hispi_psp4l_i.pre_fifo_we_sof_sol_w
x393_testbench02.par12_hispi_psp4l_i.pre_fifo_we_w
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x393_testbench02.par12_hispi_psp4l_i.pre_lines
x393_testbench02.par12_hispi_psp4l_i.pxd[11:0]
x393_testbench02.par12_hispi_psp4l_i.pxd_d[47:0]
x393_testbench02.par12_hispi_psp4l_i.rdy[3:0]
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x393_testbench02.par12_hispi_psp4l_i.rst
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x393_testbench02.par12_hispi_psp4l_i.sdata[3:0]
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(0)x393_testbench02.par12_hispi_psp4l_i.sdata[3:0]
(1)x393_testbench02.par12_hispi_psp4l_i.sdata[3:0]
(2)x393_testbench02.par12_hispi_psp4l_i.sdata[3:0]
(3)x393_testbench02.par12_hispi_psp4l_i.sdata[3:0]
@1401200 @1401200
-group_end -PX1
@22
x393_testbench02.par12_hispi_psp4l_i.sdata_dly[3:0]
@28
x393_testbench02.par12_hispi_psp4l_i.sof_sol_sent
x393_testbench02.par12_hispi_psp4l_i.vact
x393_testbench02.par12_hispi_psp4l_i.vact_d
@1000200
-par12_hspi
@c00200 @c00200
-PX2 -PX2
@28 @28
...@@ -735,131 +546,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -735,131 +546,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-sensor_channel -sensor_channel
@800200 @800200
-sim_clk_tests -sim_clk_tests
@200
-
@800200
-simul_clk_mult
@28
x393_testbench02.PX1_MRST
@22
x393_testbench02.simul_clk_mult_i.prev_phase
x393_testbench02.simul_clk_mult_i.phase
x393_testbench02.simul_clk_mult_i.out_half_period
@28
x393_testbench02.simul_clk_mult_i.clk_in
x393_testbench02.simul_clk_mult_i.clk_out
x393_testbench02.simul_clk_mult_i.en
@1000200
-simul_clk_mult
@200
-
@28
x393_testbench02.PX1_MCLK_MULT_DIV
@c00022
x393_testbench02.PX1_DIV_CNTR[7:0]
@28
(0)x393_testbench02.PX1_DIV_CNTR[7:0]
(1)x393_testbench02.PX1_DIV_CNTR[7:0]
(2)x393_testbench02.PX1_DIV_CNTR[7:0]
(3)x393_testbench02.PX1_DIV_CNTR[7:0]
(4)x393_testbench02.PX1_DIV_CNTR[7:0]
(5)x393_testbench02.PX1_DIV_CNTR[7:0]
(6)x393_testbench02.PX1_DIV_CNTR[7:0]
(7)x393_testbench02.PX1_DIV_CNTR[7:0]
@1401200
-group_end
@800028
x393_testbench02.TEST_DLY[1:0]
@28
(1)x393_testbench02.TEST_DLY[1:0]
(0)x393_testbench02.TEST_DLY[1:0]
@1001200
-group_end
@800200
-sim_frac_clk_delay1
@28
x393_testbench02.sim_frac_clk_delay1_i.clk
x393_testbench02.sim_frac_clk_delay1_i.din
x393_testbench02.sim_frac_clk_delay1_i.dly_half
x393_testbench02.sim_frac_clk_delay1_i.dout
x393_testbench02.sim_frac_clk_delay1_i.en
@22
x393_testbench02.sim_frac_clk_delay1_i.frac_period
x393_testbench02.sim_frac_clk_delay1_i.num_period
x393_testbench02.sim_frac_clk_delay1_i.phase
x393_testbench02.sim_frac_clk_delay1_i.prev_phase
@800028
x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.sr[2:0]
@1001200
-group_end
@800028
x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.sr_fract[2:0]
@1001200
-group_end
@c00022
x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
(3)x393_testbench02.sim_frac_clk_delay1_i.taps[3:0]
@1401200
-group_end
@c00022
x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
@28
(0)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
(1)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
(2)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
(3)x393_testbench02.sim_frac_clk_delay1_i.taps_fract[3:0]
@1401200
-group_end
@1000200
-sim_frac_clk_delay1
@800200
-sim_frac_clk_delay2
@28
x393_testbench02.sim_frac_clk_delay2_i.clk
x393_testbench02.sim_frac_clk_delay2_i.din
x393_testbench02.sim_frac_clk_delay2_i.dly_half
x393_testbench02.sim_frac_clk_delay2_i.dout
x393_testbench02.sim_frac_clk_delay2_i.en
@22
x393_testbench02.sim_frac_clk_delay2_i.frac_period
x393_testbench02.sim_frac_clk_delay2_i.num_period
x393_testbench02.sim_frac_clk_delay2_i.phase
x393_testbench02.sim_frac_clk_delay2_i.prev_phase
@c00028
x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
@28
(0)x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
(1)x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
(2)x393_testbench02.sim_frac_clk_delay2_i.sr[2:0]
@1401200
-group_end
@28
x393_testbench02.sim_frac_clk_delay2_i.sr_fract[2:0]
@c00022
x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
@28
(0)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
(1)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
(2)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
(3)x393_testbench02.sim_frac_clk_delay2_i.taps[3:0]
@1401200
-group_end
@22
x393_testbench02.sim_frac_clk_delay2_i.taps_fract[3:0]
@1000200 @1000200
-sim_frac_clk_delay2
-sim_clk_tests -sim_clk_tests
@c00200 @c00200
-sensor_channel_2 -sensor_channel_2
......
x393_testbench02.tf
View file @ c7ad1d57
...@@ -195,6 +195,11 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -195,6 +195,11 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
wire PX4_HACT; // output wire PX4_HACT; // output
wire PX4_VACT; // output wire PX4_VACT; // output
wire PX1_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
// Sensor signals - as on FPGA pads // Sensor signals - as on FPGA pads
wire [ 7:0] sns1_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK} wire [ 7:0] sns1_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
wire [ 7:0] sns1_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF} wire [ 7:0] sns1_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
...@@ -232,10 +237,114 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -232,10 +237,114 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
wire sns4_ctl; // inout PX_ARO/TCK wire sns4_ctl; // inout PX_ARO/TCK
wire sns4_pg; // inout SENSPGM wire sns4_pg; // inout SENSPGM
//connect sensor to sensor port 1 // Keep signals defined even if HISPI is not, to preserve non-existing signals in .sav files of gtkwave
`ifdef HISPI
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock
`else
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock
`endif
`ifdef HISPI
localparam HISPI_CLK_DIV = 3; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
localparam HISPI_CLK_MULT = 10; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
localparam HISPI_EMBED_LINES = 2; // first lines will be marked as "embedded" (non-image data)
localparam HISPI_MSB_FIRST = 2; // 0 - serialize LSB first, 1 - MSB first
localparam HISPI_FIFO_LOGDEPTH = 12; // 49-bit wide FIFO address bits (>log (line_length + 2)
`endif
//`ifdef HISPI
wire [3:0] PX1_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX1_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX1_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX1_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX1_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX1_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX1_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire [3:0] PX2_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX2_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX2_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX2_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX2_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX2_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX2_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire [3:0] PX3_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX3_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX3_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX3_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX3_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX3_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX3_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire [3:0] PX4_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX4_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX4_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX4_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX4_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX4_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX4_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
//`endif
`ifdef HISPI
assign sns1_dp[3:0] = PX1_LANE_P;
assign sns1_dn[3:0] = PX1_LANE_N;
assign sns1_clkp = PX1_CLK_P;
assign sns1_clkn = PX1_CLK_N;
// non-HiSPi signals
assign sns1_dp[4] = PX1_FLASH;
assign sns1_dn[4] = PX1_SHUTTER;
assign PX1_GP[3:0] = {sns1_dn[7],sns1_dn[6], sns1_dn[5], sns1_dp[5]};
assign PX1_MCLK_PRE = sns1_dp[6]; // from FPGA to sensor
assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
assign PX1_ARST = sns1_dn[7]; // same as GP[3]
assign PX1_ARO = sns1_dn[6]; // same as GP[2]
assign sns2_dp[3:0] = PX2_LANE_P;
assign sns2_dn[3:0] = PX2_LANE_N;
assign sns2_clkp = PX2_CLK_P;
assign sns2_clkn = PX2_CLK_N;
// non-HiSPi signals
assign sns2_dp[4] = PX1_FLASH;
assign sns2_dn[4] = PX2_SHUTTER;
assign PX2_GP[3:0] = {sns2_dn[7],sns2_dn[6], sns2_dn[5], sns2_dp[5]};
assign PX2_MCLK_PRE = sns2_dp[6]; // from FPGA to sensor
assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor
assign PX2_ARST = sns2_dn[7]; // same as GP[3]
assign PX2_ARO = sns2_dn[6]; // same as GP[2]
assign sns3_dp[3:0] = PX3_LANE_P;
assign sns3_dn[3:0] = PX3_LANE_N;
assign sns3_clkp = PX3_CLK_P;
assign sns3_clkn = PX3_CLK_N;
// non-HiSPi signals
assign sns3_dp[4] = PX3_FLASH;
assign sns3_dn[4] = PX3_SHUTTER;
assign PX3_GP[3:0] = {sns3_dn[7],sns3_dn[6], sns3_dn[5], sns3_dp[5]};
assign PX3_MCLK_PRE = sns3_dp[6]; // from FPGA to sensor
assign PX3_MRST = sns3_dp[7]; // from FPGA to sensor
assign PX3_ARST = sns3_dn[7]; // same as GP[3]
assign PX3_ARO = sns3_dn[6]; // same as GP[2]
assign sns4_dp[3:0] = PX4_LANE_P;
assign sns4_dn[3:0] = PX4_LANE_N;
assign sns4_clkp = PX4_CLK_P;
assign sns4_clkn = PX4_CLK_N;
// non-HiSPi signals
assign sns4_dp[4] = PX4_FLASH;
assign sns4_dn[4] = PX4_SHUTTER;
assign PX4_GP[3:0] = {sns4_dn[7],sns4_dn[6], sns4_dn[5], sns4_dp[5]};
assign PX4_MCLK_PRE = sns4_dp[6]; // from FPGA to sensor
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_ARST = sns4_dn[7]; // same as GP[3]
assign PX4_ARO = sns4_dn[6]; // same as GP[2]
`else
//connect parallel12 sensor to sensor port 1
assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT}; assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
assign PX1_MCLK = sns1_dp[0]; // from FPGA to sensor assign PX1_MCLK_PRE = sns1_dp[0]; // from FPGA to sensor
assign sns1_dn[6:0] = {PX1_D[11], PX1_D[9], PX1_D[7], PX1_D[5], PX1_D[3], PX1_VACT, PX1_DCLK}; assign sns1_dn[6:0] = {PX1_D[11], PX1_D[9], PX1_D[7], PX1_D[5], PX1_D[3], PX1_VACT, PX1_DCLK};
assign PX1_ARST = sns1_dn[7]; assign PX1_ARST = sns1_dn[7];
assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI
...@@ -243,17 +352,17 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -243,17 +352,17 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
assign PX1_ARO = sns1_ctl; // from FPGA to sensor assign PX1_ARO = sns1_ctl; // from FPGA to sensor
assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor
assign PX2_MCLK = sns2_dp[0]; // from FPGA to sensor assign PX2_MCLK_PRE = sns2_dp[0]; // from FPGA to sensor
assign PX2_ARST = sns2_dn[7]; assign PX2_ARST = sns2_dn[7];
assign PX2_ARO = sns2_ctl; // from FPGA to sensor assign PX2_ARO = sns2_ctl; // from FPGA to sensor
assign PX3_MRST = sns3_dp[7]; // from FPGA to sensor assign PX3_MRST = sns3_dp[7]; // from FPGA to sensor
assign PX3_MCLK = sns3_dp[0]; // from FPGA to sensor assign PX3_MCLK_PRE = sns3_dp[0]; // from FPGA to sensor
assign PX3_ARST = sns3_dn[7]; assign PX3_ARST = sns3_dn[7];
assign PX3_ARO = sns3_ctl; // from FPGA to sensor assign PX3_ARO = sns3_ctl; // from FPGA to sensor
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_MCLK = sns4_dp[0]; // from FPGA to sensor assign PX4_MCLK_PRE = sns4_dp[0]; // from FPGA to sensor
assign PX4_ARST = sns4_dn[7]; assign PX4_ARST = sns4_dn[7];
assign PX4_ARO = sns4_ctl; // from FPGA to sensor assign PX4_ARO = sns4_ctl; // from FPGA to sensor
...@@ -275,24 +384,27 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -275,24 +384,27 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
assign sns4_clkp = PX4_D[1]; // CNVCLK/TDO assign sns4_clkp = PX4_D[1]; // CNVCLK/TDO
`else `else
//connect sensor to sensor port 2 (all data rotated left by 1 bit) //connect parallel12 sensor to sensor port 2 (all data rotated left by 1 bit)
assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT}; assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK}; assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
//connect sensor to sensor port 3 (all data rotated left by 2 bits //connect parallel12 sensor to sensor port 3 (all data rotated left by 2 bits
assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT}; assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK}; assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
//connect sensor to sensor port 4 (all data rotated left by 3 bits //connect parallel12 sensor to sensor port 4 (all data rotated left by 3 bits
assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT}; assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK}; assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
`endif `endif
`endif
wire [ 9:0] gpio_pins; // inout[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1) wire [ 9:0] gpio_pins; // inout[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
// Connect trigger outs to triggets in (#10 needed for Icarus) // Connect trigger outs to triggets in (#10 needed for Icarus)
...@@ -1976,63 +2088,20 @@ simul_axi_hp_wr #( ...@@ -1976,63 +2088,20 @@ simul_axi_hp_wr #(
.ffclk1 ({ffclk1n, ffclk1p}) // output[1:0] .ffclk1 ({ffclk1n, ffclk1p}) // output[1:0]
); );
wire PX1_MCLK_MULT; // Testing parallel12 -> HiSPi simulation converter
wire PX1_MCLK_MULT_DIV; `ifdef HISPI
reg [7:0] PX1_DIV_CNTR = 0;
wire [1:0] TEST_DLY;
simul_clk_mult #(
.MULTIPLIER(3)
) simul_clk_mult_i (
.clk_in (PX1_MCLK), // input
.en (1'b1), // input
.clk_out (PX1_MCLK_MULT) // output reg
);
sim_clk_div #(
.DIVISOR (5)
) sim_clk_div_i (
.clk_in (PX1_MCLK_MULT), // input
.en (1'b1), // input
.clk_out (PX1_MCLK_MULT_DIV) // output
);
always @ (posedge PX1_MCLK_MULT_DIV) PX1_DIV_CNTR <= PX1_DIV_CNTR + 1;
sim_frac_clk_delay #(
.FRAC_DELAY(2.1),
.SKIP_FIRST(5)
) sim_frac_clk_delay1_i (
.clk(PX1_MCLK_MULT_DIV), // input
.din(PX1_DIV_CNTR[3]), // input
.dout(TEST_DLY[0]) // output
);
sim_frac_clk_delay #(
.FRAC_DELAY(2.9),
.SKIP_FIRST(5)
) sim_frac_clk_delay2_i (
.clk(PX1_MCLK_MULT_DIV), // input
.din(PX1_DIV_CNTR[3]), // input
.dout(TEST_DLY[1]) // output
);
wire [3:0] PX1_LANE_P;
wire [3:0] PX1_LANE_N;
wire PX1_CLK_P;
wire PX1_CLK_N;
par12_hispi_psp4l #( par12_hispi_psp4l #(
.CLOCK_MPY(10), .CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV(3), .CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY(1.3), .LANE0_DLY (1.3),
.LANE1_DLY(2.7), .LANE1_DLY (2.7),
.LANE2_DLY(0.2), .LANE2_DLY (0.2),
.LANE3_DLY(3.3), .LANE3_DLY (3.3),
.CLK_DLY(2.3), .CLK_DLY (2.3),
.EMBED_LINES(2), .EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST(0), .MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH(12) .FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l_i ( ) par12_hispi_psp4l0_i (
.pclk ( PX1_MCLK), // input .pclk ( PX1_MCLK), // input
.rst (!PX1_MRST), // input .rst (!PX1_MRST), // input
.pxd (PX1_D), // input[11:0] .pxd (PX1_D), // input[11:0]
...@@ -2044,7 +2113,115 @@ simul_axi_hp_wr #( ...@@ -2044,7 +2113,115 @@ simul_axi_hp_wr #(
.clk_n (PX1_CLK_N) // output .clk_n (PX1_CLK_N) // output
); );
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l1_i (
.pclk ( PX2_MCLK), // input
.rst (!PX2_MRST), // input
.pxd (PX2_D), // input[11:0]
.vact (PX2_VACT), // input
.hact_in (PX2_HACT), // input
.lane_p (PX2_LANE_P), // output[3:0]
.lane_n (PX2_LANE_N), // output[3:0]
.clk_p (PX2_CLK_P), // output
.clk_n (PX2_CLK_N) // output
);
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l2_i (
.pclk ( PX3_MCLK), // input
.rst (!PX3_MRST), // input
.pxd (PX3_D), // input[11:0]
.vact (PX3_VACT), // input
.hact_in (PX3_HACT), // input
.lane_p (PX3_LANE_P), // output[3:0]
.lane_n (PX3_LANE_N), // output[3:0]
.clk_p (PX3_CLK_P), // output
.clk_n (PX3_CLK_N) // output
);
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (3.3),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l3_i (
.pclk ( PX4_MCLK), // input
.rst (!PX4_MRST), // input
.pxd (PX4_D), // input[11:0]
.vact (PX4_VACT), // input
.hact_in (PX4_HACT), // input
.lane_p (PX4_LANE_P), // output[3:0]
.lane_n (PX4_LANE_N), // output[3:0]
.clk_p (PX4_CLK_P), // output
.clk_n (PX4_CLK_N) // output
);
`endif
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix1_i (
.clk_in (PX1_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX1_MCLK) // output
);
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix2_i (
.clk_in (PX2_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX2_MCLK) // output
);
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix3_i (
.clk_in (PX3_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX3_MCLK) // output
);
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix4_i (
.clk_in (PX4_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX4_MCLK) // output
);
simul_sensor12bits #( simul_sensor12bits #(
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE), .lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
......
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