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Commit c676b5f2 authored by Andrey Filippov's avatar Andrey Filippov
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working on ddr3 phy

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.editor_defines 0 → 100644
View file @ c676b5f2
// This file may be used to define same pre-processor macros to be included into each parsed file
// It can be used to check different `ifdef branches
`define XIL_TIMING //Simprim
.project
View file @ c676b5f2
......@@ -43,25 +43,80 @@
<nature>com.elphel.vdt.veditor.HdlNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140429103628186.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140429103628186.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140515133627717.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140429103628186.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140515133627717.log</location>
</link>
<link>
<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140515133627717.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-place.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140515133627717.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140515133627717.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140429103628186.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140515133627717.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ c676b5f2
FPGA_project_2_ImplementationTopFile=phy/test_dqs07.v
FPGA_project_2_ImplementationTopFile=phy/test_phy_top_01.v
FPGA_project_4_part=xc7z030fbg484-2
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644
View file @ c676b5f2
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ c676b5f2
VivadoSynthesis_102_ConstraintsFiles=phy/test_dqs07_placement.xdc<-@\#\#@->
VivadoSynthesis_102_ConstraintsFiles=phy/test_phy_top_01.xdc<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs 0 → 100644
View file @ c676b5f2
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs 0 → 100644
View file @ c676b5f2
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
phy/byte_lane.v
View file @ c676b5f2
......@@ -31,7 +31,8 @@ module byte_lane #(
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
inout [7:0] dq, // DQ I/O pads
inout dm, // DM I/O pad (actually only output)
// inout dm, // DM I/O pad (actually only output)
output dm, // DM I/O pad (actually only output)
inout dqs, // DQS I/O pad
inout ndqs, // ~DQS I/O pad
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
......@@ -57,11 +58,12 @@ wire dqs_read;
wire iclk; // source-synchronous clock (BUFR from DQS)
reg [31:0] din_r=0;
reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
reg [7:0] dly_data_r=0;
reg set_r=0;
// Preventing register duplication
(* keep = "true" *) reg [7:0] dly_data_r=0;
(* keep = "true" *) reg set_r=0;
(* keep = "true" *) reg dci_disable_dqs_r, dci_disable_dq_r;
reg [7:0] ld_odly=8'b0, ld_idly=8'b0;
reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
reg dci_disable_dqs_r, dci_disable_dq_r;
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
wire [9:0] decode_sel={
(dly_addr[3:0]==9)?1'b1:1'b0,
......@@ -120,7 +122,7 @@ generate
);
end
endgenerate
/*
dq_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
......@@ -145,6 +147,31 @@ dq_single #(
.set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
.ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
);
*/
dm_single #(
.IODELAY_GRP(IODELAY_GRP),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.IOSTANDARD(IOSTANDARD_DQ),
.SLEW(SLEW_DQ),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dm_i(
.dm(dm), // DM output pad
// .iclk(iclk), // source-synchronous clock (BUFR from DQS)
.clk(clk), // free-running system clock, same frequency as iclk (shared for R/W)
.clk_div(clk_div), // free-running half clk frequency, front aligned to clk (shared for R/W)
// .inv_clk_div(inv_clk_div), // invert clk_div for R channel (clk_div is shared between R and W)
.rst(rst),
.dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
.dly_data(dly_data_r), // delay value (3 LSB - fine delay)
.din(din_dm_r[3:0]) , // parallel data to be sent out
.tin(tin_dq_r), // tristate for data out (sent out earlier than data!)
// .dout(), // parallel data received from DDR3 memory
.set_odelay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
// .set_idelay(1'b0), // clk_div synchronous load idelay value from dly_data
// .ld_idelay(1'b0) // clk_div synchronous set idealy value from loaded
);
dqs_single #(
.IODELAY_GRP(IODELAY_GRP),
......
phy/cmd_addr.v
View file @ c676b5f2
......@@ -45,7 +45,8 @@ module cmd_addr #(
input [1:0] in_cas, // input CAS, 2 bits (first, second)
input [1:0] in_cke, // input CKE, 2 bits (first, second)
input [1:0] in_odt, // input ODT, 2 bits (first, second)
input [1:0] in_tri, // tristate command/address outputs - same timing, but no odelay
// input [1:0] in_tri, // tristate command/address outputs - same timing, but no odelay
input in_tri, // tristate command/address outputs - same timing, but no odelay
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [4:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_iv synchronous)
......@@ -54,9 +55,11 @@ module cmd_addr #(
reg [2*ADDRESS_NUMBER-1:0] in_a_r=0;
reg [5:0] in_ba_r=0;
reg [1:0] in_we_r=2'h3, in_ras_r=2'h3, in_cas_r=2'h3, in_cke_r=2'h3, in_odt_r=2'h0;
reg [1:0] in_tri_r=2'h0; // or tri-state on reset?
reg [7:0] dly_data_r=0;
reg set_r=0;
//reg [1:0] in_tri_r=2'h0; // or tri-state on reset?
reg in_tri_r=1'b0; // or tri-state on reset?
// Preventing register duplication
(* keep = "true" *) reg [7:0] dly_data_r=0;
(* keep = "true" *) reg set_r=0;
reg [7:0] ld_dly_cmd=8'b0;
reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0;
wire [ADDRESS_NUMBER-1:0] decode_addr;
......@@ -74,7 +77,8 @@ always @ (posedge clk_div or posedge rst) begin
if (rst) begin
in_a_r <= 0; in_ba_r <= 6'b0;
in_we_r <= 2'h3; in_ras_r <= 2'h3; in_cas_r <= 2'h3; in_cke_r <= 2'h3; in_odt_r <= 2'h0;
in_tri_r <= 2'h0; // or tri-state on reset?
// in_tri_r <= 2'h0; // or tri-state on reset?
in_tri_r <= 1'b0; // or tri-state on reset?
dly_data_r<=8'b0;set_r<=1'b0;
ld_dly_cmd <= 8'b0; ld_dly_addr <= 0;
end else begin
......@@ -82,7 +86,8 @@ always @ (posedge clk_div or posedge rst) begin
in_ba_r <= in_ba;
in_we_r <= in_we; in_ras_r <= in_ras; in_cas_r <= in_cas; in_cke_r <= in_cke; in_odt_r <= in_odt;
in_tri_r <= in_tri;
dly_data_r<=dly_data;set_r<=set;
dly_data_r<=dly_data;
set_r<=set;
ld_dly_cmd <= {8 { dly_addr[4] & dly_addr[3] & ld_delay}} & decode_sel[7:0];
ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr;
end
......@@ -106,7 +111,8 @@ generate
.rst(rst),
.dly_data(dly_data_r[7:0]), // delay value (3 LSB - fine delay)
.din(in_a_r[2*i+1:2*i]), // parallel data to be sent out
.tin(in_tri_r[1:0]), // tristate for data out (sent out earlier than data!)
// .tin(in_tri_r[1:0]), // tristate for data out (sent out earlier than data!)
.tin(in_tri_r), // tristate for data out (sent out earlier than data!)
.set_delay(set_r), // clk_div synchronous load odelay value from dly_data
.ld_delay(ld_dly_addr[i]) // clk_div synchronous set odealy value from loaded
);
......@@ -127,7 +133,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_ba_r[1:0]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[0]));
// ba1
......@@ -144,7 +151,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_ba_r[3:2]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[1]));
// ba2
......@@ -161,7 +169,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_ba_r[5:4]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[2]));
......@@ -179,7 +188,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_we_r[1:0]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[3]));
......@@ -197,7 +207,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_ras_r[1:0]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[4]));
......@@ -215,7 +226,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_cas_r[1:0]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[5]));
......@@ -233,7 +245,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_cke_r[1:0]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[6]));
......@@ -251,7 +264,8 @@ endgenerate
.rst(rst),
.dly_data(dly_data_r[7:0]),
.din(in_odt_r[1:0]),
.tin(in_tri_r[1:0]),
// .tin(in_tri_r[1:0]),
.tin(in_tri_r),
.set_delay(set_r),
.ld_delay(ld_dly_cmd[7]));
......
phy/cmda_single.v
View file @ c676b5f2
......@@ -33,7 +33,8 @@ module cmda_single #(
input rst,
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [1:0] din, // parallel data to be sent out
input [1:0] tin, // tristate for data out (sent out earlier than data!)
// input [1:0] tin, // tristate for data out (sent out earlier than data!)
input tin, // tristate for data out (sent out earlier than data!)
input set_delay, // clk_div synchronous load odelay value from dly_data
input ld_delay // clk_div synchronous set odealy value from loaded
);
......@@ -48,7 +49,8 @@ oserdes_mem#(
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[1:0]), // parallel data in
.tin(tin[1:0]), // parallel tri-state in
// .tin(tin[1:0]), // parallel tri-state in
.tin(tin), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
......
phy/dm_single.v 0 → 100644
View file @ c676b5f2
/*******************************************************************************
* Module: dm_single
* Date:2014-04-26
* Author: Andrey Filippov
* Description: Single-bit DDR3 DQ I/O, same used for DM
*
* Copyright (c) 2014 Elphel, Inc.
* dm_single.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dm_single.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dm_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE"
)(
output dm, // I/O pad
input clk, // free-running system clock, same frequency as iclk (shared for R/W)
input clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W)
input rst,
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [3:0] din, // parallel data to be sent out
input [3:0] tin, // tristate for data out (sent out earlier than data!)
input set_odelay, // clk_div synchronous load odelay value from dly_data
input ld_odelay // clk_div synchronous set odealy value from loaded
);
wire d_ser;
wire dq_tri;
wire dq_data_dly;
oserdes_mem#(
.MODE_DDR("TRUE")
) oserdes_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(din[3:0]), // parallel data in
.tin(tin[3:0]), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(dq_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
odelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
.ld(ld_odelay),
.delay(dly_data[7:0]),
.data_in(d_ser),
.data_out(dq_data_dly)
);
IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
// SuppressWarnings VivadoSynthesis : VivadoSynthesis: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed
) iobufs_dqs_i (
// .O(dq_di),
.O(),
.IO(dm),
.DCITERMDISABLE(dci_disable),
.IBUFDISABLE(1'b0),
.I(dq_data_dly), //dqs_data),
.T(dq_tri));
endmodule
phy/phy_top.v
View file @ c676b5f2
......@@ -43,10 +43,10 @@ module phy_top #(
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_PHASE = 0.000,
parameter CLKOUT0_PHASE = 0.000,
parameter CLKOUT1_PHASE = 0.000,
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter ICLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 0.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
......@@ -83,7 +83,8 @@ module phy_top #(
input [1:0] in_cas, // input CAS, 2 bits (first, second)
input [1:0] in_cke, // input CKE, 2 bits (first, second)
input [1:0] in_odt, // input ODT, 2 bits (first, second)
input [1:0] in_tri, // tristate command/address outputs - same timing, but no odelay
// input [1:0] in_tri, // tristate command/address outputs - same timing, but no odelay
input in_tri, // tristate command/address outputs - same timing, but no odelay
input [63:0] din, // parallel data to be sent out (4 bits per DG I/))
input [7:0] din_dm, // parallel data to be sent out over DM
......@@ -143,7 +144,8 @@ module phy_top #(
.in_cas (in_cas[1:0]), // input CAS, 2 bits (first, second)
.in_cke (in_cke[1:0]), // input CKE, 2 bits (first, second)
.in_odt (in_odt[1:0]), // input ODT, 2 bits (first, second)
.in_tri (in_tri[1:0]), // tristate command/address outputs - same timing, but no odelay
// .in_tri (in_tri[1:0]), // tristate command/address outputs - same timing, but no odelay
.in_tri (in_tri), // tristate command/address outputs - same timing, but no odelay
.dly_data (dly_data[7:0]), // delay value (3 LSB - fine delay)
.dly_addr (dly_addr[4:0]), // select which delay to program
.ld_delay (ld_cmda), // load delay data to selected iodelayl (clk_iv synchronous)
......@@ -237,7 +239,10 @@ wire clk_pre, clk_div_pre, iclk_pre, mclk_pre, clk_fb;
BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(iclk), .I(iclk_pre) );
BUFIO clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
//BUFIO clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
//assign clk_ref=clk_ref_pre;
//BUFH clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
BUFG clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
BUFG mclk_i (.O(mclk),.I(mclk_pre) );
/* Instance template for module mmcm_phase_cntr */
mmcm_phase_cntr #(
......@@ -247,10 +252,10 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.CLKFBOUT_MULT_F (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT0_PHASE (ICLK_PHASE),
.CLKOUT1_PHASE (CLK_PHASE),
.CLKOUT2_PHASE (CLK_DIV_PHASE),
.CLKOUT3_PHASE (MCLK_PHASE),
// .CLKOUT4_PHASE (0.000),
// .CLKOUT5_PHASE (0.000),
// .CLKOUT6_PHASE (0.000),
......@@ -303,10 +308,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
);
// Generate reference clock for the I/O delays
/*
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
Instance template for module pll_base */
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD),
.BANDWIDTH("OPTIMIZED"),
......
phy/test_phy_top_01.v 0 → 100644
View file @ c676b5f2
/*******************************************************************************
* Module: test_phy_top_01
* Date:2014-05-14
* Author: Andrey Filippov
* Description: minimal instance of phy_top to test synthesis
*
* Copyright (c) 2014 Elphel, Inc.
* test_phy_top_01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_phy_top_01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module test_phy_top_01#(
parameter ADDRESS_NUMBER = 15,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKFBOUT_PHASE = 0.000,
parameter ICLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 0.000,
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000
)
(
output SDCLK, // DDR3 clock differential output, positive
output SDNCLK,// DDR3 clock differential output, negative
output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
output [2:0] SDBA, // output bank address ports
output SDWE, // output WE port
output SDRAS, // output RAS port
output SDCAS, // output CAS port
output SDCKE, // output Clock Enable port
output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads
inout SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad
inout SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad
inout NDQSU, // ~UDQS I/O pad
input clk_in, // master input clock, initially assuming 100MHz
input rst_in, // reset delays/serdes\
input fake_din,
input fake_en
);
// SuppressWarnings VEditor
(* keep = "true" *) wire clk; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire clk_div; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire mclk; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire [63:0] dout; // output[63:0]
// SuppressWarnings VEditor
(* keep = "true" *) wire locked; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire ps_rdy; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire [7:0]ps_out;// output[7:0]
reg [2*ADDRESS_NUMBER-1:0] in_a; // input address, 2 bits per signal (first, second) (29:0) for 4Gb device
reg [5:0] in_ba; // input bank address, 2 bits per signal (first, second)
reg [1:0] in_we; // input WE, 2 bits (first, second)
reg [1:0] in_ras; // input RAS, 2 bits (first, second)
reg [1:0] in_cas; // input CAS, 2 bits (first, second)
reg [1:0] in_cke; // input CKE, 2 bits (first, second)
reg [1:0] in_odt; // input ODT, 2 bits (first, second)
// reg [1:0] in_tri; // tristate command/address outputs - same timing, but no odelay
reg in_tri; // tristate command/address outputs - same timing, but no odelay
reg [63:0] din; // parallel data to be sent out (4 bits per DG I/))
reg [7:0] din_dm; // parallel data to be sent out over DM
reg [7:0] tin_dq; // tristate for data out (sent out earlier than data!) and dm
reg [7:0] din_dqs; // parallel data to be sent out over DQS
reg [7:0] tin_dqs; // tristate for DQS out (sent out earlier than data!)
reg inv_clk_div; // invert clk_div for R channels (clk_div is shared between R and W)
reg dci_disable_dqs; // disable DCI termination during writes and idle for dqs
reg dci_disable_dq; // disable DCI termination during writes and idle for dq and dm signals
reg [7:0] dly_data; // delay value (3 LSB - fine delay)
reg [6:0] dly_addr; // select which delay to program
reg ld_delay; // load delay data to selected iodelayl (clk_iv synchronous)
reg set; // clk_div synchronous set all delays from previously loaded values
// Create fake data sources for all input
always @ (posedge mclk) begin
if (fake_en)
{
in_a,
in_ba,
in_we,
in_ras,
in_cas,
in_cke,
in_odt,
in_tri,
din,
din_dm,
tin_dq,
din_dqs,
tin_dqs,
inv_clk_div,
dci_disable_dqs,
dci_disable_dq,
dly_data,
dly_addr,
ld_delay,
set
} <= {
fake_din,
in_a,
in_ba,
in_we,
in_ras,
in_cas,
in_cke,
in_odt,
in_tri,
din,
din_dm,
tin_dq,
din_dqs,
tin_dqs,
inv_clk_div,
dci_disable_dqs,
dci_disable_dq,
dly_data,
dly_addr,
ld_delay
};
end
phy_top #(
.IOSTANDARD_DQ ("SSTL15_T_DCI"),
.IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"),
.IOSTANDARD_CMDA ("SSTL15"),
.IOSTANDARD_CLK ("DIFF_SSTL15"),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
.SLEW_CMDA (SLEW_CMDA),
.SLEW_CLK (SLEW_CLK),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IODELAY_GRP (IODELAY_GRP),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.PHASE_WIDTH (8),
.BANDWIDTH ("OPTIMIZED"),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.ICLK_PHASE (ICLK_PHASE),
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
.REF_JITTER1 (REF_JITTER1),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD)
) phy_top_i (
.ddr3_clk (SDCLK), // output
.ddr3_nclk (SDNCLK), // output
.ddr3_a (SDA[14:0]), // output[14:0]
.ddr3_ba (SDBA[2:0]), // output[2:0]
.ddr3_we (SDWE), // output
.ddr3_ras (SDRAS), // output
.ddr3_cas (SDCAS), // output
.ddr3_cke (SDCKE), // output
.ddr3_odt (SDODT), // output
.dq (SDD[15:0]), // inout[15:0]
.dml (SDDML), // inout
.dqsl (DQSL), // inout
.ndqsl (NDQSL), // inout
.dmu (SDDMU), // inout
.dqsu (DQSU), // inout
.ndqsu (NDQSU), // inout
.clk_in (clk_in), // input
.clk (clk), // output
.clk_div (clk_div), // output
.mclk (mclk), // output
.rst_in (rst_in), // input
.in_a (in_a), // input[29:0]
.in_ba (in_ba), // input[5:0]
.in_we (in_we), // input[1:0]
.in_ras (in_ras), // input[1:0]
.in_cas (in_cas), // input[1:0]
.in_cke (in_cke), // input[1:0]
.in_odt (in_odt), // input[1:0]
.in_tri (in_tri), // input[1:0]
.din (din), // input[63:0]
.din_dm (din_dm), // input[7:0]
.tin_dq (tin_dq), // input[7:0]
.din_dqs (din_dqs), // input[7:0]
.tin_dqs (tin_dqs), // input[7:0]
.dout (dout[63:0]), // output[63:0]
.inv_clk_div (inv_clk_div), // input
.dci_disable_dqs (dci_disable_dqs), // input
.dci_disable_dq (dci_disable_dq), // input
.dly_data (dly_data), // input[7:0]
.dly_addr (dly_addr), // input[6:0]
.ld_delay (ld_delay), // input
.set (set), // input
.locked (locked), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]) // output[7:0]
);
endmodule
phy/test_phy_top_01.xdc 0 → 100644
View file @ c676b5f2
# output SDCLK, // DDR3 clock differential output, positive
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
# output SDNCLK,// DDR3 clock differential output, negative
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDNCLK}]
set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
# output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
set_property IOSTANDARD SSTL15 [get_ports {SDA[0]}]
set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[1]}]
set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[2]}]
set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[3]}]
set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[4]}]
set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[5]}]
set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[6]}]
set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[7]}]
set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[8]}]
set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[9]}]
set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[10]}]
set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[11]}]
set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[12]}]
set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[13]}]
set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[14]}]
set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
# output [2:0] SDBA, // output bank address ports
set_property IOSTANDARD SSTL15 [get_ports {SDBA[0]}]
set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
set_property IOSTANDARD SSTL15 [get_ports {SDBA[1]}]
set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
set_property IOSTANDARD SSTL15 [get_ports {SDBA[2]}]
set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
# output SDWE, // output WE port
set_property IOSTANDARD SSTL15 [get_ports {SDWE}]
set_property PACKAGE_PIN G4 [get_ports {SDWE}]
# output SDRAS, // output RAS port
set_property IOSTANDARD SSTL15 [get_ports {SDRAS}]
set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
# output SDCAS, // output CAS port
set_property IOSTANDARD SSTL15 [get_ports {SDCAS}]
set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
# output SDCKE, // output Clock Enable port
set_property IOSTANDARD SSTL15 [get_ports {SDCKE}]
set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
# output SDODT, // output ODT port
set_property IOSTANDARD SSTL15 [get_ports {SDODT}]
set_property PACKAGE_PIN M7 [get_ports {SDODT}]
#
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[0]}]
set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[1]}]
set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[2]}]
set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[3]}]
set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[4]}]
set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[5]}]
set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[6]}]
set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[7]}]
set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[8]}]
set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[9]}]
set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[10]}]
set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[11]}]
set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[12]}]
set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[13]}]
set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[14]}]
set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[15]}]
set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
# inout DQSL, // LDQS I/O pad
set_property PACKAGE_PIN N7 [get_ports {DQSL}]
set_property SLEW FAST [get_ports {DQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSL}]
# inout NDQSL, // ~LDQS I/O pad
set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
set_property SLEW FAST [get_ports {NDQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSL}]
# inout DQSU, // UDQS I/O pad
set_property PACKAGE_PIN H7 [get_ports {DQSU}]
#set_property SLEW FAST [get_ports {DQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSU}]
# inout NDQSU, // ~UDQS I/O pad
set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
#set_property SLEW FAST [get_ports {NDQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]
# inout SDDML, // LDM I/O pad (actually only output)
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
set_property PACKAGE_PIN L5 [get_ports {SDDML}]
# inout SDDMU, // UDM I/O pad (actually only output)
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
########### Other (fake - just for testing) pins ##################
# input clk_in, // master input clock, initially assuming 100MHz
set_property IOSTANDARD SSTL15 [get_ports {clk_in}]
set_property PACKAGE_PIN M5 [get_ports {clk_in}]
### borrowing fake inputs from a sensor port #########
# input rst_in, // reset delays/serdes
set_property IOSTANDARD SSTL15 [get_ports {rst_in}]
set_property PACKAGE_PIN U10 [get_ports {rst_in}]
# input fake_din,
set_property IOSTANDARD SSTL15 [get_ports {fake_din}]
set_property PACKAGE_PIN T9 [get_ports {fake_din}]
# input fake_en
set_property IOSTANDARD SSTL15 [get_ports {fake_en}]
set_property PACKAGE_PIN T10 [get_ports {fake_en}]
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
#set_property DCI_CASCADE{slave_banks} [get_iobanks master_bank]
# Designate Bank 14 as a master DCI Cascade bank and Banks 15 and 16 as its slaves
# set_property DCI_CASCADE {15 16} [get_iobanks 14]
set_property DCI_CASCADE 34 [get_iobanks 35]
set_property INTERNAL_VREF 0.750 [get_iobanks 35]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override
# this clock rule.
# < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF] >
# clk_ref_in_IBUF_inst (IBUF.O) is locked to IOB_X1Y123
# ref_clk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
# Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two.
# There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that
# result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is
# not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended
# clock has been placed on the N-Side of a differential pair CCIO-pin.
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ref_in_IBUF]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets *]
#trying to force BUFR to use fabric input
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets dqs_single_i/dqs_in_dly_i/dqs_received]
#puts [get_property CLOCK_DEDICATED_ROUTE [get_nets dqs_single_i/dqs_in_dly_i/dqs_received]]
\ No newline at end of file
phy/wrap/iserdes_mem.v
View file @ c676b5f2
......@@ -22,7 +22,8 @@
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
module iserdes_mem #
(
parameter DYN_CLKDIV_INV_EN="FALSE"
parameter DYN_CLKDIV_INV_EN="FALSE",
parameter IOBDELAY = "IFD" // "NONE", "IBUF", "IFD", "BOTH"
) (
input iclk, // source-synchronous clock
input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
......@@ -33,7 +34,6 @@ module iserdes_mem #
input ddly, // serial input from idelay
output [3:0] dout
);
parameter IOBDELAY = "IFD"; // "NONE", "IBUF", "IFD", "BOTH"
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
ISERDESE2 #(
......
phy/wrap/mmcm_phase_cntr.v
View file @ c676b5f2
......@@ -80,7 +80,7 @@ module mmcm_phase_cntr#(
input ps_we, // phase shift write eneble
input [PHASE_WIDTH-1:0] ps_din, // phase shift data input (2-s complement)
output ps_ready, // phase shift change finished
output reg [PHASE_WIDTH-1:0] ps_dout, // current phase shift value
output [PHASE_WIDTH-1:0] ps_dout, // current phase shift value
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
......@@ -97,22 +97,27 @@ module mmcm_phase_cntr#(
output clkfboutb,// inverted feedback output
output locked // PLL locked output
);
reg [PHASE_WIDTH-1:0] ps_dout_r;
wire psen; // phase shift enable input
reg psincdec; // phase shift direction input (1 - increment, 0 - decrement)
wire psdone; // phase shift done (12 clocks after psen
reg [PHASE_WIDTH-1:0] ps_target;
reg ps_busy=0;
reg ps_start0, ps_start;
// TODO: find out why it was optimized out!
(* keep = "true" *) reg ps_start0, ps_start; // debugging
assign ps_ready=!ps_busy && locked && ps_start0 && ps_start;
assign psen=ps_start && (diff != 0);
wire [PHASE_WIDTH:0] diff= ps_target-ps_dout;
// wire [PHASE_WIDTH:0] diff= ps_target-ps_dout_r;
// made a difference, so it doesn't seem Vivado extends bits of operands "+", "-"
wire [PHASE_WIDTH:0] diff= {ps_target[PHASE_WIDTH-1],ps_target}-{ps_dout_r[PHASE_WIDTH-1],ps_dout_r};
assign ps_dout = ps_dout_r;
always @ (posedge psclk or posedge rst) begin
if (rst) ps_start0 <= 0;
else ps_start0 <= ps_we && ps_ready;
if (rst) ps_dout <= 0;
else if (psen && psincdec) ps_dout <= ps_dout +1;
else if (psen && !psincdec) ps_dout <= ps_dout -1;
if (rst) ps_dout_r <= 0;
else if (psen && psincdec) ps_dout_r <= ps_dout_r +1;
else if (psen && !psincdec) ps_dout_r <= ps_dout_r -1;
if (rst) ps_target <= 0;
else if (ps_we && ps_ready) ps_target <= ps_din;
......
phy/wrap/oddr_ds.v
View file @ c676b5f2
......@@ -66,7 +66,3 @@ module oddr_ds # (
endmodule
endmodule
phy/wrap/oserdes_mem.v
View file @ c676b5f2
......@@ -27,7 +27,8 @@ module oserdes_mem #(
input clk_div, // oclk divided by 2, front aligned
input rst, // reset
input [((MODE_DDR=="TRUE")?3:1):0] din, // parallel data in
input [((MODE_DDR=="TRUE")?3:1):0] tin, // parallel tri-state in
// input [((MODE_DDR=="TRUE")?3:1):0] tin, // parallel tri-state in
input [((MODE_DDR=="TRUE")?3:0):0] tin, // parallel tri-state in
output dout_dly, // data out to be connected to odelay input
output dout_iob, // data out to be connected directly to the output buffer
output tout_dly, // tristate out to be connected to odelay input
......@@ -36,6 +37,7 @@ module oserdes_mem #(
//localparam integer MODE_DDR_BIN=(MODE_DDR=="TRUE")?1:0;
localparam DATA_RATE= (MODE_DDR=="TRUE")?"DDR":"SDR";
localparam integer DATA_WIDTH= (MODE_DDR=="TRUE")?4:2;
localparam integer DATA_WIDTH_TRI= (MODE_DDR=="TRUE")?4:1;
//localparam integer DDR3_DATA= (MODE_DDR=="TRUE")?1:0;
/*
Serialized data will go through odelay elements (with fine delay adjustment), tristate output will
......@@ -54,7 +56,7 @@ localparam integer DATA_WIDTH= (MODE_DDR=="TRUE")?4:2;
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (DATA_WIDTH),
.TRISTATE_WIDTH (DATA_WIDTH_TRI),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
) oserdes_i (
......@@ -79,7 +81,7 @@ localparam integer DATA_WIDTH= (MODE_DDR=="TRUE")?4:2;
.SHIFTIN1 (),
.SHIFTIN2 (),
.T1 (tin[0]),
.T2 (tin[1]),
.T2 ((MODE_DDR=="TRUE")?tin[1]:1'b0),
.T3 ((MODE_DDR=="TRUE")?tin[2]:1'b0),
.T4 ((MODE_DDR=="TRUE")?tin[3]:1'b0),
.TCE (1'b1),
......
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