added wrappers for block RAM in TDP mode (each port with R+W)

wrap/ramt_var_w_var_r.v

+/*******************************************************************************
+ * Module: ramt_var_w_var_r
+ * Date:2015-05-29  
+ * Author: andrey     
+ * Description:  Dual port memory wrapper, with variable width write and variable
+ * width read,  using "TDP" mode of RAMB36E1. Same R/W widths in each port.
+ * Does not use parity bits to increase total data width, width down to 1 are valid.
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * ramt_var_w_var_r.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  ramt_var_w_var_r.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+/*
+   Address/data widths
+   Connect unused data to 1b0, unused addresses - to 1'b1
+   
+   RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+   +-----------+---------+---------+---------+
+   |Data Width | Address |   Data  | Parity  |
+   +-----------+---------+---------+---------+
+   |     1     | A[13:0] | D[0]    |  ---    |
+   |     2     | A[13:1] | D[1:0]  |  ---    |
+   |     4     | A[13:2] | D[3:0[  |  ---    |
+   |     9     | A[13:3] | D[7:0]  | DP[0]   |
+   |    18     | A[13:4] | D[15:0] | DP[1:0] |
+   +-----------+---------+---------+---------+
+
+   RAMB18E1 in Simple Dual Port (SDP) Mode
+   one of the ports (r or w) - 32/36 bits, other - variable 
+   +------------+---------+---------+---------+
+   |Data Widths | Address |   Data  | Parity  |
+   +------------+---------+---------+---------+
+   |   32/  1   | A[13:0] | D[0]    |  ---    |
+   |   32/  2   | A[13:1] | D[1:0]  |  ---    |
+   |   32/  4   | A[13:2] | D[3:0[  |  ---    |
+   |   36/  9   | A[13:3] | D[7:0]  | DP[0]   |
+   |   36/ 18   | A[13:4] | D[15:0] | DP[1:0] |
+   |   36/ 36   | A[13:5] | D[31:0] | DP[3:0] |
+   +------------+---------+---------+---------+
+   
+   RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+   +-----------+---------+---------+---------+
+   |Data Width | Address |   Data  | Parity  |
+   +-----------+---------+---------+---------+
+   |     1     | A[14:0] | D[0]    |  ---    |
+   |     2     | A[14:1] | D[1:0]  |  ---    |
+   |     4     | A[14:2] | D[3:0[  |  ---    |
+   |     9     | A[14:3] | D[7:0]  | DP[0]   |
+   |    18     | A[14:4] | D[15:0] | DP[1:0] |
+   |    36     | A[14:5] | D[31:0] | DP[3:0] |
+   |1(Cascade) | A[15:0] | D[0]    |  ---    |
+   +-----------+---------+---------+---------+
+
+   RAMB36E1 in Simple Dual Port (SDP) Mode
+   one of the ports (r or w) - 64/72 bits, other - variable 
+   +------------+---------+---------+---------+
+   |Data Widths | Address |   Data  | Parity  |
+   +------------+---------+---------+---------+
+   |   64/  1   | A[14:0] | D[0]    |  ---    |
+   |   64/  2   | A[14:1] | D[1:0]  |  ---    |
+   |   64/  4   | A[14:2] | D[3:0[  |  ---    |
+   |   64/  9   | A[14:3] | D[7:0]  | DP[0]   |
+   |   64/ 18   | A[14:4] | D[15:0] | DP[1:0] |
+   |   64/ 36   | A[14:5] | D[31:0] | DP[3:0] |
+   |   64/ 72   | A[14:6] | D[63:0] | DP[7:0] |
+   +------------+---------+---------+---------+
+*/
+
+module  ramt_var_w_var_r
+#(
+  parameter integer REGISTERS_A = 0, // 1 - registered output
+  parameter integer REGISTERS_B = 0, // 1 - registered output
+  parameter integer LOG2WIDTH_A = 5,  // WIDTH= 9  << (LOG2WIDTH - 3)
+  parameter integer LOG2WIDTH_B = 5   // WIDTH= 9  << (LOG2WIDTH - 3)
+ )(
+      input                               clk_a,     // clock for port A
+      input            [14-LOG2WIDTH_A:0] addr_a,    // address port A
+      input                               en_a,      // enable port A (read and write)
+      input                               regen_a,   // output register enable port A
+      input                               we_a,      // write port enable port A
+      output     [(1 << LOG2WIDTH_A)-1:0] data_out_a,// data out port A
+      input      [(1 << LOG2WIDTH_A)-1:0] data_in_a, // data in port A
+      
+      input                               clk_b,     // clock for port BA
+      input            [14-LOG2WIDTH_B:0] addr_b,    // address port B
+      input                               en_b,      // read enable port B
+      input                               regen_b,   // output register enable port B
+      input                               we_b,      // write port enable port B
+      output     [(1 << LOG2WIDTH_B)-1:0] data_out_b,// data out port B
+      input      [(1 << LOG2WIDTH_B)-1:0] data_in_b  // data in port B
+);
+
+    localparam  PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
+    localparam  PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
+    localparam  WIDTH_A  = 1 << LOG2WIDTH_A;
+    localparam  WIDTH_B  = 1 << LOG2WIDTH_B;
+    
+    wire          [31:0] data_out32_a;
+    assign data_out_a=data_out32_a[WIDTH_A-1:0];
+
+    wire          [31:0] data_out32_b;
+    assign data_out_b=data_out32_b[WIDTH_B-1:0];
+
+
+    wire [WIDTH_A+31:0] data_in_ext_a =  {32'b0,data_in_a[WIDTH_A-1:0]};
+    wire         [31:0] data_in32_a =    data_in_ext_a[31:0];
+
+    wire [WIDTH_B+31:0] data_in_ext_b =  {32'b0,data_in_b[WIDTH_B-1:0]};
+    wire         [31:0] data_in32_b =    data_in_ext_b[31:0];
+
+    RAMB36E1
+    #(
+    .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
+    .RSTREG_PRIORITY_B         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
+    .DOA_REG                   (REGISTERS_A),    // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
+    .DOB_REG                   (REGISTERS_B),    // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
+    .RAM_EXTENSION_A           ("NONE"),         // Cascading, valid: "NONE","UPPER", LOWER"
+    .RAM_EXTENSION_B           ("NONE"),         // Cascading, valid: "NONE","UPPER", LOWER"
+    .READ_WIDTH_A              (PWIDTH_A),       // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .READ_WIDTH_B              (PWIDTH_B),       // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .WRITE_WIDTH_A             (PWIDTH_A),              // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .WRITE_WIDTH_B             (PWIDTH_B),       // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .RAM_MODE                  ("TDP"),          // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
+    .WRITE_MODE_A              ("WRITE_FIRST"),  // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
+    .WRITE_MODE_B              ("WRITE_FIRST"),  // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
+    .RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
+    .SIM_COLLISION_CHECK       ("ALL"),          // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
+    .INIT_FILE                 ("NONE"),         // "NONE" or filename with initialization data
+    .SIM_DEVICE                ("7SERIES"),      // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
+
+    .EN_ECC_READ               ("FALSE"),        // Valid:"FALSE","TRUE" (ECC decoder circuitry)
+    .EN_ECC_WRITE              ("FALSE")         // Valid:"FALSE","TRUE" (ECC decoder circuitry)
+//    .INIT_A(36'h0),               // Output latches initialization data
+//    .INIT_B(36'h0),               // Output latches initialization data
+//    .SRVAL_A(36'h0),              // Output latches initialization data (copied at when RSTRAM/RSTREG activated)    
+//    .SRVAL_B(36'h0)               // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
+/*
+    parameter IS_CLKARDCLK_INVERTED = 1'b0;
+    parameter IS_CLKBWRCLK_INVERTED = 1'b0;
+    parameter IS_ENARDEN_INVERTED = 1'b0;
+    parameter IS_ENBWREN_INVERTED = 1'b0;
+    parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
+    parameter IS_RSTRAMB_INVERTED = 1'b0;
+    parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
+    parameter IS_RSTREGB_INVERTED = 1'b0;
+*/    
+    
+    ) RAMB36E1_i
+    (
+        // Port A (Read port in SDP mode):
+        .DOADO           (data_out32_a),    // Port A data/LSB data[31:0], output
+        .DOPADOP         (),                // Port A parity/LSB parity[3:0], output
+        .DIADI           (data_in32_a),     // Port A data/LSB data[31:0], input
+        .DIPADIP         (4'b0),            // Port A parity/LSB parity[3:0], input
+        .ADDRARDADDR     ({1'b1,addr_a,{LOG2WIDTH_A{1'b1}}}),  // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
+        .CLKARDCLK       (clk_a),           // Port A (read port in SDP) clock, input
+        .ENARDEN         (en_a),            // Port A (read port in SDP) Enable, input
+        .REGCEAREGCE     (regen_a),         // Port A (read port in SDP) register enable, input
+        .RSTRAMARSTRAM   (1'b0),            // Port A (read port in SDP) set/reset, input
+        .RSTREGARSTREG   (1'b0),            // Port A (read port in SDP) register set/reset, input
+        .WEA             ({4{we_a}}),       // Port A (read port in SDP) Write Enable[3:0], input
+        // Port B
+        .DOBDO           (data_out32_b),    // Port B data/MSB data[31:0], output
+        .DOPBDOP         (),                // Port B parity/MSB parity[3:0], output
+        .DIBDI           (data_in32_b),     // Port B data/MSB data[31:0], input
+        .DIPBDIP         (4'b0),            // Port B parity/MSB parity[3:0], input
+        .ADDRBWRADDR     ({1'b1,addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
+        .CLKBWRCLK       (clk_b),           // Port B (write port in SDP) clock, input
+        .ENBWREN         (en_b),            // Port B (write port in SDP) Enable, input
+        .REGCEB          (regen_b),         // Port B (write port in SDP) register enable, input
+        .RSTRAMB         (1'b0),            // Port B (write port in SDP) set/reset, input
+        .RSTREGB         (1'b0),            // Port B (write port in SDP) register set/reset, input
+        .WEBWE           ({4'b0,{4{we_b}}}),// Port B (write port in SDP) Write Enable[7:0], input
+        // Error correction circuitry
+        .SBITERR         (),                // Single bit error status, output
+        .DBITERR         (),                // Double bit error status, output
+        .ECCPARITY       (),                // Genearted error correction parity [7:0], output
+        .RDADDRECC       (),                // ECC read address[8:0], output
+        .INJECTSBITERR   (1'b0),            // inject a single-bit error, input
+        .INJECTDBITERR   (1'b0),            // inject a double-bit error, input
+        // Cascade signals to create 64Kx1
+        .CASCADEOUTA     (),                // A-port cascade, output   
+        .CASCADEOUTB     (),                // B-port cascade, output
+        .CASCADEINA      (1'b0),            // A-port cascade, input
+        .CASCADEINB      (1'b0)             // B-port cascade, input
+    );
+
+
+endmodule
+

wrap/ramtp_var_w_var_r.v

+/*******************************************************************************
+ * Module: ramtp_var_w_var_r
+ * Date:2015-05-29  
+ * Author: andrey     
+ * Description:  Dual port memory wrapper, with variable width write and variable
+ * width read,  using "TDP" mode of RAMB36E1. Same R/W widths in each port.
+ * Uses parity bits to increase total data width. Widths down to 9 are valid.
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * ramtp_var_w_var_r.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  ramtp_var_w_var_r.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+/*
+   Address/data widths
+   Connect unused data to 1b0, unused addresses - to 1'b1
+   
+   RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+   +-----------+---------+---------+---------+
+   |Data Width | Address |   Data  | Parity  |
+   +-----------+---------+---------+---------+
+   |     1     | A[13:0] | D[0]    |  ---    |
+   |     2     | A[13:1] | D[1:0]  |  ---    |
+   |     4     | A[13:2] | D[3:0[  |  ---    |
+   |     9     | A[13:3] | D[7:0]  | DP[0]   |
+   |    18     | A[13:4] | D[15:0] | DP[1:0] |
+   +-----------+---------+---------+---------+
+
+   RAMB18E1 in Simple Dual Port (SDP) Mode
+   one of the ports (r or w) - 32/36 bits, other - variable 
+   +------------+---------+---------+---------+
+   |Data Widths | Address |   Data  | Parity  |
+   +------------+---------+---------+---------+
+   |   32/  1   | A[13:0] | D[0]    |  ---    |
+   |   32/  2   | A[13:1] | D[1:0]  |  ---    |
+   |   32/  4   | A[13:2] | D[3:0[  |  ---    |
+   |   36/  9   | A[13:3] | D[7:0]  | DP[0]   |
+   |   36/ 18   | A[13:4] | D[15:0] | DP[1:0] |
+   |   36/ 36   | A[13:5] | D[31:0] | DP[3:0] |
+   +------------+---------+---------+---------+
+   
+   RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+   +-----------+---------+---------+---------+
+   |Data Width | Address |   Data  | Parity  |
+   +-----------+---------+---------+---------+
+   |     1     | A[14:0] | D[0]    |  ---    |
+   |     2     | A[14:1] | D[1:0]  |  ---    |
+   |     4     | A[14:2] | D[3:0[  |  ---    |
+   |     9     | A[14:3] | D[7:0]  | DP[0]   |
+   |    18     | A[14:4] | D[15:0] | DP[1:0] |
+   |    36     | A[14:5] | D[31:0] | DP[3:0] |
+   |1(Cascade) | A[15:0] | D[0]    |  ---    |
+   +-----------+---------+---------+---------+
+
+   RAMB36E1 in Simple Dual Port (SDP) Mode
+   one of the ports (r or w) - 64/72 bits, other - variable 
+   +------------+---------+---------+---------+
+   |Data Widths | Address |   Data  | Parity  |
+   +------------+---------+---------+---------+
+   |   64/  1   | A[14:0] | D[0]    |  ---    |
+   |   64/  2   | A[14:1] | D[1:0]  |  ---    |
+   |   64/  4   | A[14:2] | D[3:0[  |  ---    |
+   |   64/  9   | A[14:3] | D[7:0]  | DP[0]   |
+   |   64/ 18   | A[14:4] | D[15:0] | DP[1:0] |
+   |   64/ 36   | A[14:5] | D[31:0] | DP[3:0] |
+   |   64/ 72   | A[14:6] | D[63:0] | DP[7:0] |
+   +------------+---------+---------+---------+
+*/
+
+module  ramtp_var_w_var_r
+#(
+  parameter integer REGISTERS_A = 0, // 1 - registered output
+  parameter integer REGISTERS_B = 0, // 1 - registered output
+  parameter integer LOG2WIDTH_A = 5,  // WIDTH= 9  << (LOG2WIDTH - 3)
+  parameter integer LOG2WIDTH_B = 5   // WIDTH= 9  << (LOG2WIDTH - 3)
+ )(
+      input                               clk_a,     // clock for port A
+      input            [14-LOG2WIDTH_A:0] addr_a,    // address port A
+      input                               en_a,      // enable port A (read and write)
+      input                               regen_a,   // output register enable port A
+      input                               we_a,      // write port enable port A
+      output [(9 << (LOG2WIDTH_A-3))-1:0] data_out_a,// data out port A
+      input  [(9 << (LOG2WIDTH_A-3))-1:0] data_in_a, // data in port A
+      
+      input                               clk_b,     // clock for port BA
+      input            [14-LOG2WIDTH_B:0] addr_b,    // address port B
+      input                               en_b,      // read enable port B
+      input                               regen_b,   // output register enable port B
+      input                               we_b,      // write port enable port B
+      output [(9 << (LOG2WIDTH_B-3))-1:0] data_out_b,// data out port B
+      input  [(9 << (LOG2WIDTH_B-3))-1:0] data_in_b  // data in port B
+);
+
+    localparam  PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
+    localparam  PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
+    localparam  WIDTH_A  = 1 << LOG2WIDTH_A;
+    localparam  WIDTH_AP = 1 << (LOG2WIDTH_A-3);
+    localparam  WIDTH_B  = 1 << LOG2WIDTH_B;
+    localparam  WIDTH_BP = 1 << (LOG2WIDTH_B-3);
+    
+    wire          [31:0] data_out32_a;
+    wire          [ 3:0] datap_out4_a;
+    assign data_out_a={datap_out4_a[WIDTH_AP-1:0], data_out32_a[WIDTH_A-1:0]};
+
+    wire          [31:0] data_out32_b;
+    wire          [ 3:0] datap_out4_b;
+    assign data_out_b={datap_out4_b[WIDTH_BP-1:0], data_out32_b[WIDTH_B-1:0]};
+
+
+    wire [WIDTH_A+31:0] data_in_ext_a =  {32'b0,data_in_a[WIDTH_A-1:0]};
+    wire         [31:0] data_in32_a =    data_in_ext_a[31:0];
+    wire [WIDTH_AP+3:0] datap_in_ext_a = {4'b0,data_in_a[WIDTH_A+:WIDTH_AP]};
+    wire          [3:0] datap_in4_a=     datap_in_ext_a[3:0];
+
+    wire [WIDTH_B+31:0] data_in_ext_b =  {32'b0,data_in_b[WIDTH_B-1:0]};
+    wire         [31:0] data_in32_b =    data_in_ext_b[31:0];
+    wire [WIDTH_BP+3:0] datap_in_ext_b = {4'b0,data_in_b[WIDTH_B+:WIDTH_BP]};
+    wire          [3:0] datap_in4_b=     datap_in_ext_b[3:0];
+
+    RAMB36E1
+    #(
+    .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
+    .RSTREG_PRIORITY_B         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
+    .DOA_REG                   (REGISTERS_A),    // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
+    .DOB_REG                   (REGISTERS_B),    // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
+    .RAM_EXTENSION_A           ("NONE"),         // Cascading, valid: "NONE","UPPER", LOWER"
+    .RAM_EXTENSION_B           ("NONE"),         // Cascading, valid: "NONE","UPPER", LOWER"
+    .READ_WIDTH_A              (PWIDTH_A),       // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .READ_WIDTH_B              (PWIDTH_B),       // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .WRITE_WIDTH_A             (PWIDTH_A),              // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .WRITE_WIDTH_B             (PWIDTH_B),       // Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
+    .RAM_MODE                  ("TDP"),          // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
+    .WRITE_MODE_A              ("WRITE_FIRST"),  // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
+    .WRITE_MODE_B              ("WRITE_FIRST"),  // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
+    .RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
+    .SIM_COLLISION_CHECK       ("ALL"),          // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
+    .INIT_FILE                 ("NONE"),         // "NONE" or filename with initialization data
+    .SIM_DEVICE                ("7SERIES"),      // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
+
+    .EN_ECC_READ               ("FALSE"),        // Valid:"FALSE","TRUE" (ECC decoder circuitry)
+    .EN_ECC_WRITE              ("FALSE")         // Valid:"FALSE","TRUE" (ECC decoder circuitry)
+//    .INIT_A(36'h0),               // Output latches initialization data
+//    .INIT_B(36'h0),               // Output latches initialization data
+//    .SRVAL_A(36'h0),              // Output latches initialization data (copied at when RSTRAM/RSTREG activated)    
+//    .SRVAL_B(36'h0)               // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
+/*
+    parameter IS_CLKARDCLK_INVERTED = 1'b0;
+    parameter IS_CLKBWRCLK_INVERTED = 1'b0;
+    parameter IS_ENARDEN_INVERTED = 1'b0;
+    parameter IS_ENBWREN_INVERTED = 1'b0;
+    parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
+    parameter IS_RSTRAMB_INVERTED = 1'b0;
+    parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
+    parameter IS_RSTREGB_INVERTED = 1'b0;
+*/    
+    
+    ) RAMB36E1_i
+    (
+        // Port A (Read port in SDP mode):
+        .DOADO           (data_out32_a),    // Port A data/LSB data[31:0], output
+        .DOPADOP         (datap_out4_a),    // Port A parity/LSB parity[3:0], output
+        .DIADI           (data_in32_a),     // Port A data/LSB data[31:0], input
+        .DIPADIP         (datap_in4_a),     // Port A parity/LSB parity[3:0], input
+        .ADDRARDADDR     ({1'b1,addr_a,{LOG2WIDTH_A{1'b1}}}),  // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
+        .CLKARDCLK       (clk_a),           // Port A (read port in SDP) clock, input
+        .ENARDEN         (en_a),            // Port A (read port in SDP) Enable, input
+        .REGCEAREGCE     (regen_a),         // Port A (read port in SDP) register enable, input
+        .RSTRAMARSTRAM   (1'b0),            // Port A (read port in SDP) set/reset, input
+        .RSTREGARSTREG   (1'b0),            // Port A (read port in SDP) register set/reset, input
+        .WEA             ({4{we_a}}),       // Port A (read port in SDP) Write Enable[3:0], input
+        // Port B
+        .DOBDO           (data_out32_b),    // Port B data/MSB data[31:0], output
+        .DOPBDOP         (datap_out4_b),    // Port B parity/MSB parity[3:0], output
+        .DIBDI           (data_in32_b),     // Port B data/MSB data[31:0], input
+        .DIPBDIP         (datap_in4_b),     // Port B parity/MSB parity[3:0], input
+        .ADDRBWRADDR     ({1'b1,addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
+        .CLKBWRCLK       (clk_b),           // Port B (write port in SDP) clock, input
+        .ENBWREN         (en_b),            // Port B (write port in SDP) Enable, input
+        .REGCEB          (regen_b),         // Port B (write port in SDP) register enable, input
+        .RSTRAMB         (1'b0),            // Port B (write port in SDP) set/reset, input
+        .RSTREGB         (1'b0),            // Port B (write port in SDP) register set/reset, input
+        .WEBWE           ({4'b0,{4{we_b}}}), // Port B (write port in SDP) Write Enable[7:0], input
+        // Error correction circuitry
+        .SBITERR         (),                // Single bit error status, output
+        .DBITERR         (),                // Double bit error status, output
+        .ECCPARITY       (),                // Genearted error correction parity [7:0], output
+        .RDADDRECC       (),                // ECC read address[8:0], output
+        .INJECTSBITERR   (1'b0),            // inject a single-bit error, input
+        .INJECTDBITERR   (1'b0),            // inject a double-bit error, input
+        // Cascade signals to create 64Kx1
+        .CASCADEOUTA     (),                // A-port cascade, output   
+        .CASCADEOUTB     (),                // B-port cascade, output
+        .CASCADEINA      (1'b0),            // A-port cascade, input
+        .CASCADEINB      (1'b0)             // B-port cascade, input
+    );
+
+
+endmodule
+