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Commit c4d0f3bc authored by Andrey Filippov's avatar Andrey Filippov
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Debugging mclt bayer

parent 1b250b27
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dsp/dsp_ma_preadd.v
View file @ c4d0f3bc
...@@ -42,7 +42,8 @@ module dsp_ma_preadd #( ...@@ -42,7 +42,8 @@ module dsp_ma_preadd #(
parameter B_WIDTH = 18, parameter B_WIDTH = 18,
parameter A_WIDTH = 25, parameter A_WIDTH = 25,
parameter P_WIDTH = 48, parameter P_WIDTH = 48,
parameter BREG = 1) // means number in series, so "2" always reads the second parameter AREG = 1,
parameter BREG = 1) // means number in series, so "2" always reads the second
( (
input clk, input clk,
input rst, input rst,
...@@ -86,7 +87,7 @@ module dsp_ma_preadd #( ...@@ -86,7 +87,7 @@ module dsp_ma_preadd #(
.ACASCREG (1), .ACASCREG (1),
.ADREG (1), .ADREG (1),
.ALUMODEREG (1), .ALUMODEREG (1),
.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second .AREG (AREG), // 2), // (1) - means number in series, so "2" always reads the second
.AUTORESET_PATDET ("NO_RESET"), .AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"), // "DIRECT", "CASCADE" .A_INPUT ("DIRECT"), // "DIRECT", "CASCADE"
.BCASCREG (1), .BCASCREG (1),
...@@ -206,20 +207,36 @@ module dsp_ma_preadd #( ...@@ -206,20 +207,36 @@ module dsp_ma_preadd #(
generate generate
case (AREG)
1 : begin
always @(posedge clk) begin
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain;
end
end
2 : begin
always @(posedge clk) begin
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= a1_reg;
end
end
endcase
case (BREG) case (BREG)
1 : begin 1 : begin
always @(posedge clk) begin always @(posedge clk) begin
if (rst) b2_reg <= 18'b0; if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin; else if (ceb2) b2_reg <= bin;
end end
end end
2 : begin 2 : begin
always @(posedge clk) begin always @(posedge clk) begin
if (rst) b2_reg <= 18'b0; if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= b1_reg; else if (ceb2) b2_reg <= b1_reg;
end end
end end
endcase endcase
endgenerate endgenerate
...@@ -228,14 +245,14 @@ module dsp_ma_preadd #( ...@@ -228,14 +245,14 @@ module dsp_ma_preadd #(
else if (ceb1) b1_reg <= bin; else if (ceb1) b1_reg <= bin;
if (rst) b2_reg <= 0; // if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin; // else if (ceb2) b2_reg <= bin;
if (rst) a1_reg <= 0; if (rst) a1_reg <= 0;
else if (cea1) a1_reg <= ain; else if (cea1) a1_reg <= ain;
if (rst) a2_reg <= 0; // if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain; // else if (cea2) a2_reg <= ain;
if (rst) d_reg <= 0; if (rst) d_reg <= 0;
else if (ced) d_reg <= din; else if (ced) d_reg <= din;
......
dsp/mclt16x16_bayer.v
View file @ c4d0f3bc
...@@ -79,8 +79,15 @@ module mclt16x16_bayer#( ...@@ -79,8 +79,15 @@ module mclt16x16_bayer#(
output signed [OUT_WIDTH - 1 : 0] dout1 //!<frequency domain data output (odd s amples) output signed [OUT_WIDTH - 1 : 0] dout1 //!<frequency domain data output (odd s amples)
); );
// When defined, use 2 DSP multipleierts
`define DSP_ACCUM_FOLD 1
localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=? localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_IN_DELAY = 62; // 69; // wa -ra min = 1 localparam DTT_IN_DELAY = 62; // 69; // wa -ra min = 1
wire signed [OUT_WIDTH - 1 : 0] dbg_dout0 = {dout0[OUT_WIDTH - 1],dout0[OUT_WIDTH - 1 : 1]}; // SuppressThisWarning VEditor : debug only signal
wire signed [OUT_WIDTH - 1 : 0] dbg_dout1 = {dout1[OUT_WIDTH - 1],dout1[OUT_WIDTH - 1 : 1]}; // SuppressThisWarning VEditor : debug only signal
reg [ 1:0] start_r; reg [ 1:0] start_r;
// maybe use small FIFO memory? // maybe use small FIFO memory?
...@@ -98,38 +105,26 @@ module mclt16x16_bayer#( ...@@ -98,38 +105,26 @@ module mclt16x16_bayer#(
reg inv_checker_r4; reg inv_checker_r4;
wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
wire [14:0] phases; //!< other signals wire [6:0] phases; //!< other signals
wire signed [WND_WIDTH-1:0] window_w; wire signed [WND_WIDTH-1:0] window_w;
reg signed [WND_WIDTH-1:0] window_r;
reg signed [PIXEL_WIDTH-1:0] pix_d_r; // registered pixel data (to be absorbed by MPY) wire signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
reg signed [PIXEL_WIDTH + WND_WIDTH - 1:0] pix_wnd_r; // MSB not used: positive[PIXEL_WIDTH]*positive[WND_WIDTH]->positive[PIXEL_WIDTH+WND_WIDTH-1]
reg signed [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow
// rounding
wire signed [DTT_IN_WIDTH-3:0] pix_wnd_r2_w = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]
`ifdef ROUND
+ pix_wnd_r[PIXEL_WIDTH + WND_WIDTH -DTT_IN_WIDTH]
`endif
;
reg signed [DTT_IN_WIDTH-1:0] data_cc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r;
reg signed [DTT_IN_WIDTH-1:0] data_sc_r2; // data_sc_r delayed by 1 cycle
reg signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
reg mode_mux;
reg [6:0] dtt_in_cntr; // reg [6:0] dtt_in_cntr; //
reg dtt_in_page; reg dtt_in_page;
wire [8:0] dtt_in_wa = {1'b0,dtt_in_page, dtt_in_cntr[0], dtt_in_cntr[6:1]}; wire [8:0] dtt_in_wa = {1'b0,dtt_in_page, dtt_in_cntr[0], dtt_in_cntr[6:1]};
wire dtt_we = phases[14]; // wire dtt_we = phases[14];
wire dtt_we;
wire [ 1:0] pix_sgn_d; // wire [ 1:0] pix_sgn_d;
reg [ 1:0] pix_sgn_r; // reg [ 1:0] pix_sgn_r;
wire var_first; // adding subtracting first variant of 4 folds // wire var_first; // adding subtracting first variant of 4 folds
reg var_last; // next cycle the data_xx_r will have data (in_busy[14], ...) wire var_pre2_first; //
// reg var_last; // next cycle the data_xx_r will have data (in_busy[14], ...)
// reading/converting DTT // reading/converting DTT
reg start_dtt; // = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256 reg start_dtt; // = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256
...@@ -143,6 +138,7 @@ module mclt16x16_bayer#( ...@@ -143,6 +138,7 @@ module mclt16x16_bayer#(
wire [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr}; wire [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr};
wire signed [35:0] dtt_r_data_w; // high bits are not used wire signed [35:0] dtt_r_data_w; // high bits are not used
wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0]; wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0];
wire signed [DTT_IN_WIDTH-1:0] dbg_dtt_r_data = {dtt_r_data_w[DTT_IN_WIDTH-1],dtt_r_data_w[DTT_IN_WIDTH-1:1]}; // SuppressThisWarning VEditor : debug only signal
reg pre_last_out_r; reg pre_last_out_r;
wire pre_last_in_w; wire pre_last_in_w;
...@@ -177,37 +173,9 @@ module mclt16x16_bayer#( ...@@ -177,37 +173,9 @@ module mclt16x16_bayer#(
y_shft_r4 <= y_shft_r3; y_shft_r4 <= y_shft_r3;
inv_checker_r4 <= inv_checker_r3; inv_checker_r4 <= inv_checker_r3;
end end
if (phases[8]) begin // if (!phases[14]) dtt_in_cntr <= 0;
pix_d_r <= pix_d; if (!dtt_we) dtt_in_cntr <= 0;
window_r <= window_w;
end
if (phases[9]) pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra
if (phases[10]) begin
pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};
pix_sgn_r <= pix_sgn_d;
end
var_last <= var_first & phases[11];
if (phases[11]) begin
data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (pix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2) ;
data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (pix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2) ;
data_sc_r2 <= data_sc_r;
end
if (phases[12]) data_sc_r2 <= data_sc_r;
if (var_last) mode_mux <= 0;
else if (phases[13]) mode_mux <= mode_mux + 1;
if (phases[13]) case (mode_mux)
1'b0: data_dtt_in <= data_cc_r;
1'b1: data_dtt_in <= data_sc_r2;
endcase
if (!phases[14]) dtt_in_cntr <= 0;
else dtt_in_cntr <= dtt_in_cntr + 1; else dtt_in_cntr <= dtt_in_cntr + 1;
start_dtt <= dtt_in_cntr == DTT_IN_DELAY; start_dtt <= dtt_in_cntr == DTT_IN_DELAY;
...@@ -235,6 +203,7 @@ module mclt16x16_bayer#( ...@@ -235,6 +203,7 @@ module mclt16x16_bayer#(
mclt_bayer_fold #( mclt_bayer_fold #(
.SHIFT_WIDTH (SHIFT_WIDTH), .SHIFT_WIDTH (SHIFT_WIDTH),
.PIX_ADDR_WIDTH (PIX_ADDR_WIDTH), .PIX_ADDR_WIDTH (PIX_ADDR_WIDTH),
.ADDR_DLY (4'h1), // 2 for mpy, 1 - for dsp
.COORD_WIDTH (COORD_WIDTH), .COORD_WIDTH (COORD_WIDTH),
// .PIXEL_WIDTH (PIXEL_WIDTH), // .PIXEL_WIDTH (PIXEL_WIDTH),
.WND_WIDTH (WND_WIDTH) .WND_WIDTH (WND_WIDTH)
...@@ -248,35 +217,26 @@ module mclt16x16_bayer#( ...@@ -248,35 +217,26 @@ module mclt16x16_bayer#(
// .DSP_P_WIDTH (DSP_P_WIDTH), // .DSP_P_WIDTH (DSP_P_WIDTH),
// .DEAD_CYCLES (DEAD_CYCLES) // .DEAD_CYCLES (DEAD_CYCLES)
) mclt_bayer_fold_i ( ) mclt_bayer_fold_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.start (start), // input .start (start), // input
.tile_size (tile_size), // input[1:0] .tile_size (tile_size), // input[1:0]
.inv_checker (inv_checker), // input .inv_checker (inv_checker), // input
.top_left (top_left), // input[7:0] .top_left (top_left), // input[7:0]
.valid_rows (valid_rows), // input[1:0] .valid_rows (valid_rows), // input[1:0]
.x_shft (x_shft), // input[6:0] .x_shft (x_shft), // input[6:0]
.y_shft (y_shft), // input[6:0] .y_shft (y_shft), // input[6:0]
.pix_addr (pix_addr), // output[8:0] .pix_addr (pix_addr), // output[8:0]
.pix_re (pix_re), // output .pix_re (pix_re), // output
.pix_page (pix_page), // output .pix_page (pix_page), // output
.window (window_w), // output[17:0] signed .window (window_w), // output[17:0] signed
.signs (signs), // output[1:0] .signs (signs), // output[1:0]
.phases (phases), // output[7:0] .phases (phases), // output[7:0]
.var_first (var_first), // output reg .var_pre2_first(var_pre2_first), // output
.pre_last_in (pre_last_in_w)// output reg // .var_first (), // var_first), // output reg
.pre_last_in (pre_last_in_w)// output reg
); );
dly_var #(
.WIDTH(2),
.DLY_WIDTH(4)
) dly_pix_sgn_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h1), // input[3:0]
.din (signs), // input[0:0]
.dout (pix_sgn_d) // output[0:0]
);
ram18p_var_w_var_r #( ram18p_var_w_var_r #(
...@@ -299,6 +259,9 @@ module mclt16x16_bayer#( ...@@ -299,6 +259,9 @@ module mclt16x16_bayer#(
wire signed [OUT_WIDTH-1:0] dtt_out_wd; wire signed [OUT_WIDTH-1:0] dtt_out_wd;
wire signed [OUT_WIDTH-1:0] dbg_dtt_out_wd={dtt_out_wd[OUT_WIDTH-1],dtt_out_wd[OUT_WIDTH-1:1]};// SuppressThisWarning VEditor : debug only signal
wire [3:0] dtt_out_wa16; wire [3:0] dtt_out_wa16;
wire dtt_out_we; wire dtt_out_we;
wire dtt_sub16; wire dtt_sub16;
...@@ -308,7 +271,7 @@ module mclt16x16_bayer#( ...@@ -308,7 +271,7 @@ module mclt16x16_bayer#(
reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_first_fill; reg dtt_start_first_fill;
reg dtt_start_out; // start read out to sin/cos rotator reg [1:0] dtt_start_out; // start read out to sin/cos rotator
// frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first) // frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first)
...@@ -330,6 +293,8 @@ module mclt16x16_bayer#( ...@@ -330,6 +293,8 @@ module mclt16x16_bayer#(
// data to be input to phase rotator // data to be input to phase rotator
wire signed [OUT_WIDTH-1:0] dtt_rd_data0 = dtt_rd_data0_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3] wire signed [OUT_WIDTH-1:0] dtt_rd_data0 = dtt_rd_data0_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dtt_rd_data1 = dtt_rd_data1_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3] wire signed [OUT_WIDTH-1:0] dtt_rd_data1 = dtt_rd_data1_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dbg_dtt_rd_data0 = {dtt_rd_data0[OUT_WIDTH-1],dtt_rd_data0[OUT_WIDTH-1:1]}; // SuppressThisWarning VEditor : debug only signal
wire signed [OUT_WIDTH-1:0] dbg_dtt_rd_data1 = {dtt_rd_data1[OUT_WIDTH-1],dtt_rd_data1[OUT_WIDTH-1:1]}; // SuppressThisWarning VEditor : debug only signal
wire dtt_first_quad_out = ~dtt_out_ram_cntr[2]; wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
...@@ -346,19 +311,20 @@ module mclt16x16_bayer#( ...@@ -346,19 +311,20 @@ module mclt16x16_bayer#(
else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY; else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1; else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
dtt_start_out <= dtt_dly_cntr == 1; dtt_start_out <= {dtt_start_out[0],(dtt_dly_cntr == 1) ? 1'b1 : 1'b0};
if (rst) dtt_rd_regen_dv[0] <= 0; if (rst) dtt_rd_regen_dv[0] <= 0;
else if (dtt_start_out) dtt_rd_regen_dv[0] <= 1; else if (dtt_start_out[0]) dtt_rd_regen_dv[0] <= 1;
else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0; else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[3:1] <= 0; if (rst) dtt_rd_regen_dv[3:1] <= 0;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0]; else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
if (dtt_start_out) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1; else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
/*
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7], dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5], dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0], dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0],
...@@ -367,10 +333,42 @@ module mclt16x16_bayer#( ...@@ -367,10 +333,42 @@ module mclt16x16_bayer#(
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5], dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0], dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0],
~dtt_rd_cntr_pre[5]}; ~dtt_rd_cntr_pre[5]};
*/
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
dtt_rd_cntr_pre[0]};
dtt_rd_ra1 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
~dtt_rd_cntr_pre[0]};
end end
mclt_baeyer_fold_accum #(
.PIXEL_WIDTH(PIXEL_WIDTH),
.WND_WIDTH(WND_WIDTH),
.DTT_IN_WIDTH(DTT_IN_WIDTH),
.DSP_B_WIDTH(DSP_B_WIDTH),
.DSP_A_WIDTH(DSP_A_WIDTH),
.DSP_P_WIDTH(DSP_P_WIDTH)
) mclt_baeyer_fold_accum_i (
.clk (clk), // input
.rst (rst), // input
.pre_phase (phases[6]), // input
.pix_d (pix_d), // input[15:0] signed
.pix_sgn (signs), // input[1:0]
.window (window_w), // input[17:0] signed
.var_pre2_first (var_pre2_first), // input
.dtt_in (data_dtt_in), // output[24:0] signed
.dtt_in_dv (dtt_we) // output reg
);
dtt_iv_8x8_ad #( dtt_iv_8x8_ad #(
.INPUT_WIDTH (DTT_IN_WIDTH), .INPUT_WIDTH (DTT_IN_WIDTH),
.OUT_WIDTH (OUT_WIDTH), .OUT_WIDTH (OUT_WIDTH),
...@@ -453,7 +451,7 @@ module mclt16x16_bayer#( ...@@ -453,7 +451,7 @@ module mclt16x16_bayer#(
) phase_rotator0_i ( ) phase_rotator0_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.start (dtt_start_out), // input .start (dtt_start_out[1]), // input
// are these shift OK? Will need to be valis only @ dtt_start_out // are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r4), // input[6:0] signed .shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r4), // input[6:0] signed .shift_v (y_shft_r4), // input[6:0] signed
...@@ -475,15 +473,15 @@ module mclt16x16_bayer#( ...@@ -475,15 +473,15 @@ module mclt16x16_bayer#(
) phase_rotator1_i ( ) phase_rotator1_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.start (dtt_start_out), // input .start (dtt_start_out[1]), // input
// are these shift OK? Will need to be valis only @ dtt_start_out // are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r4), // input[6:0] signed .shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r4), // input[6:0] signed .shift_v (y_shft_r4), // input[6:0] signed
.inv_checker (inv_checker_r4),// input only used for Bayer mosaic data .inv_checker (inv_checker_r4),// input only used for Bayer mosaic data
.fd_din (dtt_rd_data1), // input[24:0] signed. Expected latency = 3 from start .fd_din (dtt_rd_data1), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout1), // output[24:0] reg signed .fd_out (dout1), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg .pre_first_out (), // output reg
.fd_dv (dv) // output reg .fd_dv () // output reg
); );
......
dsp/mclt_bayer_fold.v
View file @ c4d0f3bc
...@@ -42,7 +42,7 @@ module mclt_bayer_fold#( ...@@ -42,7 +42,7 @@ module mclt_bayer_fold#(
parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional) parameter SHIFT_WIDTH = 7, // bits in shift (7 bits - fractional)
parameter PIX_ADDR_WIDTH = 9, // number of pixel address width parameter PIX_ADDR_WIDTH = 9, // number of pixel address width
// parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency // parameter EXT_PIX_LATENCY = 2, // external pixel buffer a->d latency
// parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay parameter ADDR_DLY = 4'h2, // extra delay of pixel address to match window delay
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
// parameter PIXEL_WIDTH = 16, // input pixel width (unsigned) // parameter PIXEL_WIDTH = 16, // input pixel width (unsigned)
parameter WND_WIDTH = 18 // input pixel width (unsigned) parameter WND_WIDTH = 18 // input pixel width (unsigned)
...@@ -71,12 +71,15 @@ module mclt_bayer_fold#( ...@@ -71,12 +71,15 @@ module mclt_bayer_fold#(
output pix_page, //!< copy pixel page (should be externally combined with first color) output pix_page, //!< copy pixel page (should be externally combined with first color)
output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive
output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
output [14:0] phases, //!< other signals // output [14:0] phases, //!< other signals
output reg var_first, //!< first of 2 fold variants (4 for monochrome, 2 left for checker) output [6:0] phases, //!< other signals
output var_pre2_first,//!< two ahead of first of 2 fold variants (4 for monochrome, 2 left for checker)
// output reg var_first, //!< first of 2 fold variants (4 for monochrome, 2 left for checker)
output reg pre_last_in //!< pre last data in output reg pre_last_in //!< pre last data in
); );
reg [6:0] in_cntr; // input phase counter reg [6:0] in_cntr; // input phase counter
reg [14:0] run_r; // run phase // reg [14:0] run_r; // run phase
reg [6:0] run_r; // run phase
reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr) reg [1:0] tile_size_r; // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
reg inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT reg inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
...@@ -102,8 +105,9 @@ module mclt_bayer_fold#( ...@@ -102,8 +105,9 @@ module mclt_bayer_fold#(
wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out wire pre_page = in_cntr == 2; // valid 1 cycle before fold_rom_out
wire var_first_d; // adding subtracting first variant of 2 folds wire var_first_d; // adding subtracting first variant of 2 folds
// reg var_pre_first;
assign phases = run_r; assign phases = run_r;
assign var_pre2_first = var_first_d;
// wire [ 3:0] bayer_1hot = { mpix_a_w[4] & mpix_a_w[0], // wire [ 3:0] bayer_1hot = { mpix_a_w[4] & mpix_a_w[0],
// mpix_a_w[4] & ~mpix_a_w[0], // mpix_a_w[4] & ~mpix_a_w[0],
...@@ -117,7 +121,8 @@ module mclt_bayer_fold#( ...@@ -117,7 +121,8 @@ module mclt_bayer_fold#(
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst) run_r <= 0; if (rst) run_r <= 0;
else run_r <= {run_r[13:0], start | (run_r[0] & ~(&in_cntr[6:0]))}; // else run_r <= {run_r[13:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
else run_r <= {run_r[5:0], start | (run_r[0] & ~(&in_cntr[6:0]))};
if (!run_r[0]) in_cntr <= 0; if (!run_r[0]) in_cntr <= 0;
else in_cntr <= in_cntr + 1; else in_cntr <= in_cntr + 1;
...@@ -144,11 +149,14 @@ module mclt_bayer_fold#( ...@@ -144,11 +149,14 @@ module mclt_bayer_fold#(
/// if (in_cntr == 2) valid_rows_r <= valid_rows_r0; /// if (in_cntr == 2) valid_rows_r <= valid_rows_r0;
/// blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]); /// blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);
/// if (run_r[9]) var_pre_first <= var_first_d;
if (run_r[10]) begin /// if (run_r[10]) begin
var_first <= var_first_d; // var_first <= var_first_d;
end /// var_first <= var_pre_first;
/// end
pre_last_in <= in_cntr[6:0] == 7'h7d; pre_last_in <= in_cntr[6:0] == 7'h7d;
...@@ -184,32 +192,19 @@ module mclt_bayer_fold#( ...@@ -184,32 +192,19 @@ module mclt_bayer_fold#(
); );
// Matching window latency with pixel data latency // Matching window latency with pixel data latency
wire [3:0] addr_dly = ADDR_DLY;
dly_var #( dly_var #(
.WIDTH(11), .WIDTH(11),
.DLY_WIDTH(4) .DLY_WIDTH(4)
) dly_pixel_addr_i ( ) dly_pixel_addr_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher // .dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher
.dly (addr_dly), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({pre_page, run_r[3], pix_a_r}), // input[0:0] .din ({pre_page, run_r[3], pix_a_r}), // input[0:0]
.dout ({pix_page, pix_re, pix_addr}) // output[0:0] .dout ({pix_page, pix_re, pix_addr}) // output[0:0]
); );
/*
dly_var #(
.WIDTH(1),
.DLY_WIDTH(4)
) dly_blank_i (
.clk (clk), // input
.rst (rst), // input
.dly (4'h0), // TODO: put correct value!
.din (blank_r), // input[0:0]
.dout (blank_d) // output[0:0]
);
*/
// Latency = 6 // Latency = 6
mclt_wnd_mul #( mclt_wnd_mul #(
.SHIFT_WIDTH (SHIFT_WIDTH), .SHIFT_WIDTH (SHIFT_WIDTH),
...@@ -243,7 +238,8 @@ module mclt_bayer_fold#( ...@@ -243,7 +238,8 @@ module mclt_bayer_fold#(
) dly_var_first_i ( ) dly_var_first_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h9), // input[3:0] // .dly (4'h9), // input[3:0]
.dly (4'h8), // input[3:0]
.din (run_r[0] && (in_cntr[0] == 0)), // input[0:0] .din (run_r[0] && (in_cntr[0] == 0)), // input[0:0]
.dout (var_first_d) // output[0:0] .dout (var_first_d) // output[0:0]
); );
......
dsp/phase_rotator.v
View file @ c4d0f3bc
...@@ -80,7 +80,9 @@ module phase_rotator#( ...@@ -80,7 +80,9 @@ module phase_rotator#(
// 0xxxxxx (>0) nnn s s xxxxxx nnn 0 0 // 0xxxxxx (>0) nnn s s xxxxxx nnn 0 0
reg [5:0] start_d; // delayed versions of start (TODO: adjust length) reg [5:0] start_d; // delayed versions of start (TODO: adjust length)
reg [7:0] cntr_h; // input sample counter reg [7:0] cntr_h_consec; // input sample counter
wire [7:0] cntr_h = DECIMATE ? {cntr_h_consec[6:2], ODD ? 1'b1: 1'b0, cntr_h_consec[1:0]}: cntr_h_consec;
reg run_h; reg run_h;
wire [7:0] cntr_v; // delayed sample counter wire [7:0] cntr_v; // delayed sample counter
wire run_v; wire run_v;
...@@ -117,12 +119,12 @@ module phase_rotator#( ...@@ -117,12 +119,12 @@ module phase_rotator#(
if (start_d[3]) shift_vr <= shift_v0; if (start_d[3]) shift_vr <= shift_v0;
if (start_d[4]) inv_checker_r2 <= inv_checker_r; if (start_d[4]) inv_checker_r2 <= inv_checker_r;
if (rst) run_h <= 0; if (rst) run_h <= 0;
else if (start) run_h <= 1; else if (start) run_h <= 1;
else if (&cntr_h[7:1] && (cntr_h[0] || DECIMATE)) run_h <= 0; else if (&cntr_h_consec[6:0] && (cntr_h[7] || DECIMATE)) run_h <= 0;
if (!run_h) cntr_h <= ODD; if (!run_h) cntr_h_consec <= 0;
else cntr_h <= cntr_h + (1 << DECIMATE); else cntr_h_consec <= cntr_h_consec + 1;
// combine horizontal and vertical counters and shifts to feed to ROM // combine horizontal and vertical counters and shifts to feed to ROM
hv_index <= mux_v ? cntr_v[4:2] : cntr_h[7:5]; // input data "down first" (transposed) hv_index <= mux_v ? cntr_v[4:2] : cntr_h[7:5]; // input data "down first" (transposed)
...@@ -247,7 +249,7 @@ module phase_rotator#( ...@@ -247,7 +249,7 @@ module phase_rotator#(
fd_dv <= pre_dv; fd_dv <= pre_dv;
if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH]; if (pre_dv) fd_out <= omux_sel ? pout_4[COEFF_WIDTH +: DSP_A_WIDTH] : pout_3[COEFF_WIDTH +: DSP_A_WIDTH];
pre_first_out <= cntr_h[7:0] == 8'hd; pre_first_out <= cntr_h_consec[7:0] == 8'hd;
end end
......
mclt_test_02.sav
View file @ c4d0f3bc
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Dec 23 06:37:18 2017 [*] Sun Dec 24 08:31:35 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_02-20171222233655371.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_02-20171224011207780.fst"
[dumpfile_mtime] "Sat Dec 23 06:37:00 2017" [dumpfile_mtime] "Sun Dec 24 08:12:14 2017"
[dumpfile_size] 1389826 [dumpfile_size] 1516519
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_02.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_02.sav"
[timestart] 275700 [timestart] 3589100
[size] 1920 1171 [size] 1814 1171
[pos] -1920 0 [pos] 0 0
*-15.350550 306400 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-14.476400 3690400 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_02. [treeopen] mclt_test_02.
[treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i. [treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
[treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i. [treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i.
...@@ -20,11 +20,16 @@ ...@@ -20,11 +20,16 @@
[treeopen] mclt_test_02.mclt16x16_i.phase_rotator_i.dsp_2_i. [treeopen] mclt_test_02.mclt16x16_i.phase_rotator_i.dsp_2_i.
[treeopen] mclt_test_02.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i. [treeopen] mclt_test_02.mclt16x16_i.phase_rotator_i.dsp_2_i.DSP48E1_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i. [treeopen] mclt_test_02.mclt_bayer_fold_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i. [treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i. [treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i. [treeopen] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.
[sst_width] 306 [treeopen] mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.
[signals_width] 327 [sst_width] 280
[signals_width] 319
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 343 [sst_vpaned_height] 343
@c00200 @c00200
...@@ -1267,7 +1272,30 @@ mclt_test_02.mclt_bayer_fold_i.start ...@@ -1267,7 +1272,30 @@ mclt_test_02.mclt_bayer_fold_i.start
mclt_test_02.mclt_bayer_fold_i.pre_last_in mclt_test_02.mclt_bayer_fold_i.pre_last_in
mclt_test_02.mclt_bayer_fold_i.pre_last_in_w mclt_test_02.mclt_bayer_fold_i.pre_last_in_w
mclt_test_02.mclt_bayer_fold_i.pre_busy mclt_test_02.mclt_bayer_fold_i.pre_busy
@800200 mclt_test_02.mclt_bayer_fold_i.pre_first_out
mclt_test_02.mclt_bayer_fold_i.dv
@22
mclt_test_02.mclt_bayer_fold_i.dout0[24:0]
mclt_test_02.mclt_bayer_fold_i.dout1[24:0]
[color] 7
mclt_test_02.mclt_bayer_fold_i.dbg_dout0[24:0]
[color] 7
mclt_test_02.mclt_bayer_fold_i.dbg_dout1[24:0]
mclt_test_02.mclt_bayer_fold_i.dtt_rd_data0[24:0]
mclt_test_02.mclt_bayer_fold_i.dtt_rd_data1[24:0]
[color] 2
mclt_test_02.mclt_bayer_fold_i.dbg_dtt_rd_data0[24:0]
[color] 2
mclt_test_02.mclt_bayer_fold_i.dbg_dtt_rd_data1[24:0]
mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
mclt_test_02.mclt_bayer_fold_i.dtt_r_data[24:0]
[color] 3
mclt_test_02.mclt_bayer_fold_i.dbg_dtt_r_data[24:0]
mclt_test_02.mclt_bayer_fold_i.dtt_out_wd[24:0]
[color] 3
mclt_test_02.mclt_bayer_fold_i.dbg_dtt_out_wd[24:0]
@c00200
-fold -fold
@28 @28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start
...@@ -1275,42 +1303,263 @@ mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start ...@@ -1275,42 +1303,263 @@ mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows[1:0] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows[1:0]
@28 @28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows_r0[1:0] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
@23
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.valid_rows_r[1:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pre_last_in mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pre_last_in
@22 @22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@1000200 @1401200
-fold -fold
@1000200
-top -top
@29
mclt_test_02.mclt_bayer_fold_i.dtt_start_out
@200
-
@800200
-rotator0
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.start
@22 @22
mclt_test_02.mclt_bayer_fold_i.pix_d[15:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.start_d[5:0]
mclt_test_02.mclt_bayer_fold_i.pix_d_r[15:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.fd_din[24:0]
mclt_test_02.mclt_bayer_fold_i.window_w[17:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.rom_a[9:0]
mclt_test_02.mclt_bayer_fold_i.window_r[17:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cos_sin_w[17:0]
mclt_test_02.mclt_bayer_fold_i.pix_wnd_r[33:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.fd_out[24:0]
mclt_test_02.mclt_bayer_fold_i.pix_wnd_r2[24:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_h[6:0]
mclt_test_02.mclt_bayer_fold_i.phases[14:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_v[6:0]
@28 @28
mclt_test_02.mclt_bayer_fold_i.var_first mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.inv_checker
mclt_test_02.mclt_bayer_fold_i.var_last
@22 @22
mclt_test_02.mclt_bayer_fold_i.signs[1:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_02.mclt_bayer_fold_i.pix_sgn_r[1:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_02.mclt_bayer_fold_i.data_cc_r[24:0] mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_vr[6:0]
mclt_test_02.mclt_bayer_fold_i.data_sc_r[24:0]
mclt_test_02.mclt_bayer_fold_i.data_sc_r2[24:0]
@28 @28
mclt_test_02.mclt_bayer_fold_i.mode_mux mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.inv_checker_r
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.inv_checker_r2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_hv[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.hv_sin
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.sign_cs[4:0]
@28
(12)mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.ph[16:0]
(1)mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.start_d[5:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.negm_1
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.negm_2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cntr_h[7:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cntr_v[7:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.pre_dv
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.pre_first_out
@1000200
-rotator0
@800200
-rotator1
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.start
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.start_d[5:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.fd_din[24:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.shift_h[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.shift_v[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.inv_checker
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.shift_hr[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.shift_v0[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.inv_checker_r
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.shift_vr[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.inv_checker_r2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.shift_hv[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.hv_sin
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.sign_cs[4:0]
@28
(12)mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.ph[16:0]
(1)mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.start_d[5:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.negm_1
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.negm_2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.cntr_h[7:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.cntr_v[7:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.pre_dv
mclt_test_02.mclt_bayer_fold_i.phase_rotator1_i.pre_first_out
@200
-
@1000200
-rotator1
@c00200
-mclt_bayer_fold
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.rst
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.tile_size_r[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.y_shft_r[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.fold_rom_out[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.sgn_w[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.signs[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_addr[8:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_re
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_page
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.window[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.en_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.regen_a
@c00200
-mclt_wnd_mul
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_in[3:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_in[3:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_shft[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_shft[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out[17:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.zero_in
(1)mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
(0)mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_full[9:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_full[9:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
@1401200
-mclt_wnd_mul
-mclt_bayer_fold
@22 @22
mclt_test_02.mclt_bayer_fold_i.pix_d[15:0]
mclt_test_02.mclt_bayer_fold_i.window_w[17:0]
mclt_test_02.mclt_bayer_fold_i.data_dtt_in[24:0] mclt_test_02.mclt_bayer_fold_i.data_dtt_in[24:0]
@28
mclt_test_02.mclt_bayer_fold_i.dtt_we
@22
mclt_test_02.mclt_bayer_fold_i.dtt_in_cntr[6:0] mclt_test_02.mclt_bayer_fold_i.dtt_in_cntr[6:0]
@28 @28
mclt_test_02.mclt_bayer_fold_i.dtt_in_page mclt_test_02.mclt_bayer_fold_i.dtt_in_page
mclt_test_02.mclt_bayer_fold_i.start_dtt mclt_test_02.mclt_bayer_fold_i.start_dtt
@c00200 @c00200
-mclt_baeyer_fold_accum
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pre_phase
@c00022
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
@28
(0)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(1)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(2)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(3)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(4)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(5)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
(6)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
@1401200
-group_end
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_d[15:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_dr[15:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_d_r[15:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.window[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_sgn_r[1:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.var_pre_first
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.var_last
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dtt_in_dv
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.mode_mux
(0)mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.phases[6:0]
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_d_r[15:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.window_r[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_wnd_r[33:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_wnd_r2_w[23:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_wnd_r2[24:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.data_cc_r[24:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.data_sc_r[24:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.data_sc_r2[24:0]
@200
-
@22
mclt_test_02.mclt_bayer_fold_i.signs[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pix_sgn_r[1:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.neg_m1
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pout1[47:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.neg_m2
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.pout2[47:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dtt_in_dsp[24:0]
@800200
-dsp1
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.cead
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qp_o_reg1[47:0]
@1000200
-dsp1
@800200
-dsp2
@28
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.cead
@22
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_02.mclt_bayer_fold_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qp_o_reg1[47:0]
@200
-
@1000200
-dsp2
@1401200
-mclt_baeyer_fold_accum
@c00200
-membuf -membuf
@8022 @8022
mclt_test_02.mclt_bayer_fold_i.dbg_diff_wara_dtt_in[8:0] mclt_test_02.mclt_bayer_fold_i.dbg_diff_wara_dtt_in[8:0]
...@@ -1474,100 +1723,6 @@ mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0] ...@@ -1474,100 +1723,6 @@ mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(8)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0] (8)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
@1401200 @1401200
-group_end -group_end
@800200
-rotator0
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.start
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_h[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_v[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.inv_checker
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_vr[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.inv_checker_r
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.inv_checker_r2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.sign_cs[4:0]
@28
(12)mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.ph[16:0]
(1)mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.start_d[5:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.negm_1
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.negm_2
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cntr_h[7:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.cntr_v[7:0]
@200
-
@1000200
-rotator0
@c00200
-mclt_bayer_fold
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.rst
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.tile_size_r[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.start
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.y_shft_r[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.blank_r
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.fold_rom_out[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.sgn_w[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.signs[1:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_addr[8:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_re
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.pix_page
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.window[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.en_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.i_mclt_fold_rom.regen_a
@c00200
-mclt_wnd_mul
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_in[3:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_in[3:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_shft[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_shft[6:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out[17:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.zero_in
(1)mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
(0)mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0]
@22
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.x_full[9:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.y_full[9:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
@28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
@1401200
-mclt_wnd_mul
-mclt_bayer_fold
@1000200 @1000200
-mclt_bayer -mclt_bayer
@800200 @800200
......
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