Commit c4c0d10a authored by Andrey Filippov's avatar Andrey Filippov

working on address export for C, fixed some copied typos in multiple files

parent e16fd10f
......@@ -62,52 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160319192210839.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -127,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160316133233827.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160319192210839.dcp</location>
</link>
</linkedResources>
</projectDescription>
......@@ -31,7 +31,14 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller
parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
// parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
// parameter FPGA_VERSION = 32'h03930079; // diff - failed
// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
// parameter FPGA_VERSION = 32'h03930077; // Restoring IOSTANDARDs - OK
// parameter FPGA_VERSION = 32'h03930076; // Trying PPDS_25 with 1.8 actual power - Stuck when applying 1.8 or 2.5V
// parameter FPGA_VERSION = 32'h03930075; // Trying IN_TERM = "UNTUNED_50"
// parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller 16365 ( 83.28%)
// parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
// parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
......
......@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
......@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
......@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
......@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end
......@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
......
......@@ -273,7 +273,7 @@
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
parameter BUFFER_DEPTH32= 10, // Block RAM buffer depth on a 32-bit port
// bits in mode control word
parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
......@@ -324,7 +324,7 @@
parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
......@@ -334,7 +334,7 @@
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
......@@ -543,16 +543,22 @@
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
`define TWEAKING_IOSTANDARD
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
// parameter PXD_IOSTANDARD = "LVCMOS25",
// parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -564,6 +570,20 @@
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
......@@ -603,16 +623,15 @@
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif DIFF_HSTL_II_18
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
......@@ -888,26 +907,6 @@
parameter BUF_CLK1X_PCLK2X = "BUFG",
// parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
// parameter DIVCLK_DIVIDE_XCLK = 1,
// parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
//`ifdef USE_XCLK2X
// parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
//`else
// parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
//`endif
// parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
// parameter PHASE_CLK2X_XCLK = 0.000,
// parameter BUF_CLK1X_XCLK = "BUFG",
// parameter BUF_CLK1X_XCLK2X = "BUFG",
// parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
// parameter DIVCLK_DIVIDE_SYNC = 1,
// parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
// parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
// parameter BUF_CLK1X_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IOSTANDARD = "SSTL15",
......@@ -928,4 +927,3 @@
\ No newline at end of file
......@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to
input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
......
......@@ -72,6 +72,7 @@ import x393_sensor
import x393_rtc
import x393_jpeg
import vrlg
import x393_export_c
__all__ = []
__version__ = 0.1
__date__ = '2015-03-01'
......@@ -357,6 +358,7 @@ USAGE
x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams)
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams)
x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams)
'''
print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__))
......@@ -390,6 +392,7 @@ USAGE
extractTasks(x393_sensor.X393Sensor, x393Sensor)
extractTasks(x393_rtc.X393Rtc, x393Rtc)
extractTasks(x393_jpeg.X393Jpeg, x393Jpeg)
extractTasks(x393_export_c.X393ExportC, x393ExportC)
for cmdLine in commands:
print ('Running task: '+str(cmdLine))
......
......@@ -711,6 +711,7 @@ MCONTR_LINTILE_REPEAT = int
CHNBUF_READ_LATENCY = int
SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str
WBUF_DLY_DFLT__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str
TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
......@@ -917,7 +918,7 @@ T_RFC__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
SENSI2C_REL_RADDR__RAW = str
FRAME_START_ADDRESS = int
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
......@@ -1151,7 +1152,7 @@ MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
CMPRS_FRMT_LMARG__RAW = str
SENSOR_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
LOGGER_BIT_DURATION = int
CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
......@@ -1165,6 +1166,7 @@ LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int
CMDFRAMESEQ_IRQ_BIT__TYPE = str
PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
......@@ -1186,6 +1188,7 @@ CMPRS_CBIT_CMODE_JP4DC__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
CMDFRAMESEQ_REL = int
......@@ -1265,7 +1268,7 @@ SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int
SCANLINE_STARTX = int
FFCLK0_DIFF_TERM__TYPE = str
WBUF_DLY_DFLT__RAW = str
HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN = int
CMPRS_CBIT_RUN_RST = int
......@@ -1293,7 +1296,7 @@ DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
WINDOW_X0__RAW = str
FRAME_START_ADDRESS = int
CMDFRAMESEQ_IRQ_BIT = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
CMPRS_GROUP_ADDR = int
......@@ -1833,6 +1836,7 @@ SENSIO_RADDR__RAW = str
DFLT_CHN_EN__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCLK_PHASE = float
CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
......@@ -1874,6 +1878,7 @@ MCONTR_BUF3_RD_ADDR__RAW = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
LOGGER_CONF_GPS_BITS = int
HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
......@@ -2075,6 +2080,7 @@ RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_INTERRUPTS__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int
......@@ -2130,6 +2136,7 @@ AXI_WR_ADDR_BITS = int
FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
......@@ -2154,6 +2161,7 @@ MULT_SAXI_ADDR = int
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
SENSOR_BASE_INC = int
MULT_SAXI_CNTRL_MASK__RAW = str
SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str
......@@ -2183,6 +2191,7 @@ DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str
LOGGER_STATUS = int
CMDFRAMESEQ_RUN_BIT__RAW = str
......@@ -966,6 +966,7 @@ ff d9
"""
"""
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "HISPI"
measure_all "*DI"
setup_all_sensors True None 0xf
#write_sensor_i2c 0 1 0 0x30700101
......
......@@ -68,9 +68,9 @@ class X393PIOSequences(object):
def schedule_ps_pio(self, #; // schedule software-control memory operation (may need to check FIFO status first)
seq_addr, # input [9:0] seq_addr; // sequence start address
page, # input [1:0] page; // buffer page number
urgent, # input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
urgent, # input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
chn, # input chn; // channel buffer to use: 0 - memory read, 1 - memory write
wait_complete): # input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete): # input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
"""
Schedule PS PIO memory transaction
<seq_addr> 10-bit sequence start address
......@@ -971,7 +971,7 @@ class X393PIOSequences(object):
2, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 2, num, show_rslt ) # chn=0, page=2, number of 32-bit words=num, show_rslt
......@@ -992,7 +992,7 @@ class X393PIOSequences(object):
3, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt
......@@ -1146,7 +1146,7 @@ class X393PIOSequences(object):
0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE );# wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # `PS_PIO_WAIT_COMPLETE );# wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt
......@@ -1234,7 +1234,7 @@ class X393PIOSequences(object):
0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
......@@ -1285,9 +1285,9 @@ class X393PIOSequences(object):
self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
vrlg.INITIALIZE_OFFSET, # input [9:0] seq_addr; # sequence start address
0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete ); # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete ); # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
# Wait PS PIO sequence DOEN
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE, 1 , 2.0); # wait FIFO not half full, sync sequences, timeout 2 sec
......
......@@ -78,6 +78,7 @@ GLBL_WINDOW = None
# for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
......@@ -188,6 +189,11 @@ class X393SensCmprs(object):
if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1)
def setupSensorsPower(self, ifaceType, quiet=0):
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
"""
Set interface voltage and turn on power for interface and the sensors
......@@ -212,6 +218,8 @@ class X393SensCmprs(object):
if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
# for sub_pair in (0,1):
# self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
# def getSensorInterfaceType(self):
# """
......@@ -220,12 +228,15 @@ class X393SensCmprs(object):
# """
# return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def setupSensorsPowerClock(self,quiet=0):
def setupSensorsPowerClock(self, setPower=False, quiet=0):
"""
Set interface voltage for all sensors, clock for frequency and sensor power
for the interface matching bitstream file
Not possible for diff. termination - power should be set before the bitstream
"""
ifaceType = self.x393Sensor.getSensorInterfaceType();
if setPower:
if quiet == 0:
print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType))
for sub_pair in (0,1):
......@@ -1158,8 +1169,10 @@ class X393SensCmprs(object):
self.setSensorClock(freq_MHz = 24.0)
"""
if verbose >0 :
print ("===================== Set up sensor and interface power, clock generator =========================")
self.setupSensorsPowerClock(quiet = (verbose >0))
# print ("===================== Set up sensor and interface power, clock generator =========================")
print ("===================== Set up clock generator (power should be set before bitstream) =========================")
self.setupSensorsPowerClock(setPower=False, # Should be set before bitstream
quiet = (verbose >0))
if exit_step == 1: return False
if verbose >0 :
print ("===================== GPIO_SETUP =========================")
......
......@@ -40,8 +40,12 @@ import vrlg # global parameters
import x393_axi_control_status
import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178
FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
FPGA_DEVCFG_CTRL = 0xf8007000 # &= (1 << 30) - reset
FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c
#SAVE_FILE_NAME="Some_name"# None
......@@ -86,6 +90,25 @@ class X393Utils(object):
else:
for d in data:
self.x393_mem.write_mem(FPGA_RST_CTRL,d)
def fpga_shutdown(self,
quiet = 1):
if quiet < 2:
print ("fpga_shutdown(): FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
if quiet < 2:
print ("fpga_shutdown(): Reset ON")
self.reset(0)
if quiet < 2:
print ("fpga_shutdown(): Disabling level shifters")
# turn off level shifters
self.x393_mem.write_mem(FPGA_LVL_SHFTR,0)
old_devcfg_ctrl = self.x393_mem.read_mem(FPGA_DEVCFG_CTRL)
if quiet < 2:
print ("fpga_shutdown():FPGA_DEVCFG_CTRL was 0x%08x"%(old_devcfg_ctrl))
print ("fpga_shutdown(): Applying PROG_B")
self.x393_mem.write_mem(FPGA_DEVCFG_CTRL,old_devcfg_ctrl & ~(1 << 30))
def bitstream(self,
bitfile=None,
quiet=1):
......@@ -100,8 +123,8 @@ class X393Utils(object):
# POWER393_PATH = '/sys/devices/elphel393-pwr.1'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
# with open (POWER393_PATH + "/channels_dis","w") as f:
# print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
......
......@@ -98,6 +98,7 @@ module sens_10398 #(
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -368,6 +369,7 @@ module sens_10398 #(
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
......@@ -68,6 +68,7 @@ module sens_hispi12l4#(
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -197,6 +198,7 @@ module sens_hispi12l4#(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
......@@ -61,6 +61,7 @@ module sens_hispi_clock#(
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -97,7 +98,22 @@ module sens_hispi_clock#(
assign ps_rdy = (HISPI_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (HISPI_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
generate
if (HISPI_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
......@@ -111,6 +127,8 @@ module sens_hispi_clock#(
.I (clp_p), // input
.IB (clk_n) // input
);
end
endgenerate
generate
if (HISPI_DELAY_CLK == "TRUE") begin
idelay_nofine # (
......
......@@ -42,6 +42,7 @@ module sens_hispi_din #(
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -67,6 +68,21 @@ module sens_hispi_din #(
generate
genvar i;
for (i=0; i < HISPI_NUMLANES; i=i+1) begin: din_block
if (HISPI_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
......@@ -80,6 +96,7 @@ module sens_hispi_din #(
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
......
......@@ -81,7 +81,7 @@ module sensor_channel#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
......@@ -263,6 +263,7 @@ module sensor_channel#(
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -788,6 +789,7 @@ module sensor_channel#(
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
......@@ -49,7 +49,7 @@ module sensor_i2c#(
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
......
......@@ -49,7 +49,7 @@ module sensor_i2c_io#(
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA