working on address export for C, fixed some copied typos in multiple files (c4c0d10a) · Commits · Elphel / x393

.project

+11 −11

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		@@ -62,52 +62,52 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160316133233827.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160319192210839.log</location>
		</link>
		<link>
		<name>vivado_state/x393-opt-phys.dcp</name>
		@@ -127,7 +127,7 @@
		<link>
		<name>vivado_state/x393-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160316133233827.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160319192210839.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

fpga_version.vh

+10 −3

Original line number	Diff line number	Diff line
		@@ -31,7 +31,14 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*******************************************************************************/
		parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller
		parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
		// parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
		// parameter FPGA_VERSION = 32'h03930079; // diff - failed
		// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
		// parameter FPGA_VERSION = 32'h03930077; // Restoring IOSTANDARDs - OK
		// parameter FPGA_VERSION = 32'h03930076; // Trying PPDS_25 with 1.8 actual power - Stuck when applying 1.8 or 2.5V
		// parameter FPGA_VERSION = 32'h03930075; // Trying IN_TERM = "UNTUNED_50"
		// parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller 16365 ( 83.28%)
		// parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
		// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
		// parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)

includes/tasks_tests_memory.vh

+14 −14

Original line number	Diff line number	Diff line
		@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
		0, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished

		wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
		read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
		@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
		1, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
		read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
		// task wait_read_queue_empty; - alternative way to check fo empty read queue
		@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
		2, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
		read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
		end
		@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
		0, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		// tempoary - for debugging:
		// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
		end
		@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
		3, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
		2, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
		READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
		1, // input [1:0] page; // buffer page number
		0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
		0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
		0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
		read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
		end

includes/x393_parameters.vh

+176 −178

Original line number	Diff line number	Diff line
		@@ -273,7 +273,7 @@
		// spread long-programming (tiled) over fast-programming (linear) requests.
		// But that should not be too big to maintain 2-level priorities
		parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
		parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
		parameter BUFFER_DEPTH32= 10, // Block RAM buffer depth on a 32-bit port

		// bits in mode control word
		parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
		@@ -324,7 +324,7 @@
		parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
		parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
		parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
		parameter MEMBRIDGE_MODE= 'h7, // frame width in 64-bit words (partial last page in each line)
		parameter MEMBRIDGE_MODE= 'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
		parameter MEMBRIDGE_STATUS_REG= 'h3b,

		parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
		@@ -334,7 +334,7 @@
		parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel

		parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
		parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
		parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR


		parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
		@@ -543,16 +543,22 @@
		parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

		// parameters for the sensor-synchronous clock PLL
		`define TWEAKING_IOSTANDARD
		`ifdef HISPI
		parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
		parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,
		`ifdef TWEAKING_IOSTANDARD
		parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
		parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
		// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
		// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
		`else
		parameter PXD_IOSTANDARD = "LVCMOS18",
		parameter SENSI2C_IOSTANDARD = "LVCMOS18",
		// parameter PXD_IOSTANDARD = "LVCMOS25",
		// parameter SENSI2C_IOSTANDARD = "LVCMOS25",
		`endif

		`else
		parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		@@ -564,6 +570,20 @@
		parameter SENSI2C_IOSTANDARD = "LVCMOS25",

		`endif

		`ifdef TWEAKING_IOSTANDARD
		parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
		parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
		// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
		// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
		parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
		`else
		parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
		parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
		parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
		`endif


		// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",

		@@ -603,16 +623,15 @@
		parameter HISPI_FIFO_DEPTH = 4,
		parameter HISPI_FIFO_START = 7,
		parameter HISPI_CAPACITANCE = "DONT_CARE",
		parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
		parameter HISPI_DQS_BIAS = "TRUE",
		parameter HISPI_IBUF_DELAY_VALUE = "0",
		parameter HISPI_IBUF_LOW_PWR = "TRUE",
		parameter HISPI_IFD_DELAY_VALUE = "AUTO",
		// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
		parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
		// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
		//`endif DIFF_HSTL_II_18


		parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
		parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
		parameter CMPRS_BASE_INC = 'h10,
		@@ -888,26 +907,6 @@
		parameter BUF_CLK1X_PCLK2X = "BUFG",


		// parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
		// parameter DIVCLK_DIVIDE_XCLK = 1,
		// parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
		//`ifdef USE_XCLK2X
		// parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
		//`else
		// parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
		//`endif
		// parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
		// parameter PHASE_CLK2X_XCLK = 0.000,
		// parameter BUF_CLK1X_XCLK = "BUFG",
		// parameter BUF_CLK1X_XCLK2X = "BUFG",

		// parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
		// parameter DIVCLK_DIVIDE_SYNC = 1,
		// parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
		// parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
		// parameter BUF_CLK1X_SYNC = "BUFG",


		parameter MEMCLK_CAPACITANCE = "DONT_CARE",
		parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
		parameter MEMCLK_IOSTANDARD = "SSTL15",
		@@ -928,4 +927,3 @@




		No newline at end of file

includes/x393_tasks_ps_pio.vh

+1 −1

Original line number	Diff line number	Diff line
		@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to
		input [1:0] page; // buffer page number
		input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
		input chn; // channel buffer to use: 0 - memory read, 1 - memory write
		input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
		input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
		begin
		// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
		write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});

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