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Elphel
x393
Commits
bf5ea2bb
Commit
bf5ea2bb
authored
Jul 01, 2016
by
Andrey Filippov
Browse files
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Plain Diff
working to add cocotb simualtion
parent
bb9fdc40
Changes
11
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Showing
11 changed files
with
1214 additions
and
77 deletions
+1214
-77
.editor_defines
.editor_defines
+1
-0
.gitignore
.gitignore
+4
-1
com.elphel.vdt.FPGA_project.prefs
.settings/com.elphel.vdt.FPGA_project.prefs
+3
-1
com.elphel.vdt.cocotb.prefs
.settings/com.elphel.vdt.cocotb.prefs
+8
-0
x393_dut.v
cocotb/x393_dut.v
+712
-51
x393buses.py
cocotb/x393buses.py
+335
-0
x393coco_02.py
cocotb/x393coco_02.py
+107
-0
simul_sensor12bits.v
simulation_modules/simul_sensor12bits.v
+10
-3
system_defines.vh
system_defines.vh
+11
-6
oserdes_mem.v
wrap/oserdes_mem.v
+1
-0
x393_testbench04.sav
x393_testbench04.sav
+22
-15
No files found.
.editor_defines
View file @
bf5ea2bb
// This file may be used to define same pre-processor macros to be included into each parsed file opened in the editor
// This file may be used to define same pre-processor macros to be included into each parsed file opened in the editor
// `define IVERILOG 1 // if IVERILOG is defined, editor will use simulator's "point of view", if not that of synthesis.
// `define IVERILOG 1 // if IVERILOG is defined, editor will use simulator's "point of view", if not that of synthesis.
`define COCOTB 1 // if IVERILOG is defined, editor will use simulator's "point of view", if not that of synthesis.
`include "system_defines.vh"
`include "system_defines.vh"
\ No newline at end of file
.gitignore
View file @
bf5ea2bb
...
@@ -52,3 +52,6 @@ simulation_data/*.jpeg
...
@@ -52,3 +52,6 @@ simulation_data/*.jpeg
.pydevproject
.pydevproject
#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
workingSet.psf
workingSet.psf
*.fst
cocotb/Makefile
cocotb/sim_build
\ No newline at end of file
.settings/com.elphel.vdt.FPGA_project.prefs
View file @
bf5ea2bb
FPGA_project_0_SimulationTopFile=x393_testbench03.tf
FPGA_project_0_SimulationTopFile=x393_testbench03.tf
FPGA_project_1_SimulationTopModule=x393_testbench03
FPGA_project_1_SimulationTopModule=x393_testbench03
FPGA_project_2_DUTTopFile=cocotb/x393_dut.v
FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_3_DUTTopModule=x393_dut
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@->
eclipse.preferences.version=1
eclipse.preferences.version=1
.settings/com.elphel.vdt.cocotb.prefs
0 → 100644
View file @
bf5ea2bb
cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v
cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->
eclipse.preferences.version=1
cocotb/x393_dut.v
View file @
bf5ea2bb
This diff is collapsed.
Click to expand it.
cocotb/x393buses.py
0 → 100644
View file @
bf5ea2bb
This diff is collapsed.
Click to expand it.
cocotb/x393coco_02.py
0 → 100644
View file @
bf5ea2bb
from
__future__
import
print_function
"""
# Copyright (C) 2016, Elphel.inc.
# Simulation code for cocotb simulation for x393 project
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2016 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
"""
import
cocotb
from
cocotb.triggers
import
Timer
from
x393buses
import
MAXIGPMaster
from
cocotb.drivers
import
BitDriver
from
cocotb.triggers
import
Timer
,
RisingEdge
,
ReadOnly
from
cocotb.result
import
ReturnValue
,
TestFailure
,
TestError
,
TestSuccess
import
logging
class
X393_cocotb_02
(
object
):
def
__init__
(
self
,
dut
,
debug
=
True
):
self
.
dut
=
dut
self
.
axiwr
=
MAXIGPMaster
(
entity
=
dut
,
name
=
"dutm0"
,
clock
=
dut
.
dutm0_aclk
,
rdlag
=
0
,
blag
=
0
)
# self.clock = dut.dutm0_aclk
level
=
logging
.
DEBUG
if
debug
else
logging
.
WARNING
self
.
axiwr
.
log
.
setLevel
(
level
)
def
print_test
(
self
):
print
(
"test"
);
@
cocotb
.
coroutine
def
run_test
(
dut
,
data_in
=
None
,
config_coroutine
=
None
,
idle_inserter
=
None
,
backpressure_inserter
=
None
):
print
(
"run_test(): starting X393_cocotb_02(dut) init"
)
tb
=
X393_cocotb_02
(
dut
)
print
(
"run_test(): X393_cocotb_02(dut) done"
)
yield
Timer
(
10000
)
# print ("run_test(): First timer wait done")
while
dut
.
reset_out
.
value
.
get_binstr
()
!=
"1"
:
# print ("Waiting for reset .., reset_out=",dut.reset_out.value)
yield
Timer
(
10000
)
while
dut
.
reset_out
.
value
:
# print ("Waiting for reset ..,reset_out=",dut.reset_out.value)
yield
Timer
(
10000
)
# print ("Waiting for reset over...,reset_out=",dut.reset_out.value)
# for i in range (10):
# yield RisingEdge(tb.clock)
# print ("10 clocks later: reset_out=",dut.reset_out.value)
# tb.print_test();
# yield tb.axiwr.print_test();
# yield tb.axiwr.print_test();
# yield tb.axiwr.print_test();
yield
tb
.
axiwr
.
axi_write
(
address
=
0x1234
,
value
=
[
0
,
1
,
2
,
3
,
4
,
5
,
6
,
7
,
8
],
byte_enable
=
None
,
address_latency
=
0
,
data_latency
=
0
,
id
=
0
,
dsize
=
2
,
burst
=
1
)
dut
.
_log
.
info
(
"Almost there"
)
yield
Timer
(
1000
)
dut
.
_log
.
info
(
"Ok!"
)
# raise TestSuccess("All done for now")
"""
MODULE=test_endian_swapper
class EndianSwapperTB(object):
def convert_string(txt):
number=0
for c in txt:
number = (number << 8) + ord(c)
return number
@cocotb.test()
def hello_test(dut):
yield Timer(100)
for i in range (1000):
if i == 200:
dut.TEST_TITLE=convert_string("passed 200")
elif i == 400:
dut.TEST_TITLE=convert_string("passed 400")
dut.maxigp0arvalid=0
yield Timer(10000)
dut.maxigp0arvalid=1
yield Timer(10000)
"""
\ No newline at end of file
simulation_modules/simul_sensor12bits.v
View file @
bf5ea2bb
...
@@ -145,6 +145,12 @@ assign #tDDO1 HACT= ihact;
...
@@ -145,6 +145,12 @@ assign #tDDO1 HACT= ihact;
assign
#
tDDO1
VACT
=
ivact
;
assign
#
tDDO1
VACT
=
ivact
;
assign
#
tDDO1
VACT1
=
ivact
&&
!
ivact1
;
assign
#
tDDO1
VACT1
=
ivact
&&
!
ivact1
;
assign
DCLK
=
c
;
assign
DCLK
=
c
;
`ifndef
ROOTPATH
`include
"IVERILOG_INCLUDE.v"
// SuppressThisWarning VEditor - maybe not used
`ifndef
ROOTPATH
`define
ROOTPATH
"."
`endif
`endif
initial
begin
initial
begin
//parameter ramp = 1; // 0 - ramp, 1 - random
//parameter ramp = 1; // 0 - ramp, 1 - random
...
@@ -162,12 +168,13 @@ initial begin
...
@@ -162,12 +168,13 @@ initial begin
$
display
(
" -- t_preHACT = %d "
,
t_preHACT
)
;
$
display
(
" -- t_preHACT = %d "
,
t_preHACT
)
;
$
display
(
" -- new_bayer = %d "
,
new_bayer
)
;
$
display
(
" -- new_bayer = %d "
,
new_bayer
)
;
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
if
(
SENSOR_IMAGE_TYPE
==
"NORM"
)
$
readmemh
(
"input_data/sensor.dat"
,
sensor_data
)
;
if
(
SENSOR_IMAGE_TYPE
==
"NORM"
)
$
readmemh
(
{
`ROOTPATH
,
"/input_data/sensor.dat"
}
,
sensor_data
)
;
else
if
(
SENSOR_IMAGE_TYPE
==
"RUN1"
)
$
readmemh
(
"input_data/sensor_run1.dat"
,
sensor_data
)
;
else
if
(
SENSOR_IMAGE_TYPE
==
"RUN1"
)
$
readmemh
(
{
`ROOTPATH
,
"/input_data/sensor_run1.dat"
}
,
sensor_data
)
;
else
begin
else
begin
$
display
(
"WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat"
,
SENSOR_IMAGE_TYPE
)
;
$
display
(
"WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat"
,
SENSOR_IMAGE_TYPE
)
;
$
readmemh
(
"input_data/sensor.dat"
,
sensor_data
)
;
$
readmemh
(
{
`ROOTPATH
,
"/input_data/sensor.dat"
}
,
sensor_data
)
;
end
end
c
=
0
;
c
=
0
;
// {ibpf,ihact,ivact}=0;
// {ibpf,ihact,ivact}=0;
...
...
system_defines.vh
View file @
bf5ea2bb
...
@@ -83,12 +83,17 @@
...
@@ -83,12 +83,17 @@
`ifdef IVERILOG
`ifdef IVERILOG
`define SIMULATION
`define SIMULATION
`define OPEN_SOURCE_ONLY
`define OPEN_SOURCE_ONLY
`else
`endif
`ifdef COCOTB
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif
`ifdef CVC
`ifdef CVC
`define SIMULATION
`define SIMULATION
`define OPEN_SOURCE_ONLY
`define OPEN_SOURCE_ONLY
`endif // CVC
`endif // CVC
`endif // IVERILOG
// will not use simultaneous reset in shift registers, just and input data with ~rst
// will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1
`define SHREG_SEQUENTIAL_RESET 1
...
...
wrap/oserdes_mem.v
View file @
bf5ea2bb
...
@@ -38,6 +38,7 @@
...
@@ -38,6 +38,7 @@
*/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
`include
"system_defines.vh"
module
oserdes_mem
#(
module
oserdes_mem
#(
parameter
MODE_DDR
=
"TRUE"
parameter
MODE_DDR
=
"TRUE"
)
(
)
(
...
...
x393_testbench04.sav
View file @
bf5ea2bb
[*]
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*]
Sun Jun 19 16:45:45
2016
[*]
Tue Jun 28 14:16:28
2016
[*]
[*]
[dumpfile] "/home/
elphel/git/x393/simulation/x393_testbench03-20160618120329839
.fst"
[dumpfile] "/home/
andrey/git/x393/simulation/x393_testbench03-20160627204141983
.fst"
[dumpfile_mtime] "
Sat Jun 18 18:21:41
2016"
[dumpfile_mtime] "
Tue Jun 28 03:05:44
2016"
[dumpfile_size] 15
2787343
[dumpfile_size] 15
3062065
[savefile] "/home/
elphel
/git/x393/x393_testbench04.sav"
[savefile] "/home/
andrey
/git/x393/x393_testbench04.sav"
[timestart] 0
[timestart]
2639520
0
[size] 1736
841
[size] 1736
1145
[pos]
0 0
[pos]
1920 38
*-
24.755907 543008
00 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-
16.746853 266600
00 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.read_compressor_frame_irq.
[treeopen] x393_testbench03.read_compressor_frame_irq.
[treeopen] x393_testbench03.read_contol_register_irq.
[treeopen] x393_testbench03.read_contol_register_irq.
...
@@ -48,26 +48,34 @@
...
@@ -48,26 +48,34 @@
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_generate1_i.genblk2.status_generate_only_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_generate1_i.genblk2.status_generate_only_i.
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.
[sst_width] 395
[sst_width] 395
[signals_width] 334
[signals_width] 334
[sst_expanded] 1
[sst_expanded] 1
[sst_vpaned_height]
249
[sst_vpaned_height]
356
@820
@820
x393_testbench03.TEST_TITLE[639:0]
x393_testbench03.TEST_TITLE[639:0]
@28
x393_testbench03.CLK
x393_testbench03.x393_i.axi_aclk
x393_testbench03.x393_i.ps7_i.MAXIGP0ARESETN
x393_testbench03.x393_i.ps7_i.MAXIGP0ARLOCK[1:0]
@22
x393_testbench03.x393_i.ps7_i.MAXIGP0ARQOS[3:0]
@28
x393_testbench03.AR_SET_CMD
x393_testbench03.AR_READY
@29
x393_testbench03.ARSIZE_IN_r[1:0]
@200
@200
-
-
@800200
@800200
...
@@ -84,7 +92,6 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.px
...
@@ -84,7 +92,6 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.px
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.eof
@29
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.hact
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.hact
@1000200
@1000200
-chn1
-chn1
...
...
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