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Commit bdfcabf1 authored by Andrey Filippov's avatar Andrey Filippov
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Working a top-level compressor module

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axi/mult_saxi_wr_inbuf.v
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/******************************************************************************* /*******************************************************************************
* Module: mult_saxi_wr_inbuf * Module: mult_saxi_wr_inbuf
* Date:2015-07-11 * Date:2015-07-11
* Author: andrey * Author: Andrey Filippov
* Description: Channel buffer with width conversion to 32 to use with mult_saxi_wr * Description: Channel buffer with width conversion to 32 to use with mult_saxi_wr
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
compressor_jp/compressor393.v 0 → 100644
View file @ bdfcabf1
/*******************************************************************************
* Module: compressor393
* Date:2015-07-14
* Author: Andrey Filippov
* Description: Top module containg all compressor channels
*
* Copyright (c) 2015 Elphel, Inc .
* compressor393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* compressor393.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module compressor393 # (
parameter CMPRS_NUM_AFI_CHN = 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_MASK= 'h7f0,
parameter CMPRS_STATUS_REG_BASE= 'h10,
parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations
parameter CMPRS_AFIMUX_REG_ADDR1= 'h1c, // Uses 4 locations
parameter CMPRS_STATUS_REG_INC= 1,
parameter CMPRS_HIFREQ_REG_INC= 1,
// parameter CMPRS_ADDR= 'h120, //TODO: assign valid address
parameter CMPRS_MASK= 'h7f8,
parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1,
parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_TABLES= 6, // 6..7
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
// Bit-fields in compressor control word
parameter CMPRS_CBIT_RUN = 2, // bit # to control compressor run modes
parameter CMPRS_CBIT_RUN_BITS = 2, // number of bits to control compressor run modes
parameter CMPRS_CBIT_QBANK = 6, // bit # to control quantization table page
parameter CMPRS_CBIT_QBANK_BITS = 3, // number of bits to control quantization table page
parameter CMPRS_CBIT_DCSUB = 8, // bit # to control extracting DC components bypassing DCT
parameter CMPRS_CBIT_DCSUB_BITS = 1, // bit # to control extracting DC components bypassing DCT
parameter CMPRS_CBIT_CMODE = 13, // bit # to control compressor color modes
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
parameter CMPRS_CBIT_RUN_STANDALONE = 2'h2, // enable compressor, compress single frame from memory (async)
parameter CMPRS_CBIT_RUN_ENABLE = 2'h3, // enable compressor, enable synchronous compression mode
parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
parameter CMPRS_COLOR20 = 1, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer (not implemented)
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word
parameter CMPRS_FRMT_MBRM1_BITS = 13, // number of bits in number of macroblock rows minus 1 field in format word
parameter CMPRS_FRMT_LMARG = 26, // bit # of left margin field in format word
parameter CMPRS_FRMT_LMARG_BITS = 5, // number of bits in left margin field in format word
parameter CMPRS_CSAT_CB = 0, // bit # of number of blue scale field in color saturation word
parameter CMPRS_CSAT_CB_BITS = 10, // number of bits in blue scale field in color saturation word
parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_TIMEOUT_BITS= 12,
parameter CMPRS_TIMEOUT= 1000, // mclk cycles
parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7
parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
)(
input rst, // global reset
input xclk, // global clock input, compressor single clock rate
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
// programming interface
input mclk, // global system/memory clock
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// Buffer interfaces
input xfer_reset_page_rd_chn0, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn0, // advance to next page memory interface writes to
input buf_we_chn0, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn0, // data out
input page_ready_chn0, // single mclk (posedge)
output next_page_chn0, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
input xfer_reset_page_rd_chn1, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn1, // advance to next page memory interface writes to
input buf_we_chn1, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn1, // data out
input page_ready_chn1, // single mclk (posedge)
output next_page_chn1, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
input xfer_reset_page_rd_chn2, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn2, // advance to next page memory interface writes to
input buf_we_chn2, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn2, // data out
input page_ready_chn2, // single mclk (posedge)
output next_page_chn2, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
input xfer_reset_page_rd_chn3, // from mcntrl_tiled_rw (
input buf_wpage_nxt_chn3, // advance to next page memory interface writes to
input buf_we_chn3, // @!mclk write buffer from memory, increment write
input [63:0] buf_din_chn3, // data out
input page_ready_chn3, // single mclk (posedge)
output next_page_chn3, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// statistics data was not used in late nc353
// input dccout, //enable output of DC and HF components for brightness/color/focus adjustments
// input [2:0] hfc_sel, // [2:0] (for autofocus) only components with both spacial frequencies higher than specified will be added
// output statistics_dv,
// output [15:0] statistics_do,
// Timestamp messages (@mclk) - combine to a single ts_data?
input ts_pre_stb_chn0, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn0, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input ts_pre_stb_chn1, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn1, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input ts_pre_stb_chn2, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn2, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input ts_pre_stb_chn3, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data_chn3, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
// Outputs for interrupts generation
output eof_written_mclk_chn0,
output stuffer_done_mclk_chn0,
output eof_written_mclk_chn1,
output stuffer_done_mclk_chn1,
output eof_written_mclk_chn2,
output stuffer_done_mclk_chn2,
output eof_written_mclk_chn3,
output stuffer_done_mclk_chn3,
// frame input synchronization
input vsync_late_chn0, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands
// that should arrive before it
input vsync_late_chn1,
input vsync_late_chn2,
input vsync_late_chn3,
// master (sensor) with slave (compressor) synchronization I/Os
output frame_start_dst_chn0, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn0,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src_chn0, // current frame number (for multi-frame ranges) in the source (sensor) channel
input frame_done_src_chn0, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// frame_done_src is later than line_unfinished_src/ frame_number_src changes
// Used withe a single-frame buffers
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn0,// number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn0, // current frame number (for multi-frame ranges) in this (compressor channel
input frame_done_dst_chn0, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353
output suspend_chn0, // suspend reading data for this channel - waiting for the source data
output frame_start_dst_chn1,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn1,
input [LAST_FRAME_BITS-1:0] frame_number_src_chn1,
input frame_done_src_chn1,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn1,
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn1,
input frame_done_dst_chn1,
output suspend_chn1,
output frame_start_dst_chn2,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn2,
input [LAST_FRAME_BITS-1:0] frame_number_src_chn2,
input frame_done_src_chn2,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn2,
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn2,
input frame_done_dst_chn2,
output suspend_chn2,
output frame_start_dst_chn3,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src_chn3,
input [LAST_FRAME_BITS-1:0] frame_number_src_chn3,
input frame_done_src_chn3,
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst_chn3,
input [LAST_FRAME_BITS-1:0] frame_number_dst_chn3,
input frame_done_dst_chn3,
output suspend_chn3,
// AXI_HP inteface (single/dual). afi indices - relative (0,1) may actually be connected to 1,2 (or only to 1)
input hclk,
// write address
output [31:0] afi0_awaddr,
output afi0_awvalid,
input afi0_awready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi0_awid,
output [ 1:0] afi0_awlock,
output [ 3:0] afi0_awcache,
output [ 2:0] afi0_awprot,
output [ 3:0] afi0_awlen,
output [ 2:0] afi0_awsize,
output [ 1:0] afi0_awburst,
output [ 3:0] afi0_awqos,
// write data
output [63:0] afi0_wdata,
output afi0_wvalid,
input afi0_wready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi0_wid,
output afi0_wlast,
output [ 7:0] afi0_wstrb,
// write response
input afi0_bvalid,
output afi0_bready,
input [ 5:0] afi0_bid,
input [ 1:0] afi0_bresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi0_wcount,
input [ 5:0] afi0_wacount,
output afi0_wrissuecap1en,
// write address, second channel
output [31:0] afi1_awaddr,
output afi1_awvalid,
input afi1_awready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi1_awid,
output [ 1:0] afi1_awlock,
output [ 3:0] afi1_awcache,
output [ 2:0] afi1_awprot,
output [ 3:0] afi1_awlen,
output [ 2:0] afi1_awsize,
output [ 1:0] afi1_awburst,
output [ 3:0] afi1_awqos,
// write data
output [63:0] afi1_wdata,
output afi1_wvalid,
input afi1_wready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi1_wid,
output afi1_wlast,
output [ 7:0] afi1_wstrb,
// write response
input afi1_bvalid,
output afi1_bready,
input [ 5:0] afi1_bid,
input [ 1:0] afi1_bresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi1_wcount,
input [ 5:0] afi1_wacount,
output afi1_wrissuecap1en
);
wire [47:0] status_ad_mux;
wire [5:0] status_rq_mux;
wire [5:0] status_start_mux;
wire [3:0] xfer_reset_page_rd = {xfer_reset_page_rd_chn3, xfer_reset_page_rd_chn2, xfer_reset_page_rd_chn1, xfer_reset_page_rd_chn0};
wire [3:0] buf_wpage_nxt = {buf_wpage_nxt_chn3, buf_wpage_nxt_chn2, buf_wpage_nxt_chn1, buf_wpage_nxt_chn0};
wire [3:0] buf_we = {buf_we_chn3, buf_we_chn2, buf_we_chn1, buf_we_chn0};
wire [255:0] buf_din = {buf_din_chn3, buf_din_chn2, buf_din_chn1, buf_din_chn0};
wire [3:0] page_ready = {page_ready_chn3, page_ready_chn2, page_ready_chn1, page_ready_chn0};
wire [3:0] next_page;
assign {next_page_chn3, next_page_chn2, next_page_chn1, next_page_chn0} = next_page;
// Timestamp messages (@mclk) - combine to a single ts_data?
wire [3:0] ts_pre_stb = {ts_pre_stb_chn3, ts_pre_stb_chn2, ts_pre_stb_chn1, ts_pre_stb_chn0};
wire [31:0] ts_data = {ts_data_chn3, ts_data_chn2, ts_data_chn1, ts_data_chn0};
// Outputs for interrupts generation
wire [3:0] eof_written_mclk;
wire [3:0] stuffer_done_mclk;
assign {eof_written_mclk_chn3, eof_written_mclk_chn2, eof_written_mclk_chn1, eof_written_mclk_chn0} = eof_written_mclk;
assign {stuffer_done_mclk_chn3, stuffer_done_mclk_chn2, stuffer_done_mclk_chn1, stuffer_done_mclk_chn0} = stuffer_done_mclk;
// frame input synchronization
wire [3:0] vsync_late = {vsync_late_chn3, vsync_late_chn2, vsync_late_chn1, vsync_late_chn0};
// master (sensor) with slave (compressor) synchronization I/Os
wire [3:0] frame_start_dst;
assign {frame_start_dst_chn3, frame_start_dst_chn2, frame_start_dst_chn1, frame_start_dst_chn0} = frame_start_dst;
wire [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_src = {line_unfinished_src_chn3, line_unfinished_src_chn2, line_unfinished_src_chn1, line_unfinished_src_chn0};
wire [4*LAST_FRAME_BITS-1:0] frame_number_src = {frame_number_src_chn3, frame_number_src_chn2, frame_number_src_chn1, frame_number_src_chn0};
wire [3:0] frame_done_src = {frame_done_src_chn3, frame_done_src_chn2, frame_done_src_chn1, frame_done_src_chn0};
wire [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_dst = {line_unfinished_dst_chn3, line_unfinished_dst_chn2, line_unfinished_dst_chn1, line_unfinished_dst_chn0};
wire [4*LAST_FRAME_BITS-1:0] frame_number_dst = {frame_number_dst_chn3, frame_number_dst_chn2, frame_number_dst_chn1, frame_number_dst_chn0};
wire [3:0] frame_done_dst = {frame_done_dst_chn3, frame_done_dst_chn2, frame_done_dst_chn1, frame_done_dst_chn0};
wire [3:0] suspend;
assign {suspend_chn3, suspend_chn2, suspend_chn1, suspend_chn0} = suspend;
// signals to connect to AFI multiplexers
wire [3:0] fifo_rst;
wire [3:0] fifo_ren;
wire [255:0] fifo_rdata;
wire [3:0] fifo_eof; //SuppressThisWarning VEditor : Not used?
wire [3:0] eof_written;
wire [3:0] fifo_flush;
wire [31:0] fifo_count;
/* Instance template for module status_router8 */
status_router8 status_router8_i (
.rst (rst), // input
.clk (mclk), // input
.db_in0 (status_ad_mux[ 0 +: 8]), // input[7:0]
.rq_in0 (status_rq_mux[0]), // input
.start_in0 (status_start_mux[0]), // output
.db_in1 (status_ad_mux[ 8 +: 8]), // input[7:0]
.rq_in1 (status_rq_mux[1]), // input
.start_in1 (status_start_mux[1]), // output
.db_in2 (status_ad_mux[ 16 +: 8]), // input[7:0]
.rq_in2 (status_rq_mux[2]), // input
.start_in2 (status_start_mux[2]), // output
.db_in3 (status_ad_mux[ 24 +: 8]), // input[7:0]
.rq_in3 (status_rq_mux[3]), // input
.start_in3 (status_start_mux[3]), // output
.db_in4 (status_ad_mux[ 32 +: 8]), // input[7:0]
.rq_in4 (status_rq_mux[4]), // input
.start_in4 (status_start_mux[4]), // output
.db_in5 (status_ad_mux[ 40 +: 8]), // input[7:0]
.rq_in5 (status_rq_mux[5]), // input
.start_in5 (status_start_mux[5]), // output
.db_in6 (0), // input[7:0]
.rq_in6 (0), // input
.start_in6 (), // output
.db_in7 (0), // input[7:0]
.rq_in7 (0), // input
.start_in7 (), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
);
generate
genvar i;
for (i=0; i < 4; i=i+1) begin: cmprs_channel_block
jp_channel #(
.CMPRS_NUMBER (i),
.CMPRS_GROUP_ADDR (CMPRS_GROUP_ADDR),
.CMPRS_BASE_INC (CMPRS_BASE_INC),
.CMPRS_STATUS_REG_BASE (CMPRS_STATUS_REG_BASE),
.CMPRS_HIFREQ_REG_BASE (CMPRS_HIFREQ_REG_BASE),
.CMPRS_STATUS_REG_INC (CMPRS_STATUS_REG_INC),
.CMPRS_HIFREQ_REG_INC (CMPRS_HIFREQ_REG_INC),
.CMPRS_MASK (CMPRS_MASK),
.CMPRS_CONTROL_REG (CMPRS_CONTROL_REG),
.CMPRS_STATUS_CNTRL (CMPRS_STATUS_CNTRL),
.CMPRS_FORMAT (CMPRS_FORMAT),
.CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION),
.CMPRS_CORING_MODE (CMPRS_CORING_MODE),
.CMPRS_TABLES (CMPRS_TABLES),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.LAST_FRAME_BITS (LAST_FRAME_BITS),
.CMPRS_CBIT_RUN (CMPRS_CBIT_RUN),
.CMPRS_CBIT_RUN_BITS (CMPRS_CBIT_RUN_BITS),
.CMPRS_CBIT_QBANK (CMPRS_CBIT_QBANK),
.CMPRS_CBIT_QBANK_BITS (CMPRS_CBIT_QBANK_BITS),
.CMPRS_CBIT_DCSUB (CMPRS_CBIT_DCSUB),
.CMPRS_CBIT_DCSUB_BITS (CMPRS_CBIT_DCSUB_BITS),
.CMPRS_CBIT_CMODE (CMPRS_CBIT_CMODE),
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
.CMPRS_CBIT_FOCUS_BITS (CMPRS_CBIT_FOCUS_BITS),
.CMPRS_CBIT_RUN_RST (CMPRS_CBIT_RUN_RST),
.CMPRS_CBIT_RUN_STANDALONE (CMPRS_CBIT_RUN_STANDALONE),
.CMPRS_CBIT_RUN_ENABLE (CMPRS_CBIT_RUN_ENABLE),
.CMPRS_CBIT_CMODE_JPEG18 (CMPRS_CBIT_CMODE_JPEG18),
.CMPRS_CBIT_CMODE_MONO6 (CMPRS_CBIT_CMODE_MONO6),
.CMPRS_CBIT_CMODE_JP46 (CMPRS_CBIT_CMODE_JP46),
.CMPRS_CBIT_CMODE_JP46DC (CMPRS_CBIT_CMODE_JP46DC),
.CMPRS_CBIT_CMODE_JPEG20 (CMPRS_CBIT_CMODE_JPEG20),
.CMPRS_CBIT_CMODE_JP4 (CMPRS_CBIT_CMODE_JP4),
.CMPRS_CBIT_CMODE_JP4DC (CMPRS_CBIT_CMODE_JP4DC),
.CMPRS_CBIT_CMODE_JP4DIFF (CMPRS_CBIT_CMODE_JP4DIFF),
.CMPRS_CBIT_CMODE_JP4DIFFHDR (CMPRS_CBIT_CMODE_JP4DIFFHDR),
.CMPRS_CBIT_CMODE_JP4DIFFDIV2 (CMPRS_CBIT_CMODE_JP4DIFFDIV2),
.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2),
.CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1),
.CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4),
.CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE),
.CMPRS_COLOR18 (CMPRS_COLOR18),
.CMPRS_COLOR20 (CMPRS_COLOR20),
.CMPRS_MONO16 (CMPRS_MONO16),
.CMPRS_JP4 (CMPRS_JP4),
.CMPRS_JP4DIFF (CMPRS_JP4DIFF),
.CMPRS_MONO8 (CMPRS_MONO8),
.CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1),
.CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS),
.CMPRS_FRMT_MBRM1 (CMPRS_FRMT_MBRM1),
.CMPRS_FRMT_MBRM1_BITS (CMPRS_FRMT_MBRM1_BITS),
.CMPRS_FRMT_LMARG (CMPRS_FRMT_LMARG),
.CMPRS_FRMT_LMARG_BITS (CMPRS_FRMT_LMARG_BITS),
.CMPRS_CSAT_CB (CMPRS_CSAT_CB),
.CMPRS_CSAT_CB_BITS (CMPRS_CSAT_CB_BITS),
.CMPRS_CSAT_CR (CMPRS_CSAT_CR),
.CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS),
.CMPRS_CORING_BITS (CMPRS_CORING_BITS),
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT)
) jp_channel_i (
.rst (rst), // input
.xclk (xclk), // input
.xclk2x (xclk2x), // input
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[8 * i +: 8]), // output[7:0]
.status_rq (status_rq_mux[i]), // output
.status_start (status_start_mux[i]), // input
.xfer_reset_page_rd (xfer_reset_page_rd[i]), // input
.buf_wpage_nxt (buf_wpage_nxt[i]), // input
.buf_we (buf_we[i]), // input
.buf_din (buf_din[64 * i +: 64]), // input[63:0]
.page_ready_chn (page_ready[i]), // input
.next_page_chn (next_page[i]), // output
.dccout (1'b0), // input
.hfc_sel (3'b0), // input[2:0]
.statistics_dv (), // output
.statistics_do (), // output[15:0]
.ts_pre_stb (ts_pre_stb[i]), // input
.ts_data (ts_data[8*i +: 8]), // input[7:0]
.eof_written_mclk (eof_written_mclk[i]), // output
.stuffer_done_mclk (stuffer_done_mclk[i]), // output
.vsync_late (vsync_late[i]), // input
.frame_start_dst (frame_start_dst[i]), // output
.line_unfinished_src (line_unfinished_src[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_src (frame_number_src[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_src (frame_done_src[i]), // input
.line_unfinished_dst (line_unfinished_dst[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_dst (frame_done_dst[i]), // input
.suspend (suspend[i]), // output
.hclk (hclk), // input
.fifo_rst (fifo_rst[i]), // input
.fifo_ren (fifo_ren[i]), // input
.fifo_rdata (fifo_rdata[64 * i +: 64]), // output[63:0]
.fifo_eof (fifo_eof[i]), // output
.eof_written (eof_written[i]), // input
.fifo_flush (fifo_flush[i]), // output
.fifo_count (fifo_count[8* i +: 8]) // output[7:0]
);
end
endgenerate
generate
if (CMPRS_NUM_AFI_CHN > 1) begin
cmprs_afi_mux #(
.CMPRS_AFIMUX_ADDR (CMPRS_GROUP_ADDR + CMPRS_AFIMUX_RADDR0),
.CMPRS_AFIMUX_MASK (CMPRS_AFIMUX_MASK),
.CMPRS_AFIMUX_EN (CMPRS_AFIMUX_EN),
.CMPRS_AFIMUX_RST (CMPRS_AFIMUX_RST),
.CMPRS_AFIMUX_MODE (CMPRS_AFIMUX_MODE),
.CMPRS_AFIMUX_STATUS_CNTRL (CMPRS_AFIMUX_STATUS_CNTRL),
.CMPRS_AFIMUX_SA_LEN (CMPRS_AFIMUX_SA_LEN),
.CMPRS_AFIMUX_STATUS_REG_ADDR (CMPRS_AFIMUX_REG_ADDR0), //***********
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi0_mux_i (
.rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[32 +: 8]), // output[7:0]
.status_rq (status_rq_mux[4]), // output
.status_start (status_start_mux[4]), // input
.fifo_rst0 (fifo_rst[0]), // output
.fifo_ren0 (fifo_ren[0]), // output
.fifo_rdata0 (fifo_rdata[0 +: 64]), // input[63:0]
.eof_written0 (eof_written[0]), // output //?
.fifo_flush0 (fifo_flush[0]), // input
.fifo_count0 (fifo_count[0 +: 8]), // input[7:0]
.fifo_rst1 (fifo_rst[1]), // output
.fifo_ren1 (fifo_ren[1]), // output
.fifo_rdata1 (fifo_rdata[64 +: 64]), // input[63:0]
.eof_written1 (eof_written[1]), // output
.fifo_flush1 (fifo_flush[1]), // input
.fifo_count1 (fifo_count[8 +: 8]), // input[7:0]
.fifo_rst2 (), // output
.fifo_ren2 (), // output
.fifo_rdata2 (0), // input[63:0]
.eof_written2 (), // output
.fifo_flush2 (0), // input
.fifo_count2 (0), // input[7:0]
.fifo_rst3 (), // output
.fifo_ren3 (), // output
.fifo_rdata3 (0), // input[63:0]
.eof_written3 (), // output
.fifo_flush3 (0), // input
.fifo_count3 (0), // input[7:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
.afi_awid (afi0_awid), // output[5:0]
.afi_awlock (afi0_awlock), // output[1:0]
.afi_awcache (afi0_awcache), // output[3:0]
.afi_awprot (afi0_awprot), // output[2:0]
.afi_awlen (afi0_awlen), // output[3:0]
.afi_awsize (afi0_awsize), // output[2:0]
.afi_awburst (afi0_awburst), // output[1:0]
.afi_awqos (afi0_awqos), // output[3:0]
.afi_wdata (afi0_wdata), // output[63:0]
.afi_wvalid (afi0_wvalid), // output
.afi_wready (afi0_wready), // input
.afi_wid (afi0_wid), // output[5:0]
.afi_wlast (afi0_wlast), // output
.afi_wstrb (afi0_wstrb), // output[7:0]
.afi_bvalid (afi0_bvalid), // input
.afi_bready (afi0_bready), // output
.afi_bid (afi0_bid), // input[5:0]
.afi_bresp (afi0_bresp), // input[1:0]
.afi_wcount (afi0_wcount), // input[7:0]
.afi_wacount (afi0_wacount), // input[5:0]
.afi_wrissuecap1en(afi0_wrissuecap1en) // output
);
cmprs_afi_mux #(
.CMPRS_AFIMUX_ADDR (CMPRS_GROUP_ADDR + CMPRS_AFIMUX_RADDR1),
.CMPRS_AFIMUX_MASK (CMPRS_AFIMUX_MASK),
.CMPRS_AFIMUX_EN (CMPRS_AFIMUX_EN),
.CMPRS_AFIMUX_RST (CMPRS_AFIMUX_RST),
.CMPRS_AFIMUX_MODE (CMPRS_AFIMUX_MODE),
.CMPRS_AFIMUX_STATUS_CNTRL (CMPRS_AFIMUX_STATUS_CNTRL),
.CMPRS_AFIMUX_SA_LEN (CMPRS_AFIMUX_SA_LEN),
.CMPRS_AFIMUX_STATUS_REG_ADDR (CMPRS_AFIMUX_REG_ADDR1),
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi1_mux_i (
.rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[40 +: 8]), // output[7:0]
.status_rq (status_rq_mux[5]), // output
.status_start (status_start_mux[5]), // input
.fifo_rst0 (fifo_rst[2]), // output
.fifo_ren0 (fifo_ren[2]), // output
.fifo_rdata0 (fifo_rdata[128 +: 64]), // input[63:0]
.eof_written0 (eof_written[2]), // output
.fifo_flush0 (fifo_flush[2]), // input
.fifo_count0 (fifo_count[16 +: 8]), // input[7:0]
.fifo_rst1 (fifo_rst[3]), // output
.fifo_ren1 (fifo_ren[3]), // output
.fifo_rdata1 (fifo_rdata[192 +: 64]), // input[63:0]
.eof_written1 (eof_written[3]), // output
.fifo_flush1 (fifo_flush[3]), // input
.fifo_count1 (fifo_count[24 +: 8]), // input[7:0]
.fifo_rst2 (), // output
.fifo_ren2 (), // output
.fifo_rdata2 (0), // input[63:0]
.eof_written2 (), // output
.fifo_flush2 (0), // input
.fifo_count2 (0), // input[7:0]
.fifo_rst3 (), // output
.fifo_ren3 (), // output
.fifo_rdata3 (0), // input[63:0]
.eof_written3 (), // output
.fifo_flush3 (0), // input
.fifo_count3 (0), // input[7:0]
.afi_awaddr (afi1_awaddr), // output[31:0]
.afi_awvalid (afi1_awvalid), // output
.afi_awready (afi1_awready), // input
.afi_awid (afi1_awid), // output[5:0]
.afi_awlock (afi1_awlock), // output[1:0]
.afi_awcache (afi1_awcache), // output[3:0]
.afi_awprot (afi1_awprot), // output[2:0]
.afi_awlen (afi1_awlen), // output[3:0]
.afi_awsize (afi1_awsize), // output[2:0]
.afi_awburst (afi1_awburst), // output[1:0]
.afi_awqos (afi1_awqos), // output[3:0]
.afi_wdata (afi1_wdata), // output[63:0]
.afi_wvalid (afi1_wvalid), // output
.afi_wready (afi1_wready), // input
.afi_wid (afi1_wid), // output[5:0]
.afi_wlast (afi1_wlast), // output
.afi_wstrb (afi1_wstrb), // output[7:0]
.afi_bvalid (afi1_bvalid), // input
.afi_bready (afi1_bready), // output
.afi_bid (afi1_bid), // input[5:0]
.afi_bresp (afi1_bresp), // input[1:0]
.afi_wcount (afi1_wcount), // input[7:0]
.afi_wacount (afi1_wacount), // input[5:0]
.afi_wrissuecap1en(afi1_wrissuecap1en) // output
);
end else begin
cmprs_afi_mux #(
.CMPRS_AFIMUX_ADDR (CMPRS_GROUP_ADDR + CMPRS_AFIMUX_RADDR0),
.CMPRS_AFIMUX_MASK (CMPRS_AFIMUX_MASK),
.CMPRS_AFIMUX_EN (CMPRS_AFIMUX_EN),
.CMPRS_AFIMUX_RST (CMPRS_AFIMUX_RST),
.CMPRS_AFIMUX_MODE (CMPRS_AFIMUX_MODE),
.CMPRS_AFIMUX_STATUS_CNTRL (CMPRS_AFIMUX_STATUS_CNTRL),
.CMPRS_AFIMUX_SA_LEN (CMPRS_AFIMUX_SA_LEN),
.CMPRS_AFIMUX_STATUS_REG_ADDR (CMPRS_AFIMUX_REG_ADDR0),
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
) cmprs_afi0_mux_i (
.rst (rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (status_ad_mux[32 +: 8]), // output[7:0]
.status_rq (status_rq_mux[4]), // output
.status_start (status_start_mux[4]), // input
.fifo_rst0 (fifo_rst[0]), // output
.fifo_ren0 (fifo_ren[0]), // output
.fifo_rdata0 (fifo_rdata[0 +: 64]), // input[63:0]
.eof_written0 (eof_written[0]), // output
.fifo_flush0 (fifo_flush[0]), // input
.fifo_count0 (fifo_count[0 +: 8]), // input[7:0]
.fifo_rst1 (fifo_rst[1]), // output
.fifo_ren1 (fifo_ren[1]), // output
.fifo_rdata1 (fifo_rdata[64 +: 64]), // input[63:0]
.eof_written1 (eof_written[1]), // output
.fifo_flush1 (fifo_flush[1]), // input
.fifo_count1 (fifo_count[8 +: 8]), // input[7:0]
.fifo_rst2 (fifo_rst[2]), // output
.fifo_ren2 (fifo_ren[2]), // output
.fifo_rdata2 (fifo_rdata[128 +: 64]), // input[63:0]
.eof_written2 (eof_written[2]), // output
.fifo_flush2 (fifo_flush[2]), // input
.fifo_count2 (fifo_count[16 +: 8]), // input[7:0]
.fifo_rst3 (fifo_rst[3]), // output
.fifo_ren3 (fifo_ren[3]), // output
.fifo_rdata3 (fifo_rdata[192 +: 64]), // input[63:0]
.eof_written3 (eof_written[3]), // output
.fifo_flush3 (fifo_flush[3]), // input
.fifo_count3 (fifo_count[24 +: 8]), // input[7:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
.afi_awid (afi0_awid), // output[5:0]
.afi_awlock (afi0_awlock), // output[1:0]
.afi_awcache (afi0_awcache), // output[3:0]
.afi_awprot (afi0_awprot), // output[2:0]
.afi_awlen (afi0_awlen), // output[3:0]
.afi_awsize (afi0_awsize), // output[2:0]
.afi_awburst (afi0_awburst), // output[1:0]
.afi_awqos (afi0_awqos), // output[3:0]
.afi_wdata (afi0_wdata), // output[63:0]
.afi_wvalid (afi0_wvalid), // output
.afi_wready (afi0_wready), // input
.afi_wid (afi0_wid), // output[5:0]
.afi_wlast (afi0_wlast), // output
.afi_wstrb (afi0_wstrb), // output[7:0]
.afi_bvalid (afi0_bvalid), // input
.afi_bready (afi0_bready), // output
.afi_bid (afi0_bid), // input[5:0]
.afi_bresp (afi0_bresp), // input[1:0]
.afi_wcount (afi0_wcount), // input[7:0]
.afi_wacount (afi0_wacount), // input[5:0]
.afi_wrissuecap1en(afi0_wrissuecap1en) // output
);
assign afi1_awaddr = 0;
assign afi1_awvalid = 0;
assign afi1_awid = 0;
assign afi1_awlock = 0;
assign afi1_awcache = 0;
assign afi1_awprot = 0;
assign afi1_awlen = 0;
assign afi1_awsize = 0;
assign afi1_awburst = 0;
assign afi1_awqos = 0;
assign afi1_wdata = 0;
assign afi1_wvalid = 0;
assign afi1_wid = 0;
assign afi1_wlast = 0;
assign afi1_wstrb = 0;
assign afi1_bready = 0;
assign afi1_wrissuecap1en = 0;
end
endgenerate
endmodule
compressor_jp/jp_channel.v
View file @ bdfcabf1
...@@ -21,7 +21,13 @@ ...@@ -21,7 +21,13 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module jp_channel#( module jp_channel#(
parameter CMPRS_ADDR= 'h120, //TODO: assign valid address parameter CMPRS_NUMBER = 0,
parameter CMPRS_GROUP_ADDR = 'h600,
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_STATUS_REG_BASE= 'h10,
parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_STATUS_REG_INC= 1,
parameter CMPRS_HIFREQ_REG_INC= 1,
parameter CMPRS_MASK= 'h7f8, parameter CMPRS_MASK= 'h7f8,
parameter CMPRS_CONTROL_REG= 0, parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1, parameter CMPRS_STATUS_CNTRL= 1,
...@@ -29,7 +35,6 @@ module jp_channel#( ...@@ -29,7 +35,6 @@ module jp_channel#(
parameter CMPRS_COLOR_SATURATION= 3, parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4, parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_TABLES= 6, // 6..7 parameter CMPRS_TABLES= 6, // 6..7
parameter CMPRS_STATUS_REG_ADDR= 'h10, //TODO: assign valid address
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over) parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
...@@ -105,10 +110,15 @@ module jp_channel#( ...@@ -105,10 +110,15 @@ module jp_channel#(
// Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one // Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one
input xfer_reset_page_rd, // from mcntrl_tiled_rw ( input xfer_reset_page_rd, // from mcntrl_tiled_rw (
output [11:0] buf_ra,
output buf_ren, input buf_wpage_nxt, // advance to next page memory interface writes to
output buf_regen, input buf_we, // @!mclk write buffer from memory, increment write
input [ 7:0] buf_di, input [63:0] buf_din, // data out
// output [11:0] buf_ra,
// output buf_ren,
// output buf_regen,
// input [ 7:0] buf_di,
input page_ready_chn, // single mclk (posedge) input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
...@@ -122,11 +132,10 @@ module jp_channel#( ...@@ -122,11 +132,10 @@ module jp_channel#(
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0) input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
/// output [23:0] imgptr, - removed - use AFI channel MUX
output eof_written_mclk, output eof_written_mclk,
output stuffer_done_mclk, output stuffer_done_mclk,
output [31:0] hifreq, // accumulated high frequency components in a frame sub-window // output [31:0] hifreq, // accumulated high frequency components in a frame sub-window
input vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active input vsync_late, // delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands // source channel should already start, some delay give time for sequencer commands
// that should arrive before it // that should arrive before it
...@@ -155,6 +164,11 @@ module jp_channel#( ...@@ -155,6 +164,11 @@ module jp_channel#(
output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read) output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO output [7:0] fifo_count // number of 32-byte chunks in FIFO
); );
localparam CMPRS_ADDR = CMPRS_GROUP_ADDR + CMPRS_NUMBER * CMPRS_BASE_INC;
localparam CMPRS_STATUS_REG_ADDR = CMPRS_STATUS_REG_BASE + CMPRS_NUMBER * CMPRS_STATUS_REG_INC;
localparam CMPRS_HIFREQ_REG_ADDR = CMPRS_HIFREQ_REG_BASE + CMPRS_NUMBER * CMPRS_HIFREQ_REG_INC;
wire [31:0] hifreq; // accumulated high frequency components in a frame sub-window was output, now - with status
// Control signals to be defined // Control signals to be defined
wire frame_en; // if 0 - will reset logic immediately (but not page number) wire frame_en; // if 0 - will reset logic immediately (but not page number)
wire stuffer_en; // extended enable to allow stuffer to gracefully finish wire stuffer_en; // extended enable to allow stuffer to gracefully finish
...@@ -204,8 +218,8 @@ module jp_channel#( ...@@ -204,8 +218,8 @@ module jp_channel#(
// wire [ 7:0] buf_di; // data from the buffer // wire [ 7:0] buf_di; // data from the buffer
// wire [11:0] buf_ra; // buffer read address (2 MSB - page number) // wire [11:0] buf_ra; // buffer read address (2 MSB - page number)
wire [ 1:0] buf_rd; // buf {regen, re} wire [ 1:0] buf_rd; // buf {regen, re}
wire [ 7:0] buf_pxd; // 8-bit pixel data from the memory buffer
wire [11:0] buf_ra; // Memory buffer read adderss
// signals connecting modules: chn_rd_buf_i and ???: // signals connecting modules: chn_rd_buf_i and ???:
wire [ 7:0] mb_data_out; // Macroblock data out in scanline order wire [ 7:0] mb_data_out; // Macroblock data out in scanline order
wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid
...@@ -306,28 +320,8 @@ module jp_channel#( ...@@ -306,28 +320,8 @@ module jp_channel#(
assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE); assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE);
assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES); assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);
assign buf_ren = buf_rd[0]; // assign buf_ren = buf_rd[0];
assign buf_regen = buf_rd[1]; // assign buf_regen = buf_rd[1];
/*
// Port buffer - TODO: Move to memory controller
mcntrl_buf_rd #(
.LOG2WIDTH_RD(3) // 64 bit external interface
) chn_rd_buf_i (
.ext_clk (xclk), // input
.ext_raddr (buf_ra), // input[11:0]
.ext_rd (buf_rd[0]), // input
.ext_regen (buf_rd[1]), // input
.ext_data_out (buf_di), // output[7:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr), // input
.data_in (buf_wdata) // input[63:0]
);
*/
cmd_deser #( cmd_deser #(
.ADDR (CMPRS_ADDR), .ADDR (CMPRS_ADDR),
...@@ -355,19 +349,38 @@ module jp_channel#( ...@@ -355,19 +349,38 @@ module jp_channel#(
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR), .STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR),
.PAYLOAD_BITS (3) .PAYLOAD_BITS (3),
.EXTRA_WORDS (1),
.EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR)
) status_generate_i ( ) status_generate_i (
.rst (rst), // input .rst (rst), // input
.clk (mclk), // input .clk (mclk), // input
.we (set_status_w), // input .we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0] .wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[2:0] .status ({hifreq,status_data}), // input[2:0]
.ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0]
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
); );
//hifreq
// Port buffer - TODO: Move to memory controller
mcntrl_buf_rd #(
.LOG2WIDTH_RD(3) // 64 bit external interface
) chn_rd_buf_i (
.ext_clk (xclk), // input
.ext_raddr (buf_ra), // input[11:0]
.ext_rd (buf_rd[0]), // input
.ext_regen (buf_rd[1]), // input
.ext_data_out (buf_pxd), // output[7:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_we), // input
.data_in (buf_din) // input[63:0]
);
cmprs_cmd_decode #( cmprs_cmd_decode #(
.CMPRS_CBIT_RUN (CMPRS_CBIT_RUN), .CMPRS_CBIT_RUN (CMPRS_CBIT_RUN),
.CMPRS_CBIT_RUN_BITS (CMPRS_CBIT_RUN_BITS), .CMPRS_CBIT_RUN_BITS (CMPRS_CBIT_RUN_BITS),
...@@ -549,7 +562,7 @@ module jp_channel#( ...@@ -549,7 +562,7 @@ module jp_channel#(
) cmprs_pixel_buf_iface_i ( ) cmprs_pixel_buf_iface_i (
.xclk (xclk), // input .xclk (xclk), // input
.frame_en (frame_en), // input .frame_en (frame_en), // input
.buf_di (buf_di), // input[7:0] .buf_di (buf_pxd), // input[7:0]
.buf_ra (buf_ra), // output[11:0] .buf_ra (buf_ra), // output[11:0]
.buf_rd (buf_rd), // output[1:0] .buf_rd (buf_rd), // output[1:0]
.converter_type (converter_type), // input[2:0] .converter_type (converter_type), // input[2:0]
......
memctrl/mcntrl_buf_rd.v
View file @ bdfcabf1
...@@ -32,7 +32,7 @@ module mcntrl_buf_rd #( ...@@ -32,7 +32,7 @@ module mcntrl_buf_rd #(
input wclk, // !mclk (inverted) input wclk, // !mclk (inverted)
input [1:0] wpage_in, // will register to wclk, input OK with mclk input [1:0] wpage_in, // will register to wclk, input OK with mclk
input wpage_set, // set internal read page to rpage_in input wpage_set, // set internal write page to wpage_in
input page_next, // advance to next page (and reset lower bits to 0) input page_next, // advance to next page (and reset lower bits to 0)
output [1:0] page, // current inernal page output [1:0] page, // current inernal page
input we, // write port enable (also increment write buffer address) input we, // write port enable (also increment write buffer address)
......
sensor/sens_sync.v
View file @ bdfcabf1
/******************************************************************************* /*******************************************************************************
* Module: sens_sync * Module: sens_sync
* Date:2015-07-13 * Date:2015-07-13
* Author: andrey * Author: Andrey Filippov
* Description: Handle linescan mode, sensor trigger and late frame sync * Description: Handle linescan mode, sensor trigger and late frame sync
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
sensor/sensor_membuf.v
View file @ bdfcabf1
/******************************************************************************* /*******************************************************************************
* Module: sensor_membuf * Module: sensor_membuf
* Date:2015-07-12 * Date:2015-07-12
* Author: andrey * Author: Andrey Filippov
* Description: Memory buffer for one sensor channel * Description: Memory buffer for one sensor channel
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
sensor/sensors393.v
View file @ bdfcabf1
/******************************************************************************* /*******************************************************************************
* Module: sensors393 * Module: sensors393
* Date:2015-07-12 * Date:2015-07-12
* Author: andrey * Author: Andrey Filippov
* Description: 4-channel sensor subsystem * Description: 4-channel sensor subsystem
* Uniform, assuming the same sensors/multiplexers, common pixel clock * Uniform, assuming the same sensors/multiplexers, common pixel clock
* *
...@@ -196,7 +196,7 @@ module sensors393 #( ...@@ -196,7 +196,7 @@ module sensors393 #(
inout sns1_scl, inout sns1_scl,
inout sns1_sda, inout sns1_sda,
inout sns1_ctl, inout sns1_ctl,
inout sns1_pg, //S uppressThisWarning VEditor : VDT bug? - assigned used in generate block only inout sns1_pg,
inout [7:0] sns2_dp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only inout [7:0] sns2_dp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [7:0] sns2_dn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only inout [7:0] sns2_dn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
...@@ -325,7 +325,7 @@ module sensors393 #( ...@@ -325,7 +325,7 @@ module sensors393 #(
generate generate
genvar i; genvar i;
for (i=0; i < 4; i=i+1) begin: sencor_channel_block for (i=0; i < 4; i=i+1) begin: sensor_channel_block
sensor_channel #( sensor_channel #(
.SENSOR_NUMBER (i), .SENSOR_NUMBER (i),
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR), .SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
......
x393.v
View file @ bdfcabf1
...@@ -25,6 +25,44 @@ ...@@ -25,6 +25,44 @@
module x393 #( module x393 #(
`include "includes/x393_parameters.vh" `include "includes/x393_parameters.vh"
)( )(
// Sensors interface: I/O pads, pin names match circuit diagram (each sensor)
inout [7:0] sns1_dp,
inout [7:0] sns1_dn,
inout sns1_clkp,
inout sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
inout sns1_pg,
inout [7:0] sns2_dp,
inout [7:0] sns2_dn,
inout sns2_clkp,
inout sns2_clkn,
inout sns2_scl,
inout sns2_sda,
inout sns2_ctl,
inout sns2_pg,
inout [7:0] sns3_dp,
inout [7:0] sns3_dn,
inout sns3_clkp,
inout sns3_clkn,
inout sns3_scl,
inout sns3_sda,
inout sns3_ctl,
inout sns3_pg,
inout [7:0] sns4_dp,
inout [7:0] sns4_dn,
inout sns4_clkp,
inout sns4_clkn,
inout sns4_scl,
inout sns4_sda,
inout sns4_ctl,
inout sns4_pg,
// DDR3 interface // DDR3 interface
output SDRST, // DDR3 reset (active low) output SDRST, // DDR3 reset (active low)
output SDCLK, // DDR3 clock differential output, positive output SDCLK, // DDR3 clock differential output, positive
...@@ -64,29 +102,29 @@ module x393 #( ...@@ -64,29 +102,29 @@ module x393 #(
//(* dont_touch = "true" *) //(* dont_touch = "true" *)
wire axi_rst; // reset, active high wire axi_rst; // reset, active high
// AXI Write Address // AXI Write Address
wire [31:0] axi_awaddr; // AWADDR[31:0], input wire [31:0] maxi0_awaddr; // AWADDR[31:0], input
wire axi_awvalid; // AWVALID, input wire maxi0_awvalid; // AWVALID, input
wire axi_awready; // AWREADY, output wire maxi0_awready; // AWREADY, output
wire [11:0] axi_awid; // AWID[11:0], input wire [11:0] maxi0_awid; // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input // input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input // input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input // input [ 2:0] awprot, // AWPROT[2:0], input
wire [ 3:0] axi_awlen; // AWLEN[3:0], input wire [ 3:0] maxi0_awlen; // AWLEN[3:0], input
wire [ 1:0] axi_awsize; // AWSIZE[1:0], input wire [ 1:0] maxi0_awsize; // AWSIZE[1:0], input
wire [ 1:0] axi_awburst; // AWBURST[1:0], input wire [ 1:0] maxi0_awburst; // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input // input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data // AXI PS Master GP0: Write Data
wire [31:0] axi_wdata; // WDATA[31:0], input wire [31:0] maxi0_wdata; // WDATA[31:0], input
wire axi_wvalid; // WVALID, input wire maxi0_wvalid; // WVALID, input
wire axi_wready; // WREADY, output wire maxi0_wready; // WREADY, output
wire [11:0] axi_wid; // WID[11:0], input wire [11:0] maxi0_wid; // WID[11:0], input
wire axi_wlast; // WLAST, input wire maxi0_wlast; // WLAST, input
wire [ 3:0] axi_wstb; // WSTRB[3:0], input wire [ 3:0] maxi0_wstb; // WSTRB[3:0], input
// AXI PS Master GP0: Write Responce // AXI PS Master GP0: Write Responce
wire axi_bvalid; // BVALID, output wire maxi0_bvalid; // BVALID, output
wire axi_bready; // BREADY, input wire maxi0_bready; // BREADY, input
wire [11:0] axi_bid; // BID[11:0], output wire [11:0] maxi0_bid; // BID[11:0], output
wire [ 1:0] axi_bresp; // BRESP[1:0], output wire [ 1:0] maxi0_bresp; // BRESP[1:0], output
// BRAM (and other write modules) interface from AXI write // BRAM (and other write modules) interface from AXI write
wire [AXI_WR_ADDR_BITS-1:0] axiwr_pre_awaddr; // same as awaddr_out, early address to decode and return dev_ready wire [AXI_WR_ADDR_BITS-1:0] axiwr_pre_awaddr; // same as awaddr_out, early address to decode and return dev_ready
...@@ -100,24 +138,24 @@ module x393 #( ...@@ -100,24 +138,24 @@ module x393 #(
wire [31:0] axiwr_wdata; wire [31:0] axiwr_wdata;
// AXI Read Address // AXI Read Address
wire [31:0] axi_araddr; // ARADDR[31:0], input wire [31:0] maxi0_araddr; // ARADDR[31:0], input
wire axi_arvalid; // ARVALID, input wire maxi0_arvalid; // ARVALID, input
wire axi_arready; // ARREADY, output wire maxi0_arready; // ARREADY, output
wire [11:0] axi_arid; // ARID[11:0], input wire [11:0] maxi0_arid; // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input // input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input // input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input // input [ 2:0] arprot, // ARPROT[2:0], input
wire [ 3:0] axi_arlen; // ARLEN[3:0], input wire [ 3:0] maxi0_arlen; // ARLEN[3:0], input
wire [ 1:0] axi_arsize; // ARSIZE[1:0], input wire [ 1:0] maxi0_arsize; // ARSIZE[1:0], input
wire [ 1:0] axi_arburst; // ARBURST[1:0], input wire [ 1:0] maxi0_arburst; // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input // input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data // AXI Read Data
wire [31:0] axi_rdata; // RDATA[31:0], output wire [31:0] maxi0_rdata; // RDATA[31:0], output
wire axi_rvalid; // RVALID, output wire maxi0_rvalid; // RVALID, output
wire axi_rready; // RREADY, input wire maxi0_rready; // RREADY, input
wire [11:0] axi_rid; // RID[11:0], output wire [11:0] maxi0_rid; // RID[11:0], output
wire axi_rlast; // RLAST, output wire maxi0_rlast; // RLAST, output
wire [ 1:0] axi_rresp; wire [ 1:0] maxi0_rresp;
// External memory synchronization // External memory synchronization
wire [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr; // same as awaddr_out, early address to decode and return dev_ready wire [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr; // same as awaddr_out, early address to decode and return dev_ready
...@@ -306,6 +344,44 @@ module x393 #( ...@@ -306,6 +344,44 @@ module x393 #(
//MEMCLK //MEMCLK
wire [63:0] gpio_in; wire [63:0] gpio_in;
// signals for sensor393 (in/outs as sseen for the sensor393)
wire rpage_set0; // (), // input
wire rpage_next0; // (), // input
wire buf_rd0; // (), // input
wire [63:0] buf_dout0; // (), // output[63:0]
wire rpage_set1; // (), // input
wire rpage_next1; // (), // input
wire buf_rd1; // (), // input
wire [63:0] buf_dout1; // (), // output[63:0]
wire rpage_set2; // (), // input
wire rpage_next2; // (), // input
wire buf_rd2; // (), // input
wire [63:0] buf_dout2; // (), // output[63:0]
wire rpage_set3; // (), // input
wire rpage_next3; // (), // input
wire buf_rd3; // (), // input
wire [63:0] buf_dout3; // (), // output[63:0]
wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0]
wire [3:0] sof_out_pclk; // (), // output[3:0]
wire [3:0] eof_out_pclk; // (), // output[3:0]
wire [3:0] sof_out_mclk; // (), // output[3:0]
wire [3:0] sof_late_mclk; // (), // output[3:0]
wire [NUM_FRAME_BITS - 1:0] frame_num0; // (), // input[3:0]
wire [NUM_FRAME_BITS - 1:0] frame_num1; // (), // input[3:0]
wire [NUM_FRAME_BITS - 1:0] frame_num2; // (), // input[3:0]
wire [NUM_FRAME_BITS - 1:0] frame_num3; // (), // input[3:0]
assign gpio_in= {48'h0,frst,tmp_debug}; assign gpio_in= {48'h0,frst,tmp_debug};
...@@ -908,7 +984,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -908,7 +984,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.NDQSU (NDQSU), // inout .NDQSU (NDQSU), // inout
.tmp_debug (tmp_debug) // output[11:0] .tmp_debug (tmp_debug) // output[11:0]
); );
// AFI0 (AXI_HP0) signals
wire [31:0] afi0_awaddr; // output[31:0] wire [31:0] afi0_awaddr; // output[31:0]
wire afi0_awvalid; // output wire afi0_awvalid; // output
wire afi0_awready; // input wire afi0_awready; // input
...@@ -1042,6 +1118,31 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1042,6 +1118,31 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.afi_racount (afi0_racount), // input[2:0] .afi_racount (afi0_racount), // input[2:0]
.afi_rdissuecap1en (afi0_rdissuecap1en) // output .afi_rdissuecap1en (afi0_rdissuecap1en) // output
); );
// SAXIGP0 signals
wire saxi0_aclk = hclk; // 150KHz
wire [31:0] saxi0_awaddr;
wire saxi0_awvalid;
wire saxi0_awready;
wire [ 5:0] saxi0_awid;
wire [ 1:0] saxi0_awlock;
wire [ 3:0] saxi0_awcache;
wire [ 2:0] saxi0_awprot;
wire [ 3:0] saxi0_awlen;
wire [ 1:0] saxi0_awsize;
wire [ 1:0] saxi0_awburst;
wire [ 3:0] saxi0_awqos;
wire [31:0] saxi0_wdata;
wire saxi0_wvalid;
wire saxi0_wready;
wire [ 5:0] saxi0_wid;
wire saxi0_wlast;
wire [ 3:0] saxi0_wstrb;
wire saxi0_bvalid;
wire saxi0_bready;
wire [ 5:0] saxi0_bid;
wire [ 1:0] saxi0_bresp;
sensors393 #( sensors393 #(
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR), .SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
...@@ -1163,86 +1264,97 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1163,86 +1264,97 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.status_ad (status_sensor_ad), // output[7:0] .status_ad (status_sensor_ad), // output[7:0]
.status_rq (status_sensor_rq), // output .status_rq (status_sensor_rq), // output
.status_start (status_sensor_start), // input .status_start (status_sensor_start), // input
.sns1_dp(), // inout[7:0] .sns1_dp (sns1_dp), // inout[7:0]
.sns1_dn(), // inout[7:0] .sns1_dn (sns1_dn), // inout[7:0]
.sns1_clkp(), // inout .sns1_clkp (sns1_clkp), // inout
.sns1_clkn(), // inout .sns1_clkn (sns1_clkn), // inout
.sns1_scl(), // inout .sns1_scl (sns1_scl), // inout
.sns1_sda(), // inout .sns1_sda (sns1_sda), // inout
.sns1_ctl(), // inout .sns1_ctl (sns1_ctl), // inout
.sns1_pg(), // inout .sns1_pg (sns1_pg), // inout
.sns2_dp(), // inout[7:0]
.sns2_dn(), // inout[7:0] .sns2_dp (sns2_dp), // inout[7:0]
.sns2_clkp(), // inout .sns2_dn (sns2_dn), // inout[7:0]
.sns2_clkn(), // inout .sns2_clkp (sns2_clkp), // inout
.sns2_scl(), // inout .sns2_clkn (sns2_clkn), // inout
.sns2_sda(), // inout .sns2_scl (sns2_scl), // inout
.sns2_ctl(), // inout .sns2_sda (sns2_sda), // inout
.sns2_pg(), // inout .sns2_ctl (sns2_ctl), // inout
.sns3_dp(), // inout[7:0] .sns2_pg (sns2_pg), // inout
.sns3_dn(), // inout[7:0]
.sns3_clkp(), // inout .sns3_dp (sns3_dp), // inout[7:0]
.sns3_clkn(), // inout .sns3_dn (sns3_dn), // inout[7:0]
.sns3_scl(), // inout .sns3_clkp (sns3_clkp), // inout
.sns3_sda(), // inout .sns3_clkn (sns3_clkn), // inout
.sns3_ctl(), // inout .sns3_scl (sns3_scl), // inout
.sns3_pg(), // inout .sns3_sda (sns3_sda), // inout
.sns4_dp(), // inout[7:0] .sns3_ctl (sns3_ctl), // inout
.sns4_dn(), // inout[7:0] .sns3_pg (sns3_pg), // inout
.sns4_clkp(), // inout
.sns4_clkn(), // inout .sns4_dp (sns4_dp), // inout[7:0]
.sns4_scl(), // inout .sns4_dn (sns4_dn), // inout[7:0]
.sns4_sda(), // inout .sns4_clkp (sns4_clkp), // inout
.sns4_ctl(), // inout .sns4_clkn (sns4_clkn), // inout
.sns4_pg(), // inout .sns4_scl (sns4_scl), // inout
.rpage_set0(), // input .sns4_sda (sns4_sda), // inout
.rpage_next0(), // input .sns4_ctl (sns4_ctl), // inout
.buf_rd0(), // input .sns4_pg (sns4_pg), // inout
.buf_dout0(), // output[63:0]
.rpage_set1(), // input .rpage_set0 (rpage_set0), // input
.rpage_next1(), // input .rpage_next0 (rpage_next0), // input
.buf_rd1(), // input .buf_rd0 (buf_rd0), // input
.buf_dout1(), // output[63:0] .buf_dout0 (buf_dout0), // output[63:0]
.rpage_set2(), // input
.rpage_next2(), // input .rpage_set1 (rpage_set1), // input
.buf_rd2(), // input .rpage_next1 (rpage_next1), // input
.buf_dout2(), // output[63:0] .buf_rd1 (buf_rd1), // input
.rpage_set3(), // input .buf_dout1 (buf_dout1), // output[63:0]
.rpage_next3(), // input
.buf_rd3(), // input .rpage_set2 (rpage_set2), // input
.buf_dout3(), // output[63:0] .rpage_next2 (rpage_next2), // input
.trigger_mode(), // input .buf_rd2 (buf_rd2), // input
.trig_in(), // input[3:0] .buf_dout2 (buf_dout2), // output[63:0]
.sof_out_pclk(), // output[3:0]
.eof_out_pclk(), // output[3:0] .rpage_set3 (rpage_set3), // input
.sof_out_mclk(), // output[3:0] .rpage_next3 (rpage_next3), // input
.sof_late_mclk(), // output[3:0] .buf_rd3 (buf_rd3), // input
.frame_num0(), // input[3:0] .buf_dout3 (buf_dout3), // output[63:0]
.frame_num1(), // input[3:0]
.frame_num2(), // input[3:0] .trigger_mode (trigger_mode), // input
.frame_num3(), // input[3:0] .trig_in (trig_in), // input[3:0]
.aclk(), // input
.saxi_awaddr(), // output[31:0] .sof_out_pclk (sof_out_pclk), // output[3:0]
.saxi_awvalid(), // output .eof_out_pclk (eof_out_pclk), // output[3:0]
.saxi_awready(), // input .sof_out_mclk (sof_out_mclk), // output[3:0]
.saxi_awid(), // output[5:0] .sof_late_mclk (sof_late_mclk), // output[3:0]
.saxi_awlock(), // output[1:0]
.saxi_awcache(), // output[3:0] .frame_num0 (frame_num0), // input[3:0]
.saxi_awprot(), // output[2:0] .frame_num1 (frame_num1), // input[3:0]
.saxi_awlen(), // output[3:0] .frame_num2 (frame_num2), // input[3:0]
.saxi_awsize(), // output[1:0] .frame_num3 (frame_num3), // input[3:0]
.saxi_awburst(), // output[1:0]
.saxi_awqos(), // output[3:0] .aclk (saxi0_aclk), // input
.saxi_wdata(), // output[31:0] .saxi_awaddr (saxi0_awaddr), // output[31:0]
.saxi_wvalid(), // output .saxi_awvalid (saxi0_awvalid), // output
.saxi_wready(), // input .saxi_awready (saxi0_awready), // input
.saxi_wid(), // output[5:0] .saxi_awid (saxi0_awid), // output[5:0]
.saxi_wlast(), // output .saxi_awlock (saxi0_awlock), // output[1:0]
.saxi_wstrb(), // output[3:0] .saxi_awcache (saxi0_awcache), // output[3:0]
.saxi_bvalid(), // input .saxi_awprot (saxi0_awprot), // output[2:0]
.saxi_bready(), // output .saxi_awlen (saxi0_awlen), // output[3:0]
.saxi_bid(), // input[5:0] .saxi_awsize (saxi0_awsize), // output[1:0]
.saxi_bresp() // input[1:0] .saxi_awburst (saxi0_awburst), // output[1:0]
.saxi_awqos (saxi0_awqos), // output[3:0]
.saxi_wdata (saxi0_wdata), // output[31:0]
.saxi_wvalid (saxi0_wvalid), // output
.saxi_wready (saxi0_wready), // input
.saxi_wid (saxi0_wid), // output[5:0]
.saxi_wlast (saxi0_wlast), // output
.saxi_wstrb (saxi0_wstrb), // output[3:0]
.saxi_bvalid (saxi0_bvalid), // input
.saxi_bready (saxi0_bready), // output
.saxi_bid (saxi0_bid), // input[5:0]
.saxi_bresp (saxi0_bresp) // input[1:0]
); );
axibram_write #( axibram_write #(
...@@ -1250,23 +1362,23 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1250,23 +1362,23 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal. ) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input .aclk (axi_aclk), // input
.rst (axi_rst), // input .rst (axi_rst), // input
.awaddr (axi_awaddr[31:0]), // input[31:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_write_i:awaddr[31:16,1:0] to constant 0 .awaddr (maxi0_awaddr[31:0]), // input[31:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_write_i:awaddr[31:16,1:0] to constant 0
.awvalid (axi_awvalid), // input .awvalid (maxi0_awvalid), // input
.awready (axi_awready), // output .awready (maxi0_awready), // output
.awid (axi_awid[11:0]), // input[11:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_write_i:awid[11:2] to constant 0 .awid (maxi0_awid[11:0]), // input[11:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_write_i:awid[11:2] to constant 0
.awlen (axi_awlen[3:0]), // input[3:0] .awlen (maxi0_awlen[3:0]), // input[3:0]
.awsize (axi_awsize[1:0]), // input[1:0] .awsize (maxi0_awsize[1:0]), // input[1:0]
.awburst (axi_awburst[1:0]), // input[1:0] .awburst (maxi0_awburst[1:0]), // input[1:0]
.wdata (axi_wdata[31:0]), // input[31:0] .wdata (maxi0_wdata[31:0]), // input[31:0]
.wvalid (axi_wvalid), // input .wvalid (maxi0_wvalid), // input
.wready (axi_wready), // output .wready (maxi0_wready), // output
.wid (axi_wid[11:0]), // input[11:0] .wid (maxi0_wid[11:0]), // input[11:0]
.wlast (axi_wlast), // input .wlast (maxi0_wlast), // input
.wstb (axi_wstb[3:0]), // input[3:0] .wstb (maxi0_wstb[3:0]), // input[3:0]
.bvalid (axi_bvalid), // output .bvalid (maxi0_bvalid), // output
.bready (axi_bready), // input .bready (maxi0_bready), // input
.bid (axi_bid[11:0]), // output[11:0] .bid (maxi0_bid[11:0]), // output[11:0]
.bresp (axi_bresp[1:0]), // output[1:0] .bresp (maxi0_bresp[1:0]), // output[1:0]
.pre_awaddr (axiwr_pre_awaddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0] .pre_awaddr (axiwr_pre_awaddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.start_burst (axiwr_start_burst), // output .start_burst (axiwr_start_burst), // output
.dev_ready (axiwr_dev_ready), // input .dev_ready (axiwr_dev_ready), // input
...@@ -1304,19 +1416,19 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -1304,19 +1416,19 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
) axibram_read_i ( //SuppressThisWarning ISExst Output port <bram_rclk> of the instance <axibram_read_i> is unconnected or connected to loadless signal. ) axibram_read_i ( //SuppressThisWarning ISExst Output port <bram_rclk> of the instance <axibram_read_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input .aclk (axi_aclk), // input
.rst (axi_rst), // input .rst (axi_rst), // input
.araddr (axi_araddr[31:0]), // input[31:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_read_i:araddr[31:16,1:0] to constant 0 .araddr (maxi0_araddr[31:0]), // input[31:0] // SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_read_i:araddr[31:16,1:0] to constant 0
.arvalid (axi_arvalid), // input .arvalid (maxi0_arvalid), // input
.arready (axi_arready), // output .arready (maxi0_arready), // output
.arid (axi_arid[11:0]), // input[11:0] .arid (maxi0_arid[11:0]), // input[11:0]
.arlen (axi_arlen[3:0]), // input[3:0] .arlen (maxi0_arlen[3:0]), // input[3:0]
.arsize (axi_arsize[1:0]), // input[1:0] .arsize (maxi0_arsize[1:0]), // input[1:0]
.arburst (axi_arburst[1:0]), // input[1:0] .arburst (maxi0_arburst[1:0]), // input[1:0]
.rdata (axi_rdata[31:0]), // output[31:0] .rdata (maxi0_rdata[31:0]), // output[31:0]
.rvalid (axi_rvalid), // output reg .rvalid (maxi0_rvalid), // output reg
.rready (axi_rready), // input .rready (maxi0_rready), // input
.rid (axi_rid), // output[11:0] reg .rid (maxi0_rid), // output[11:0] reg
.rlast (axi_rlast), // output reg .rlast (maxi0_rlast), // output reg
.rresp (axi_rresp[1:0]), // output[1:0] .rresp (maxi0_rresp[1:0]), // output[1:0]
.pre_araddr (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0] .pre_araddr (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0]
.start_burst (axird_start_burst), // output .start_burst (axird_start_burst), // output
.dev_ready (axird_dev_ready), // input SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_read_i:dev_ready to constant 0 .dev_ready (axird_dev_ready), // input SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_read_i:dev_ready to constant 0
...@@ -1593,49 +1705,49 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1593,49 +1705,49 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
// //
.MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output .MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output
// AXI PS Master GP0: Read Address // AXI PS Master GP0: Read Address
.MAXIGP0ARADDR (axi_araddr[31:0]), // AXI PS Master GP0 ARADDR[31:0], output .MAXIGP0ARADDR (maxi0_araddr[31:0]), // AXI PS Master GP0 ARADDR[31:0], output
.MAXIGP0ARVALID (axi_arvalid), // AXI PS Master GP0 ARVALID, output .MAXIGP0ARVALID (maxi0_arvalid), // AXI PS Master GP0 ARVALID, output
.MAXIGP0ARREADY (axi_arready), // AXI PS Master GP0 ARREADY, input .MAXIGP0ARREADY (maxi0_arready), // AXI PS Master GP0 ARREADY, input
.MAXIGP0ARID (axi_arid[11:0]), // AXI PS Master GP0 ARID[11:0], output .MAXIGP0ARID (maxi0_arid[11:0]), // AXI PS Master GP0 ARID[11:0], output
.MAXIGP0ARLOCK (), // AXI PS Master GP0 ARLOCK[1:0], output .MAXIGP0ARLOCK (), // AXI PS Master GP0 ARLOCK[1:0], output
.MAXIGP0ARCACHE (),// AXI PS Master GP0 ARCACHE[3:0], output .MAXIGP0ARCACHE (),// AXI PS Master GP0 ARCACHE[3:0], output
.MAXIGP0ARPROT(), // AXI PS Master GP0 ARPROT[2:0], output .MAXIGP0ARPROT(), // AXI PS Master GP0 ARPROT[2:0], output
.MAXIGP0ARLEN (axi_arlen[3:0]), // AXI PS Master GP0 ARLEN[3:0], output .MAXIGP0ARLEN (maxi0_arlen[3:0]), // AXI PS Master GP0 ARLEN[3:0], output
.MAXIGP0ARSIZE (axi_arsize[1:0]), // AXI PS Master GP0 ARSIZE[1:0], output .MAXIGP0ARSIZE (maxi0_arsize[1:0]), // AXI PS Master GP0 ARSIZE[1:0], output
.MAXIGP0ARBURST (axi_arburst[1:0]),// AXI PS Master GP0 ARBURST[1:0], output .MAXIGP0ARBURST (maxi0_arburst[1:0]),// AXI PS Master GP0 ARBURST[1:0], output
.MAXIGP0ARQOS (), // AXI PS Master GP0 ARQOS[3:0], output .MAXIGP0ARQOS (), // AXI PS Master GP0 ARQOS[3:0], output
// AXI PS Master GP0: Read Data // AXI PS Master GP0: Read Data
.MAXIGP0RDATA (axi_rdata[31:0]), // AXI PS Master GP0 RDATA[31:0], input .MAXIGP0RDATA (maxi0_rdata[31:0]), // AXI PS Master GP0 RDATA[31:0], input
.MAXIGP0RVALID (axi_rvalid), // AXI PS Master GP0 RVALID, input .MAXIGP0RVALID (maxi0_rvalid), // AXI PS Master GP0 RVALID, input
.MAXIGP0RREADY (axi_rready), // AXI PS Master GP0 RREADY, output .MAXIGP0RREADY (maxi0_rready), // AXI PS Master GP0 RREADY, output
.MAXIGP0RID (axi_rid[11:0]), // AXI PS Master GP0 RID[11:0], input .MAXIGP0RID (maxi0_rid[11:0]), // AXI PS Master GP0 RID[11:0], input
.MAXIGP0RLAST (axi_rlast), // AXI PS Master GP0 RLAST, input .MAXIGP0RLAST (maxi0_rlast), // AXI PS Master GP0 RLAST, input
.MAXIGP0RRESP (axi_rresp[1:0]), // AXI PS Master GP0 RRESP[1:0], input .MAXIGP0RRESP (maxi0_rresp[1:0]), // AXI PS Master GP0 RRESP[1:0], input
// AXI PS Master GP0: Write Address // AXI PS Master GP0: Write Address
.MAXIGP0AWADDR (axi_awaddr[31:0]), // AXI PS Master GP0 AWADDR[31:0], output .MAXIGP0AWADDR (maxi0_awaddr[31:0]), // AXI PS Master GP0 AWADDR[31:0], output
.MAXIGP0AWVALID (axi_awvalid), // AXI PS Master GP0 AWVALID, output .MAXIGP0AWVALID (maxi0_awvalid), // AXI PS Master GP0 AWVALID, output
.MAXIGP0AWREADY (axi_awready), // AXI PS Master GP0 AWREADY, input .MAXIGP0AWREADY (maxi0_awready), // AXI PS Master GP0 AWREADY, input
.MAXIGP0AWID (axi_awid[11:0]), // AXI PS Master GP0 AWID[11:0], output .MAXIGP0AWID (maxi0_awid[11:0]), // AXI PS Master GP0 AWID[11:0], output
.MAXIGP0AWLOCK (), // AXI PS Master GP0 AWLOCK[1:0], output .MAXIGP0AWLOCK (), // AXI PS Master GP0 AWLOCK[1:0], output
.MAXIGP0AWCACHE (),// AXI PS Master GP0 AWCACHE[3:0], output .MAXIGP0AWCACHE (),// AXI PS Master GP0 AWCACHE[3:0], output
.MAXIGP0AWPROT (), // AXI PS Master GP0 AWPROT[2:0], output .MAXIGP0AWPROT (), // AXI PS Master GP0 AWPROT[2:0], output
.MAXIGP0AWLEN (axi_awlen[3:0]), // AXI PS Master GP0 AWLEN[3:0], output .MAXIGP0AWLEN (maxi0_awlen[3:0]), // AXI PS Master GP0 AWLEN[3:0], output
.MAXIGP0AWSIZE (axi_awsize[1:0]), // AXI PS Master GP0 AWSIZE[1:0], output .MAXIGP0AWSIZE (maxi0_awsize[1:0]), // AXI PS Master GP0 AWSIZE[1:0], output
.MAXIGP0AWBURST (axi_awburst[1:0]),// AXI PS Master GP0 AWBURST[1:0], output .MAXIGP0AWBURST (maxi0_awburst[1:0]),// AXI PS Master GP0 AWBURST[1:0], output
.MAXIGP0AWQOS (), // AXI PS Master GP0 AWQOS[3:0], output .MAXIGP0AWQOS (), // AXI PS Master GP0 AWQOS[3:0], output
// AXI PS Master GP0: Write Data // AXI PS Master GP0: Write Data
.MAXIGP0WDATA (axi_wdata[31:0]), // AXI PS Master GP0 WDATA[31:0], output .MAXIGP0WDATA (maxi0_wdata[31:0]), // AXI PS Master GP0 WDATA[31:0], output
.MAXIGP0WVALID (axi_wvalid), // AXI PS Master GP0 WVALID, output .MAXIGP0WVALID (maxi0_wvalid), // AXI PS Master GP0 WVALID, output
.MAXIGP0WREADY (axi_wready), // AXI PS Master GP0 WREADY, input .MAXIGP0WREADY (maxi0_wready), // AXI PS Master GP0 WREADY, input
.MAXIGP0WID (axi_wid[11:0]), // AXI PS Master GP0 WID[11:0], output .MAXIGP0WID (maxi0_wid[11:0]), // AXI PS Master GP0 WID[11:0], output
.MAXIGP0WLAST (axi_wlast), // AXI PS Master GP0 WLAST, output .MAXIGP0WLAST (maxi0_wlast), // AXI PS Master GP0 WLAST, output
.MAXIGP0WSTRB (axi_wstb[3:0]), // AXI PS Master GP0 WSTRB[3:0], output .MAXIGP0WSTRB (maxi0_wstb[3:0]), // AXI PS Master GP0 WSTRB[3:0], output
// AXI PS Master GP0: Write Responce // AXI PS Master GP0: Write Responce
.MAXIGP0BVALID (axi_bvalid), // AXI PS Master GP0 BVALID, input .MAXIGP0BVALID (maxi0_bvalid), // AXI PS Master GP0 BVALID, input
.MAXIGP0BREADY (axi_bready), // AXI PS Master GP0 BREADY, output .MAXIGP0BREADY (maxi0_bready), // AXI PS Master GP0 BREADY, output
.MAXIGP0BID (axi_bid[11:0]), // AXI PS Master GP0 BID[11:0], input .MAXIGP0BID (maxi0_bid[11:0]), // AXI PS Master GP0 BID[11:0], input
.MAXIGP0BRESP (axi_bresp[1:0]), // AXI PS Master GP0 BRESP[1:0], input .MAXIGP0BRESP (maxi0_bresp[1:0]), // AXI PS Master GP0 BRESP[1:0], input
// AXI PS Master GP1 // AXI PS Master GP1
// AXI PS Master GP1: Clock, Reset // AXI PS Master GP1: Clock, Reset
...@@ -1687,9 +1799,9 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1687,9 +1799,9 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
// AXI PS Slave GP0 // AXI PS Slave GP0
// AXI PS Slave GP0: Clock, Reset // AXI PS Slave GP0: Clock, Reset
.SAXIGP0ACLK(), // AXI PS Slave GP0 Clock , input .SAXIGP0ACLK (saxi0_aclk), // AXI PS Slave GP0 Clock , input
.SAXIGP0ARESETN(), // AXI PS Slave GP0 Reset, output .SAXIGP0ARESETN(), // AXI PS Slave GP0 Reset, output
// AXI PS Slave GP0: Read Address // AXI PS Slave GP0: Read Address - Not used
.SAXIGP0ARADDR(), // AXI PS Slave GP0 ARADDR[31:0], input .SAXIGP0ARADDR(), // AXI PS Slave GP0 ARADDR[31:0], input
.SAXIGP0ARVALID(), // AXI PS Slave GP0 ARVALID, input .SAXIGP0ARVALID(), // AXI PS Slave GP0 ARVALID, input
.SAXIGP0ARREADY(), // AXI PS Slave GP0 ARREADY, output .SAXIGP0ARREADY(), // AXI PS Slave GP0 ARREADY, output
...@@ -1701,7 +1813,7 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1701,7 +1813,7 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.SAXIGP0ARSIZE(), // AXI PS Slave GP0 ARSIZE[1:0], input .SAXIGP0ARSIZE(), // AXI PS Slave GP0 ARSIZE[1:0], input
.SAXIGP0ARBURST(), // AXI PS Slave GP0 ARBURST[1:0], input .SAXIGP0ARBURST(), // AXI PS Slave GP0 ARBURST[1:0], input
.SAXIGP0ARQOS(), // AXI PS Slave GP0 ARQOS[3:0], input .SAXIGP0ARQOS(), // AXI PS Slave GP0 ARQOS[3:0], input
// AXI PS Slave GP0: Read Data // AXI PS Slave GP0: Read Data - Not used
.SAXIGP0RDATA(), // AXI PS Slave GP0 RDATA[31:0], output .SAXIGP0RDATA(), // AXI PS Slave GP0 RDATA[31:0], output
.SAXIGP0RVALID(), // AXI PS Slave GP0 RVALID, output .SAXIGP0RVALID(), // AXI PS Slave GP0 RVALID, output
.SAXIGP0RREADY(), // AXI PS Slave GP0 RREADY, input .SAXIGP0RREADY(), // AXI PS Slave GP0 RREADY, input
...@@ -1709,29 +1821,29 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1709,29 +1821,29 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
.SAXIGP0RLAST(), // AXI PS Slave GP0 RLAST, output .SAXIGP0RLAST(), // AXI PS Slave GP0 RLAST, output
.SAXIGP0RRESP(), // AXI PS Slave GP0 RRESP[1:0], output .SAXIGP0RRESP(), // AXI PS Slave GP0 RRESP[1:0], output
// AXI PS Slave GP0: Write Address // AXI PS Slave GP0: Write Address
.SAXIGP0AWADDR(), // AXI PS Slave GP0 AWADDR[31:0], input .SAXIGP0AWADDR (saxi0_awaddr), // AXI PS Slave GP0 AWADDR[31:0], input
.SAXIGP0AWVALID(), // AXI PS Slave GP0 AWVALID, input .SAXIGP0AWVALID (saxi0_awvalid), // AXI PS Slave GP0 AWVALID, input
.SAXIGP0AWREADY(), // AXI PS Slave GP0 AWREADY, output .SAXIGP0AWREADY (saxi0_awready), // AXI PS Slave GP0 AWREADY, output
.SAXIGP0AWID(), // AXI PS Slave GP0 AWID[5:0], input .SAXIGP0AWID (saxi0_awid), // AXI PS Slave GP0 AWID[5:0], input
.SAXIGP0AWLOCK(), // AXI PS Slave GP0 AWLOCK[1:0], input .SAXIGP0AWLOCK (saxi0_awlock), // AXI PS Slave GP0 AWLOCK[1:0], input
.SAXIGP0AWCACHE(), // AXI PS Slave GP0 AWCACHE[3:0], input .SAXIGP0AWCACHE (saxi0_awcache), // AXI PS Slave GP0 AWCACHE[3:0], input
.SAXIGP0AWPROT(), // AXI PS Slave GP0 AWPROT[2:0], input .SAXIGP0AWPROT (saxi0_awprot), // AXI PS Slave GP0 AWPROT[2:0], input
.SAXIGP0AWLEN(), // AXI PS Slave GP0 AWLEN[3:0], input .SAXIGP0AWLEN (saxi0_awlen), // AXI PS Slave GP0 AWLEN[3:0], input
.SAXIGP0AWSIZE(), // AXI PS Slave GP0 AWSIZE[1:0], input .SAXIGP0AWSIZE (saxi0_awsize), // AXI PS Slave GP0 AWSIZE[1:0], input
.SAXIGP0AWBURST(), // AXI PS Slave GP0 AWBURST[1:0], input .SAXIGP0AWBURST (saxi0_awburst), // AXI PS Slave GP0 AWBURST[1:0], input
.SAXIGP0AWQOS(), // AXI PS Slave GP0 AWQOS[3:0], input .SAXIGP0AWQOS (saxi0_awqos), // AXI PS Slave GP0 AWQOS[3:0], input
// AXI PS Slave GP0: Write Data // AXI PS Slave GP0: Write Data
.SAXIGP0WDATA(), // AXI PS Slave GP0 WDATA[31:0], input .SAXIGP0WDATA (saxi0_wdata), // AXI PS Slave GP0 WDATA[31:0], input
.SAXIGP0WVALID(), // AXI PS Slave GP0 WVALID, input .SAXIGP0WVALID (saxi0_wvalid), // AXI PS Slave GP0 WVALID, input
.SAXIGP0WREADY(), // AXI PS Slave GP0 WREADY, output .SAXIGP0WREADY (saxi0_wready), // AXI PS Slave GP0 WREADY, output
.SAXIGP0WID(), // AXI PS Slave GP0 WID[5:0], input .SAXIGP0WID (saxi0_wid), // AXI PS Slave GP0 WID[5:0], input
.SAXIGP0WLAST(), // AXI PS Slave GP0 WLAST, input .SAXIGP0WLAST (saxi0_wlast), // AXI PS Slave GP0 WLAST, input
.SAXIGP0WSTRB(), // AXI PS Slave GP0 WSTRB[3:0], input .SAXIGP0WSTRB (saxi0_wstrb), // AXI PS Slave GP0 WSTRB[3:0], input
// AXI PS Slave GP0: Write Responce // AXI PS Slave GP0: Write Responce
.SAXIGP0BVALID(), // AXI PS Slave GP0 BVALID, output .SAXIGP0BVALID (saxi0_bvalid), // AXI PS Slave GP0 BVALID, output
.SAXIGP0BREADY(), // AXI PS Slave GP0 BREADY, input .SAXIGP0BREADY (saxi0_bready), // AXI PS Slave GP0 BREADY, input
.SAXIGP0BID(), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!! .SAXIGP0BID (saxi0_bid), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!!
.SAXIGP0BRESP(), // AXI PS Slave GP0 BRESP[1:0], output .SAXIGP0BRESP (saxi0_bresp), // AXI PS Slave GP0 BRESP[1:0], output
// AXI PS Slave GP1 // AXI PS Slave GP1
// AXI PS Slave GP1: Clock, Reset // AXI PS Slave GP1: Clock, Reset
...@@ -1783,8 +1895,8 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0]; ...@@ -1783,8 +1895,8 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
// AXI PS Slave HP0 // AXI PS Slave HP0
// AXI PS Slave HP0: Clock, Reset // AXI PS Slave HP0: Clock, Reset
.SAXIHP0ACLK (hclk), // AXI PS Slave HP0 Clock , input .SAXIHP0ACLK (hclk), // AXI PS Slave HP0 Clock , input
.SAXIHP0ARESETN (), // AXI PS Slave HP0 Reset, output .SAXIHP0ARESETN (), // AXI PS Slave HP0 Reset, output
// AXI PS Slave HP0: Read Address // AXI PS Slave HP0: Read Address
.SAXIHP0ARADDR (afi0_araddr), // AXI PS Slave HP0 ARADDR[31:0], input .SAXIHP0ARADDR (afi0_araddr), // AXI PS Slave HP0 ARADDR[31:0], input
.SAXIHP0ARVALID (afi0_arvalid), // AXI PS Slave HP0 ARVALID, input .SAXIHP0ARVALID (afi0_arvalid), // AXI PS Slave HP0 ARVALID, input
......
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