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Commit b70d24e3 authored by Andrey Filippov's avatar Andrey Filippov
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Tested CC,CS, SC, SS with random data

parent e2153595
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Showing with 248 additions and 91 deletions
dct_tests_01.sav
View file @ b70d24e3
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 5 02:26:14 2017
[*] Wed Dec 6 03:32:52 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_01-20171130150416223.fst"
[dumpfile_mtime] "Thu Nov 30 22:04:17 2017"
[dumpfile_size] 105262
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_01-20171205202130067.fst"
[dumpfile_mtime] "Wed Dec 6 03:21:30 2017"
[dumpfile_size] 164750
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_01.sav"
[timestart] 0
[size] 1814 1167
[pos] 1940 0
*-18.730682 785000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[size] 1920 1171
[pos] -8 0
*-19.730682 1595000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_01.
[treeopen] dct_tests_01.dct_iv8_1d_i.
[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
......@@ -20,7 +20,7 @@
[signals_width] 302
[sst_expanded] 1
[sst_vpaned_height] 343
@800200
@c00200
-top
@24
dct_tests_01.i
......@@ -96,9 +96,9 @@ dct_tests_01.y_dct[23:0]
dct_tests_01.y_out[23:0]
dct_tests_01.dct_iv8_1d_i.y_index[2:0]
dct_tests_01.x_in_2d[23:0]
@1000200
@1401200
-top
@c00200
@c00201
-2d-1d
@28
dct_tests_01.start
......@@ -161,7 +161,7 @@ dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.en_out
dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.y_index[2:0]
@200
-
@1401200
@1401201
-2d-1d
@c00200
-dct_iv8_1d
......@@ -400,7 +400,7 @@ dct_tests_01.dv_2dr
dct_tests_01.d_out_2dr[23:0]
@8420
dct_tests_01.d_out_2dr[23:0]
@800200
@c00200
-debug
@420
dct_tests_01.dct_iv_8x8_i.dcth_dout0[23:0]
......@@ -439,11 +439,54 @@ dct_tests_01.dct_iv_8x8_i.dctv_xin0[23:0]
dct_tests_01.dct_iv_8x8_i.dctv_xin1[23:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_start_0_r
@29
dct_tests_01.dct_iv_8x8_i.dctv_start_1_r
@800028
dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]
(1)dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_sel
dct_tests_01.dct_iv_8x8_i.dctv_out_we_2
@1001200
-group_end
@420
[color] 3
dct_tests_01.dct_iv_8x8_i.dctv_dout0[23:0]
[color] 2
dct_tests_01.dct_iv_8x8_i.dctv_dout1[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dctv_dout0[23:0]
dct_tests_01.dct_iv_8x8_i.dctv_dout1[23:0]
@22
[color] 6
dct_tests_01.dct_iv_8x8_i.dctv_out_cntr[6:0]
[color] 7
dct_tests_01.dct_iv_8x8_i.dctv_out_wa_1[3:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_sel
[color] 2
(0)dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_run
dct_tests_01.dct_iv_8x8_i.dctv_out_run_1
@22
[color] 3
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1[6:0]
[color] 2
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1_w[3:0]
@420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
@8420
[color] 5
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
@420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@28
dct_tests_01.dct_iv_8x8_i.pre_first_out
@200
-
@1000200
@1401200
-debug
@800200
-dct_iv_8x8
......@@ -680,14 +723,33 @@ dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0]
@8420
dct_tests_01.dct_iv_8x8_i.d_out[23:0]
@28
dct_tests_01.dct_iv_8x8_i.dv
dct_tests_01.dct_iv_8x8_i.pre_first_out
@420
dct_tests_01.dct_iv_8x8_i.pre_busy
@1000200
-dct_iv_8x8
@800200
@c00200
-dct_iv_8x8r
@28
dct_tests_01.dct_iv_8x8r_i.clk
dct_tests_01.dct_iv_8x8r_i.start
@8420
dct_tests_01.dct_iv_8x8r_i.xin[23:0]
dct_tests_01.dct_iv_8x8r_i.dcth_dout0[23:0]
dct_tests_01.dct_iv_8x8r_i.dcth_dout1[23:0]
@28
dct_tests_01.dct_iv_8x8r_i.transpose_start
@8420
dct_tests_01.dct_iv_8x8r_i.transpose_out[23:0]
@200
-
@1000200
@1401200
-dct_iv_8x8r
@1000200
-st22d_test
[pattern_trace] 1
[pattern_trace] 0
dct_tests_02.sav
View file @ b70d24e3
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 5 05:26:29 2017
[*] Wed Dec 6 02:19:47 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_02-20171204214928041.fst"
[dumpfile_mtime] "Tue Dec 5 04:49:28 2017"
[dumpfile_size] 180339
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_02-20171205191817720.fst"
[dumpfile_mtime] "Wed Dec 6 02:18:18 2017"
[dumpfile_size] 244333
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_02.sav"
[timestart] 1311000
[size] 1920 1171
[pos] -1723 40
*-19.492632 3855000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 0
[size] 1814 1171
[pos] 0 40
*-20.492632 1605000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_02.
[treeopen] dct_tests_02.dtt_iv_8x8_i.
[sst_width] 204
[treeopen] dct_tests_02.dtt_iv_8x8r_i.
[sst_width] 299
[signals_width] 287
[sst_expanded] 1
[sst_vpaned_height] 344
......@@ -29,8 +30,20 @@ dct_tests_02.start
dct_tests_02.start2
@22
dct_tests_02.mode_in[1:0]
dct_tests_02.mode_out[1:0]
@420
dct_tests_02.x_in_2d[23:0]
@8420
dct_tests_02.x_in_2d[23:0]
@420
dct_tests_02.d_out_2d[23:0]
@8420
dct_tests_02.d_out_2d[23:0]
@22
dct_tests_02.mode_out[1:0]
@420
dct_tests_02.d_out_2dr[23:0]
@8420
dct_tests_02.d_out_2dr[23:0]
@800200
-dtt_iv8x8_direct
@28
......@@ -39,8 +52,9 @@ dct_tests_02.dtt_iv_8x8_i.clk
dct_tests_02.dtt_iv_8x8_i.start
@22
dct_tests_02.dtt_iv_8x8_i.mode[1:0]
@420
dct_tests_02.dtt_iv_8x8_i.xin[23:0]
@8022
@8420
dct_tests_02.dtt_iv_8x8_i.xin[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.pre_last_in
......@@ -52,6 +66,8 @@ dct_tests_02.dtt_iv_8x8_i.d_out[23:0]
dct_tests_02.dtt_iv_8x8_i.d_out[23:0]
@800200
-debug
@28
dct_tests_02.dtt_iv_8x8_i.transpose_start
@420
dct_tests_02.dtt_iv_8x8_i.dcth_dout0[23:0]
@8420
......@@ -60,8 +76,6 @@ dct_tests_02.dtt_iv_8x8_i.dcth_dout0[23:0]
dct_tests_02.dtt_iv_8x8_i.dcth_dout1[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dcth_dout1[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.transpose_start
@22
dct_tests_02.dtt_iv_8x8_i.transpose_debug_di[7:0]
@8022
......@@ -115,7 +129,6 @@ dct_tests_02.dtt_iv_8x8_i.dctv_xin1[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_start_0_r
dct_tests_02.dtt_iv_8x8_i.dctv_start_1_r
dct_tests_02.dtt_iv_8x8_i.dctv_out_sel
dct_tests_02.dtt_iv_8x8_i.dctv_out_we_2
@800028
dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@28
......@@ -126,7 +139,9 @@ dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.dctv_out_we_1[1:0]
@420
[color] 3
dct_tests_02.dtt_iv_8x8_i.dctv_dout0[23:0]
[color] 2
dct_tests_02.dtt_iv_8x8_i.dctv_dout1[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dctv_dout0[23:0]
......@@ -134,22 +149,44 @@ dct_tests_02.dtt_iv_8x8_i.dctv_dout1[23:0]
@420
dct_tests_02.dtt_iv_8x8_i.debug_dctv_dout[23:0]
@8420
[color] 5
dct_tests_02.dtt_iv_8x8_i.debug_dctv_dout[23:0]
@22
[color] 6
dct_tests_02.dtt_iv_8x8_i.dctv_out_cntr[6:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_wa_1[4:0]
@8022
dct_tests_02.dtt_iv_8x8_i.dctv_out_wa_1[4:0]
@28
[color] 7
dct_tests_02.dtt_iv_8x8_i.dctv_out_sel
[color] 2
(0)dct_tests_02.dtt_iv_8x8_i.dctv_out_we_1[1:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_run
dct_tests_02.dtt_iv_8x8_i.dctv_out_start_1
dct_tests_02.dtt_iv_8x8_i.dctv_out_run_1
@22
[color] 3
dct_tests_02.dtt_iv_8x8_i.dctv_out_ra_1[6:0]
@420
[color] 2
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_1[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_2[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_1[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_2[23:0]
@1000200
-debug
@22
dct_tests_02.dtt_iv_8x8_i.mode_out[1:0]
@28
dct_tests_02.dtt_iv_8x8_i.pre_first_out_w
@8420
dct_tests_02.dtt_iv_8x8_i.d_out[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.dv
dct_tests_02.dtt_iv_8x8_i.pre_first_out
dct_tests_02.dtt_iv_8x8_i.pre_busy
@800200
dct_tests_02.dtt_iv_8x8_i.pre_first_out
@c00200
-direct_internal
@28
dct_tests_02.dtt_iv_8x8_i.dcth_en0
......@@ -180,6 +217,15 @@ dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
(1)dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@22
dct_tests_02.dtt_iv_8x8_i.dctv_out_cntr[6:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.dctv_out_we_1[1:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_run_1
@22
dct_tests_02.dtt_iv_8x8_i.dctv_out_ra_1[6:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_1[23:0]
@800200
-g3
@28
......@@ -191,17 +237,40 @@ dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_out
@28
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.start
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_in
@29
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_out
@200
-
@1001200
-group_end
@1000200
@1401200
-direct_internal
@1000200
-dtt_iv8x8_direct
@800200
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@28
dct_tests_02.dtt_iv_8x8r_i.clk
dct_tests_02.dtt_iv_8x8r_i.start
dct_tests_02.dtt_iv_8x8r_i.mode[1:0]
@420
dct_tests_02.dtt_iv_8x8r_i.xin[23:0]
@8420
dct_tests_02.dtt_iv_8x8r_i.xin[23:0]
@28
dct_tests_02.dtt_iv_8x8r_i.mode_out[1:0]
@800200
-inv_internals
@28
dct_tests_02.dtt_iv_8x8r_i.transpose_start
@8420
dct_tests_02.dtt_iv_8x8r_i.dcth_dout0[23:0]
dct_tests_02.dtt_iv_8x8r_i.dcth_dout1[23:0]
@8421
dct_tests_02.dtt_iv_8x8r_i.transpose_out[23:0]
@200
-
@1000200
-inv_internals
@200
-
@1000200
......
dsp/dct_tests_01.tf
View file @ b70d24e3
......@@ -40,7 +40,7 @@
`timescale 1ns/1ps
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
`define DCT_INPUT_UNITY
//`define DCT_INPUT_UNITY
module dct_tests_01 ();
// parameter fstname="dct_tests_01.fst";
`ifdef IVERILOG
......@@ -71,6 +71,8 @@ module dct_tests_01 ();
parameter DCT_GAP = 16; // between runs
parameter SAME_BITS=3;
reg RST = 1'b1;
reg CLK = 1'b0;
......@@ -124,14 +126,18 @@ module dct_tests_01 ();
wire signed [OUT_WIDTH-1:0] d_out_2dr; // SuppressThisWarning VEditor - simulation only
integer i,j, i1;
integer i,j, i1, ir;
initial begin
for (i=0; i<64; i=i+1) begin
`ifdef DCT_INPUT_UNITY
data_in[i] = (i[2:0] == i[5:3]) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
`else
data_in[i] = $random;
`endif
`ifdef DCT_INPUT_UNITY
data_in[i] = (i[2:0] == (i[5:3] ^ 3'h1)) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
ir= (i[2:0] == (i[5:3] ^ 3'h1)) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
data_in[i] = ir;
`else
ir = $random;
data_in[i] = ((i[5:3] == 0) || (i[5:3] == 7) || (i[2:0] == 0) || (i[2:0] == 7))? 0:
{{SAME_BITS{ir[WIDTH -SAME_BITS - 1]}},ir[WIDTH -SAME_BITS-1:0]};
`endif
end
$display("Input data in line-scan order:");
for (i=0; i<64; i=i+8) begin
......
dsp/dct_tests_02.tf
View file @ b70d24e3
......@@ -40,7 +40,7 @@
`timescale 1ns/1ps
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
`define DCT_INPUT_UNITY
//`define DCT_INPUT_UNITY
module dct_tests_02 ();
// parameter fstname="dct_tests_02.fst";
`ifdef IVERILOG
......@@ -71,6 +71,7 @@ module dct_tests_02 ();
parameter DCT_GAP = 16; // between runs
parameter SAME_BITS=3;
reg RST = 1'b1;
reg CLK = 1'b0;
......@@ -95,7 +96,7 @@ module dct_tests_02 ();
reg start = 0;
reg start2 = 0; // second start for 2d
reg [1:0] mode_in= 3; // [0] - vertical pass 0: dct, 1 - dst, [1] - horizontal pass
reg [1:0] mode_in= 0; // 3; // [0] - vertical pass 0: dct, 1 - dst, [1] - horizontal pass
wire [1:0] mode_out; // [0] - vertical pass 0: dct, 1 - dst, [1] - horizontal pass
wire [OUT_WIDTH-1:0] y_dct;
......@@ -126,14 +127,18 @@ module dct_tests_02 ();
wire signed [OUT_WIDTH-1:0] d_out_2dr; // SuppressThisWarning VEditor - simulation only
integer i,j, i1;
integer i,j, i1, ir;
initial begin
for (i=0; i<64; i=i+1) begin
`ifdef DCT_INPUT_UNITY
data_in[i] = (i[2:0] == i[5:3]) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
`else
data_in[i] = $random;
`endif
`ifdef DCT_INPUT_UNITY
data_in[i] = (i[2:0] == (i[5:3] ^ 3'h0)) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
ir= (i[2:0] == (i[5:3] ^ 3'h1)) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
data_in[i] = ir;
`else
ir = $random;
data_in[i] = ((i[5:3] == 0) || (i[5:3] == 7) || (i[2:0] == 0) || (i[2:0] == 7))? 0:
{{SAME_BITS{ir[WIDTH -SAME_BITS - 1]}},ir[WIDTH -SAME_BITS-1:0]};
`endif
end
$display("Input data in line-scan order:");
for (i=0; i<64; i=i+8) begin
......@@ -372,7 +377,7 @@ module dct_tests_02 ();
.clk (CLK), // input
.rst (RST), // input
.start (pre_first_out_2d), // input
.mode (mode_out), // input[1:0]
.mode ({mode_out[0],mode_out[1]}), // input[1:0] // result is transposed
.xin (d_out_2d), // input[24:0] signed
.pre_last_in (pre_last_in_2dr), // output reg
.pre_first_out (pre_first_out_2dr), // output
......
dsp/dtt_iv_8x8.v
View file @ b70d24e3
......@@ -178,29 +178,38 @@ module dtt_iv_8x8#(
// wire dctv_out_start = dctv_phin [6:0] == 'h10;
wire dctv_out_start = dctv_phin [6:0] == 'h11;
reg [3:0] dctv_out_wa_1;
reg [4:0] dctv_out_wa_1;
reg [1:0] dctv_out_we_1;
reg dctv_out_sel; // select DCTv channel output;
reg signed [OUT_WIDTH-1:0] dctv_out_ram_1[0:15];
reg [2:0] dctv_out_debug_ram_1[0:15];
reg signed [OUT_WIDTH-1:0] dctv_out_ram_1[0:31];
reg [2:0] dctv_out_debug_ram_1[0:31];
reg [6:0] dctv_out_ra_1;
wire [3:0] dctv_out_ra_1_w = {dctv_out_ra_1[3:1], ~dctv_out_ra_1[0]};
wire dctv_out_start_1 = dctv_out_cntr[6:0] == 'h0c; // 'h0b;
// wire [3:0] dctv_out_ra_1_w = {dctv_out_ra_1[3:1], ~dctv_out_ra_1[0]};
/*
wire [3:0] dctv_out_ra_1_w = {dctv_out_ra_1[3],
dctv_out_ra_1[2] ? dctv_out_ra_1[1] : (~dctv_out_ra_1[1] ^ dctv_out_ra_1[0]),
~dctv_out_ra_1[2] ^ dctv_out_ra_1[0],
~dctv_out_ra_1[0]};
*/
// wire dctv_out_start_1 = dctv_out_cntr[6:0] == 'h0c; // 'h0b;
/// wire dctv_out_start_1 = dctv_out_cntr[6:0] == 'h0b; // 'h0b;
wire dctv_out_start_1 = dctv_out_cntr[6:0] == 'h0e; // 'h0b;
reg dctv_out_run_1;
reg signed [OUT_WIDTH-1:0] dctv_out_reg_1;
reg [2:0] dctv_out_debug_reg_1;
reg signed [OUT_WIDTH-1:0] dctv_out_ram_2[0:3];
reg [2:0] dctv_out_debug_ram_2[0:3];
reg [2:0] dctv_out_debug_reg_1; // SuppressThisWarning VEditor - simulation only
/*
reg signed [OUT_WIDTH-1:0] dctv_out_ram_2[0:7];
reg [2:0] dctv_out_debug_ram_2[0:7];
reg dctv_out_we_2;
reg [1:0] dctv_out_wa_2;
reg [2:0] dctv_out_wa_2;
reg [6:0] dctv_out_ra_2;
wire dctv_out_start_2 = dctv_out_ra_1[6:0] == 2;
// wire dctv_out_start_2 = dctv_out_ra_1[6:0] == 2;
wire dctv_out_start_2 = dctv_out_ra_1[6:0] == 8;
reg dctv_out_run_2;
reg signed [OUT_WIDTH-1:0] dctv_out_reg_2;
reg [2:0] dctv_out_debug_reg_2; // SuppressThisWarning VEditor - simulation only
*/
// reg [1:0] mode_in; //
// reg [1:0] mode_in; //
......@@ -217,10 +226,12 @@ module dtt_iv_8x8#(
wire [1:0] pre2_dstv; // 2 cycles before vertical output data is valid, 0 dct, 1 - dst
reg pre_dsth; // 1 cycles before horizontal output data is valid, 0 dct, 1 - dst
reg pre_dstv; // 1 cycles before vertical output data is valid, 0 dct, 1 - dst
wire pre_first_out_w = dctv_out_ra_1[6:0] == 1;
// wire pre_first_out_w = dctv_out_ra_1[6:0] == 1;
wire pre_first_out_w = dctv_out_start_1;
wire [OUT_WIDTH-1:0] debug_dctv_dout = dctv_out_sel? dctv_dout1: dctv_dout0;
assign d_out = dctv_out_reg_2;
wire [OUT_WIDTH-1:0] debug_dctv_dout = dctv_out_sel? dctv_dout1: dctv_dout0; // SuppressThisWarning VEditor - simulation only
// assign d_out = dctv_out_reg_2;
assign d_out = dctv_out_reg_1;
assign pre_last_in = pre_last_in_r;
......@@ -378,24 +389,24 @@ module dtt_iv_8x8#(
dctv_out_sel <= dctv_out_cntr[0];
case (dctv_out_cntr[3:0])
4'h0: dctv_out_wa_1 <= 0 ^ {3{pre_dstv}};
4'h1: dctv_out_wa_1 <= 9 ^ {3{pre_dstv}};
4'h2: dctv_out_wa_1 <= 7 ^ {3{pre_dstv}};
4'h3: dctv_out_wa_1 <= 14 ^ {3{pre_dstv}};
4'h4: dctv_out_wa_1 <= 4 ^ {3{pre_dstv}};
4'h5: dctv_out_wa_1 <= 10 ^ {3{pre_dstv}};
4'h6: dctv_out_wa_1 <= 3 ^ {3{pre_dstv}};
4'h7: dctv_out_wa_1 <= 13 ^ {3{pre_dstv}};
4'h8: dctv_out_wa_1 <= 1 ^ {3{pre_dstv}};
4'h9: dctv_out_wa_1 <= 8 ^ {3{pre_dstv}};
4'ha: dctv_out_wa_1 <= 6 ^ {3{pre_dstv}};
4'hb: dctv_out_wa_1 <= 15 ^ {3{pre_dstv}};
4'hc: dctv_out_wa_1 <= 2 ^ {3{pre_dstv}};
4'hd: dctv_out_wa_1 <= 12 ^ {3{pre_dstv}};
4'he: dctv_out_wa_1 <= 5 ^ {3{pre_dstv}};
4'hf: dctv_out_wa_1 <= 11 ^ {3{pre_dstv}};
4'h0: dctv_out_wa_1[3:0] <= 0 ^ {3{pre_dstv}};
4'h1: dctv_out_wa_1[3:0] <= 9 ^ {3{pre_dstv}};
4'h2: dctv_out_wa_1[3:0] <= 7 ^ {3{pre_dstv}};
4'h3: dctv_out_wa_1[3:0] <= 14 ^ {3{pre_dstv}};
4'h4: dctv_out_wa_1[3:0] <= 4 ^ {3{pre_dstv}};
4'h5: dctv_out_wa_1[3:0] <= 10 ^ {3{pre_dstv}};
4'h6: dctv_out_wa_1[3:0] <= 3 ^ {3{pre_dstv}};
4'h7: dctv_out_wa_1[3:0] <= 13 ^ {3{pre_dstv}};
4'h8: dctv_out_wa_1[3:0] <= 1 ^ {3{pre_dstv}};
4'h9: dctv_out_wa_1[3:0] <= 8 ^ {3{pre_dstv}};
4'ha: dctv_out_wa_1[3:0] <= 6 ^ {3{pre_dstv}};
4'hb: dctv_out_wa_1[3:0] <= 15 ^ {3{pre_dstv}};
4'hc: dctv_out_wa_1[3:0] <= 2 ^ {3{pre_dstv}};
4'hd: dctv_out_wa_1[3:0] <= 12 ^ {3{pre_dstv}};
4'he: dctv_out_wa_1[3:0] <= 5 ^ {3{pre_dstv}};
4'hf: dctv_out_wa_1[3:0] <= 11 ^ {3{pre_dstv}};
endcase
dctv_out_wa_1[4] <= dctv_out_cntr[4] ^ (~dctv_out_cntr[3] & dctv_out_cntr[0]);
// write first stage of output reordering
if (dctv_out_we_1[1]) dctv_out_ram_1[dctv_out_wa_1] <= dctv_out_sel? dctv_dout1: dctv_dout0;
if (dctv_out_we_1[1]) dctv_out_debug_ram_1[dctv_out_wa_1] <= dctv_out_sel? dctv_yindex1: dctv_yindex0;
......@@ -407,13 +418,15 @@ module dtt_iv_8x8#(
if (!dctv_out_run_1 || dctv_out_start_1) dctv_out_ra_1 <= 0;
else dctv_out_ra_1 <= dctv_out_ra_1 + 1;
// reading first stage of output reorder RAM
if (dctv_out_run_1) dctv_out_reg_1 <= dctv_out_ram_1[dctv_out_ra_1_w];
if (dctv_out_run_1) dctv_out_debug_reg_1 <= dctv_out_debug_ram_1[dctv_out_ra_1_w];
// last stage of the output reordering - 4 register memory
// if (dctv_out_run_1) dctv_out_reg_1 <= dctv_out_ram_1[dctv_out_ra_1_w];
// if (dctv_out_run_1) dctv_out_debug_reg_1 <= dctv_out_debug_ram_1[dctv_out_ra_1_w];
if (dctv_out_run_1) dctv_out_reg_1 <= dctv_out_ram_1[dctv_out_ra_1[4:0]];
if (dctv_out_run_1) dctv_out_debug_reg_1 <= dctv_out_debug_ram_1[dctv_out_ra_1[4:0]];
// last stage of the output reordering - 8 register memory
/*
dctv_out_we_2 <= dctv_out_run_1;
dctv_out_wa_2 <= dctv_out_ra_1_w[1:0];
dctv_out_wa_2 <= dctv_out_ra_1_w[2:0];
// write last stage of output reordering
if (dctv_out_we_2) dctv_out_ram_2[dctv_out_wa_2] <= dctv_out_reg_1;
......@@ -427,12 +440,14 @@ module dtt_iv_8x8#(
else dctv_out_ra_2 <= dctv_out_ra_2 + 1;
// reading first stage of output reorder RAM
if (dctv_out_run_2) dctv_out_reg_2 <= dctv_out_ram_2[dctv_out_ra_2[1:0]];
if (dctv_out_run_2) dctv_out_debug_reg_2 <= dctv_out_debug_ram_2[dctv_out_ra_2[1:0]];
if (dctv_out_run_2) dctv_out_reg_2 <= dctv_out_ram_2[dctv_out_ra_2[2:0]];
if (dctv_out_run_2) dctv_out_debug_reg_2 <= dctv_out_debug_ram_2[dctv_out_ra_2[2:0]];
*/
pre_first_out <= pre_first_out_w;
dv <= dctv_out_run_2;
// dv <= dctv_out_run_2;
dv <= dctv_out_run_1;
end
always @ (posedge clk) begin
......
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