Commit b4ec76e3 authored by Andrey Filippov's avatar Andrey Filippov

merged with framepars

parents 85c297b7 3603cb56
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Dec 6 17:55:24 2016
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 13 19:43:18 2016
[*]
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[treeopen] dct_tests_01.dct_iv_8x8_i.
[treeopen] dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i.
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......@@ -87,10 +90,82 @@ dct_tests_01.y_we
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......@@ -105,8 +180,6 @@ dct_tests_01.dct_iv8_1d_i.start
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(0)dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_sel
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_wa_1[3:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_start_1
dct_tests_01.dct_iv_8x8_i.dctv_out_run_1
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1[6:0]
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1_w[3:0]
@420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_1[2:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_we_2
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_wa_2[1:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_out_run_2
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_ra_2[6:0]
@420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0]
@1000200
-dct_iv_8x8
@800200
-dct_iv_8x8r
@200
-
@1000200
-dct_iv_8x8r
-st22d_test
[pattern_trace] 1
[pattern_trace] 0
No preview for this file type
......@@ -71,11 +71,10 @@ module dct_iv8_1d#(
output [OUT_WIDTH -1:0] dout,
output reg pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence
// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
output reg en_out // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)
output en_out, // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data
output reg [2:0] y_index // for simulation - valid with dout - index of the data output
);
// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
localparam RSHIFT1 = 2; // safe right shift for stage 1
localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates
......@@ -132,6 +131,11 @@ module dct_iv8_1d#(
reg run_in; // receiving input data
reg restart; // restarting next block if en was active at phase=14;
reg run_out; // running output data
reg en_out_r;
reg en_out_r2;
assign en_out = en_out_r;
assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];
......@@ -147,6 +151,23 @@ module dct_iv8_1d#(
wire din_zero = ~(|d_in);
assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};
always @ (posedge clk) begin
en_out_r2 <= en_out_r;
if (en_out_r2) begin
case (phase_cnt[3:1])
3'h0: y_index <= 0;
3'h1: y_index <= 7;
3'h2: y_index <= 4;
3'h3: y_index <= 3;
3'h4: y_index <= 1;
3'h5: y_index <= 6;
3'h6: y_index <= 2;
3'h7: y_index <= 5;
endcase
end else begin
y_index <= 'bx;
end
end
//register files
assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
......@@ -173,7 +194,7 @@ module dct_iv8_1d#(
pre2_start_out <= run_out && (phase_cnt == 14);
en_out <= run_out && !phase_cnt[0];
en_out_r <= run_out && !phase_cnt[0];
// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
case (phase_cnt)
......
/*!
* <b>Module:</b>dct_iv_8x8
* @file dct_iv_8x8.v
* @date 2016-12-08
* @author Andrey Filippov
*
* @brief 2-d DCT-IV implementation, 1 clock/data word. Input in scanline order, output - transposed
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
*dct_iv_8x8.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dct_iv_8x8.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module dct_iv_8x8#(
parameter INPUT_WIDTH = 25,
parameter OUT_WIDTH = 25,
parameter OUT_RSHIFT1 = 1, // overall right shift of the result from input, aligned by MSB for pass1 (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 1, // if sum OUT_RSHIFT1+OUT_RSHIFT2 == 2, direct*reverse == ident (may use 3, -1) or 3,0 with wider output and saturate
parameter TRANSPOSE_WIDTH = 25, // transpose memory width
parameter DSP_B_WIDTH = 18,
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter COSINE_SHIFT= 17,
parameter COS_01_32 = 130441, // int(round((1<<17) * cos( 1*pi/32)))
parameter COS_03_32 = 125428, // int(round((1<<17) * cos( 3*pi/32)))
parameter COS_04_32 = 121095, // int(round((1<<17) * cos( 4*pi/32)))
parameter COS_05_32 = 115595, // int(round((1<<17) * cos( 5*pi/32)))
parameter COS_07_32 = 101320, // int(round((1<<17) * cos( 7*pi/32)))
parameter COS_08_32 = 92682, // int(round((1<<17) * cos( 8*pi/32)))
parameter COS_09_32 = 83151, // int(round((1<<17) * cos( 9*pi/32)))
parameter COS_11_32 = 61787, // int(round((1<<17) * cos(11*pi/32)))
parameter COS_12_32 = 50159, // int(round((1<<17) * cos(12*pi/32)))
parameter COS_13_32 = 38048, // int(round((1<<17) * cos(13*pi/32)))
parameter COS_15_32 = 12847 // int(round((1<<17) * cos(15*pi/32)))
) (
input clk, //!< system clock, posedge
input rst, //!< sync reset
input start, //!< single-cycle start pulse that goes with the first pixel data.
// Next data should be sent in bursts of 8, pause of 8 - total 128 cycles
input signed [INPUT_WIDTH-1:0] xin, //!< input data
output pre_last_in, //!< output high during input of the pre-last of 64 pixels in a 8x8 block (next can be start
output reg pre_first_out, //!< 1 cycle ahead of the first output in a 64 block
output reg dv, //!< data output valid. WAS: Will go high on the 94-th cycle after the start
output signed [OUT_WIDTH-1:0] d_out, //!< output data
output reg pre_busy); //!< start should come each 64-th cycle (next after pre_last_in), and not after pre_busy)
// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock
// 2. of the horizontal DCTs
// 3. common transpose memory plus 2 input reorder memory for each of the vertical DCT
// 4. 2 of the vertical DCTs
// 5. small memory to combine/reorder outputs (2 stages as 1 x16 memory is not enough)
// TODO make a version that uses common transpose memory (twice width) and simultaneously calculates dst-iv (invert time sequence, alternate sign)
// That can be used for lateral chromatic aberration (shift in time domain). Reverse transform does not need it - will always be just dct-iv
reg x_run;
reg [5:0] x_wa;
wire dcth_phin_start = x_run && (x_wa[5:0] == 6);
reg dcth_phin_run;
reg dcth_en0;
reg dcth_en1;
reg [6:0] dcth_phin;
reg [2:0] x_ra0;
reg [2:0] x_ra1;
reg signed [INPUT_WIDTH-1:0] x_ram0[0:7];
reg signed [INPUT_WIDTH-1:0] x_ram1[0:7];
reg signed [INPUT_WIDTH-1:0] dcth_xin0;
reg signed [INPUT_WIDTH-1:0] dcth_xin1;
wire signed [TRANSPOSE_WIDTH-1:0] dcth_dout0;
wire signed [TRANSPOSE_WIDTH-1:0] dcth_dout1;
// wire dcth_pre2_start_out0;
// wire dcth_pre2_start_out1;
wire dcth_en_out0;
wire dcth_en_out1;
wire dcth_start_0_w = dcth_phin_run && (dcth_phin [6:0] ==0);
wire dcth_start_1_w = dcth_phin_run && (dcth_phin [6:0] ==9);
reg dcth_start_0_r;
reg dcth_start_1_r;
reg [1:0] transpose_w_page;
reg [6:0] transpose_cntr; // transpose memory counter, [6] == 1 when the last page is being finished
reg transpose_in_run;
// wire transpose_start = dcth_phin_run && (dcth_phin [6:0] == 7'h10);
wire transpose_start = dcth_phin_run && (dcth_phin [6:0] == 7'h11);
// wire transpose_start = dcth_phin_run && (dcth_phin [6:0] == 7'h12);
reg [2:0] transpose_wa_low; // [2:0] transpose memory low address bits, [3] - other group (of 16)
reg [4:0] transpose_wa_high; // high bits of transpose memory write address
wire [7:0] transpose_wa = {transpose_wa_high,transpose_wa_low};
wire transpose_wa_decr = (transpose_cntr[0] & ~transpose_cntr[3]);
reg [1:0] transpose_we; // [1]
wire [TRANSPOSE_WIDTH-1:0] transpose_di = transpose_cntr[0]? dcth_dout0: dcth_dout1;
reg [TRANSPOSE_WIDTH-1:0] transpose_ram[0:255];
wire [2:0] dcth_yindex0;
wire [2:0] dcth_yindex1;
wire [7:0] transpose_debug_di= {transpose_wa_high, transpose_cntr[0]? dcth_yindex0: dcth_yindex1};
reg [7:0] transpose_debug_ram[0:255];
reg [6:0] transpose_rcntr; // transpose read memory counter, [6] == 1 when the last page is being finished
reg [2:0] transpose_out_run;
wire transpose_out_start = transpose_in_run && (transpose_cntr[6:0] == 7'h34); // 7'h33 is actual minimum
reg [1:0] transpose_r_page;
reg signed [TRANSPOSE_WIDTH-1:0] transpose_reg; // internal BRAM register
reg signed [TRANSPOSE_WIDTH-1:0] transpose_out; // output BRAM register
reg [7:0] transpose_debug_reg; // internal BRAM register
reg [7:0] transpose_debug_out; // output BRAM register
wire [7:0] transpose_ra = {transpose_r_page, transpose_rcntr[2:0], transpose_rcntr[5:3]};
reg [3:0] t_wa;
wire t_we0 = transpose_out_run[2] && !t_wa[3];
wire t_we1 = transpose_out_run[2] && t_wa[3];
reg signed [TRANSPOSE_WIDTH-1:0] t_ram0[0:7];
reg signed [TRANSPOSE_WIDTH-1:0] t_ram1[0:7];
reg signed [TRANSPOSE_WIDTH-1:0] dctv_xin0;
reg signed [TRANSPOSE_WIDTH-1:0] dctv_xin1;
reg signed [7:0] t_debug_ram0[0:7];
reg signed [7:0] t_debug_ram1[0:7];
reg signed [7:0] dctv_debug_xin0; // SuppressThisWarning VEditor - simulation only
reg signed [7:0] dctv_debug_xin1; // SuppressThisWarning VEditor - simulation only
wire signed [OUT_WIDTH-1:0] dctv_dout0;
wire signed [OUT_WIDTH-1:0] dctv_dout1;
wire dctv_en_out0;
wire dctv_en_out1;
wire [2:0] dctv_yindex0;
wire [2:0] dctv_yindex1;
wire dctv_phin_start = transpose_out_run && (transpose_rcntr[5:0] == 8);
reg dctv_phin_run;
reg dctv_en0;
reg dctv_en1;
reg [6:0] dctv_phin;
reg [2:0] t_ra0;
reg [2:0] t_ra1;
wire dctv_start_0_w = dctv_phin_run && (dctv_phin [6:0] ==0);
wire dctv_start_1_w = dctv_phin_run && (dctv_phin [6:0] ==9);
reg dctv_start_0_r;
reg dctv_start_1_r;
reg pre_last_in_r;
reg [6:0] dctv_out_cntr; // count output data from second (vertical) pass (bit 6 - stopping)
reg dctv_out_run; //
// wire dctv_out_start = dctv_phin [6:0] == 'h10;
wire dctv_out_start = dctv_phin [6:0] == 'h11;
reg [3:0] dctv_out_wa_1;
reg [1:0] dctv_out_we_1;
reg dctv_out_sel; // select DCTv channel output;
reg signed [OUT_WIDTH-1:0] dctv_out_ram_1[0:15];
reg [2:0] dctv_out_debug_ram_1[0:15];
reg [6:0] dctv_out_ra_1;
wire [3:0] dctv_out_ra_1_w = {dctv_out_ra_1[3:1], ~dctv_out_ra_1[0]};
wire dctv_out_start_1 = dctv_out_cntr[6:0] == 'h0c; // 'h0b;
reg dctv_out_run_1;
reg signed [OUT_WIDTH-1:0] dctv_out_reg_1;
reg [2:0] dctv_out_debug_reg_1;
reg signed [OUT_WIDTH-1:0] dctv_out_ram_2[0:3];
reg [2:0] dctv_out_debug_ram_2[0:3];
reg dctv_out_we_2;
reg [1:0] dctv_out_wa_2;
reg [6:0] dctv_out_ra_2;
wire dctv_out_start_2 = dctv_out_ra_1[6:0] == 2;
reg dctv_out_run_2;
reg signed [OUT_WIDTH-1:0] dctv_out_reg_2;
reg [2:0] dctv_out_debug_reg_2; // SuppressThisWarning VEditor - simulation only
assign d_out = dctv_out_reg_2;
assign pre_last_in = pre_last_in_r;
always @ (posedge clk) begin
if (rst) x_run <= 0;
else if (start) x_run <= 1;
else if (&x_wa[5:0]) x_run <= 0;
if (!x_run) x_wa <= 0;
else x_wa <= x_wa + 1;
pre_last_in_r <= x_run && (x_wa[5:0] == 'h3d);
if (rst) pre_busy <= 0;
else if (pre_last_in_r) pre_busy <= 1;
else if (dcth_phin [5:0] == 5) pre_busy <= 0; // check actual?
if (rst) dcth_phin_run <= 0;
else if (dcth_phin_start) dcth_phin_run <= 1;
else if (dcth_phin [6:0] == 7'h48) dcth_phin_run <= 0; // check actual?
if (!dcth_phin_run || dcth_phin_start) dcth_phin <= 0;
else dcth_phin <= dcth_phin + 1;
if (rst) dcth_en0 <= 0;
else if (dcth_start_0_w) dcth_en0 <= 1;