Commit b4ec76e3 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

merged with framepars

parents 85c297b7 3603cb56

dct_tests_01.sav

+417 −16
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] Tue Dec  6 17:55:24 2016

[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI

[*] Tue Dec 13 19:43:18 2016

[*]

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dct_tests_01.dct_iv_8x8_i.dctv_out_cntr[6:0]

@28

(0)dct_tests_01.dct_iv_8x8_i.dctv_out_we_1[1:0]

dct_tests_01.dct_iv_8x8_i.dctv_out_sel

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dct_tests_01.dct_iv_8x8_i.dctv_out_wa_1[3:0]

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dct_tests_01.dct_iv_8x8_i.dctv_out_start_1

dct_tests_01.dct_iv_8x8_i.dctv_out_run_1

@22

dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1[6:0]

dct_tests_01.dct_iv_8x8_i.dctv_out_ra_1_w[3:0]

@420

dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]

@8420

dct_tests_01.dct_iv_8x8_i.dctv_out_reg_1[23:0]

@22

dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_1[2:0]

@28

dct_tests_01.dct_iv_8x8_i.dctv_out_we_2

@22

dct_tests_01.dct_iv_8x8_i.dctv_out_wa_2[1:0]

@28

dct_tests_01.dct_iv_8x8_i.dctv_out_run_2

@22

dct_tests_01.dct_iv_8x8_i.dctv_out_ra_2[6:0]

@420

dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]

@8420

dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0]

@22

dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0]

@1000200

-dct_iv_8x8

@800200

-dct_iv_8x8r

@200

-

@1000200

-dct_iv_8x8r

-st22d_test

[pattern_trace] 1

[pattern_trace] 0

dsp/dct_iv.ods

+6.67 KiB (82.5 KiB)

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dsp/dct_iv8_1d.v

+26 −5
Original line number Diff line number Diff line
@@ -71,11 +71,10 @@ module dct_iv8_1d#( 
    output [OUT_WIDTH -1:0]        dout,

    output reg                     pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence

                                             // start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5

    output reg                     en_out    // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)                                      

    output                         en_out,   // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data

    output reg               [2:0] y_index   // for simulation - valid with dout - index of the data output

                                          

);

// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*

// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*

// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*



    localparam RSHIFT1 = 2; // safe right shift for stage 1

    localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates
@@ -132,6 +131,11 @@ module dct_iv8_1d#( 
    reg                         run_in;  // receiving input data

    reg                         restart; // restarting next block if en was active at phase=14;

    reg                         run_out; // running output data

    reg                         en_out_r;

    reg                         en_out_r2;

    

    

    assign en_out = en_out_r;

    

    assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];
@@ -147,6 +151,23 @@ module dct_iv8_1d#( 
    wire din_zero = ~(|d_in);

    assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};



    always @ (posedge clk) begin

        en_out_r2 <= en_out_r;

        if (en_out_r2) begin

            case (phase_cnt[3:1])

                3'h0: y_index <= 0;

                3'h1: y_index <= 7;

                3'h2: y_index <= 4;

                3'h3: y_index <= 3;

                3'h4: y_index <= 1;

                3'h5: y_index <= 6;

                3'h6: y_index <= 2;

                3'h7: y_index <= 5;

            endcase

        end else begin

            y_index <= 'bx;

        end 

    end



    //register files

    assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
@@ -173,7 +194,7 @@ module dct_iv8_1d#( 
    

        pre2_start_out <= run_out && (phase_cnt == 14);

        

        en_out <= run_out && !phase_cnt[0];

        en_out_r <= run_out && !phase_cnt[0];

        

        // Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand

        case (phase_cnt)