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Commit b135946f authored by Andrey Filippov's avatar Andrey Filippov
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added serial-to-parallel converter for JTAG from the sensor ports, to increase bitstream load speed

parent edcdce95
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Showing with 33 additions and 17 deletions
.project
View file @ b135946f
......@@ -62,52 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160406001220877.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160417173535326.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160406001856812.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160417175241357.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160406001220877.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160417173535326.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160406001220877.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160417173535326.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -127,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160406001220877.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160417173535326.dcp</location>
</link>
</linkedResources>
</projectDescription>
fpga_version.vh
View file @ b135946f
......@@ -32,7 +32,8 @@
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped
parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load
// parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched
// parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met
// parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF
// parameter FPGA_VERSION = 32'h03930082; // trying other path to read xfpgatdo
......
py393/x393_export_c.py
View file @ b135946f
......@@ -1676,8 +1676,9 @@ class X393ExportC(object):
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling (N/A for HiSPI"))
dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output, previous 8 bits"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output, current"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
......
py393/x393_sensor.py
View file @ b135946f
......@@ -167,12 +167,16 @@ class X393Sensor(object):
print (" sof_mclk = %d"%((status>>17) & 1))
print (" sol_mclk = %d"%((status>>16) & 1))
"""
"""
#Folowing 5 bits may be just temporarily available
print (" irst = %d"%((status>>20) & 1))
print ("async_prst_with_sens_mrst = %d"%((status>>19) & 1))
print (" imrst = %d"%((status>>18) & 1))
print (" rst_mmcm = %d"%((status>>17) & 1))
print (" pxd_out_pre[1] = %d"%((status>>16) & 1))
"""
print (" shifted TDO %d"%((status>>16) & 0xff))
print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1))
......
sensor/sens_parallel12.v
View file @ b135946f
......@@ -192,7 +192,8 @@ module sens_parallel12 #(
// wire [17:0] status;
// wire [18:0] status;
wire [22:0] status;
// wire [22:0] status;
wire [25:0] status; // added byte-wide xfpgatdo
wire cmd_we;
wire [2:0] cmd_a;
......@@ -200,6 +201,7 @@ module sens_parallel12 #(
wire xfpgadone; // state of the MRST pin ("DONE" pin on external FPGA)
wire xfpgatdo; // TDO read from external FPGA
reg [7:0] xfpgatdo_byte; // tdo signal shifted left at each TCK _/~
wire senspgmin;
reg xpgmen=0; // enable programming mode for external FPGA
......@@ -233,11 +235,15 @@ module sens_parallel12 #(
// assign status = {pxd_out_pre[1],vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
// clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
// ps_rdy, ps_out, xfpgatdo, senspgmin};
assign status = {irst, async_prst_with_sens_mrst, imrst, rst_mmcm, pxd_out_pre[1],
// wire [25:0] status; // added byte-wide xfpgatdo
assign status = {
/// irst, async_prst_with_sens_mrst, imrst, rst_mmcm, pxd_out_pre[1],
xfpgatdo_byte[7:0],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
assign hact_out = hact_r;
assign iaro = trigger_mode? ~trig : iaro_soft;
......@@ -282,6 +288,10 @@ module sens_parallel12 #(
if (mclk_rst) xfpgatck <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TCK + 1]) xfpgatck <= data_r[SENS_JTAG_TCK];
// shift xfpgatdo to xfpgatdo_byte each time xfpgatck is 0->1
if (mclk_rst) xfpgatdo_byte <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TCK + 1] && !xfpgatck && data_r[SENS_JTAG_TCK]) xfpgatdo_byte <= {xfpgatdo_byte[6:0], xfpgatdo};
if (mclk_rst) xfpgatms <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TMS + 1]) xfpgatms <= data_r[SENS_JTAG_TMS];
......
x393.bit
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