Commit abaada40 authored by Andrey Filippov's avatar Andrey Filippov

Added instructions about unisims

parent 1053a1ba
......@@ -8,3 +8,9 @@ FPGA code for Elphel 393 camera, created with [VDT plugin](
[Documentation]( is generated with Doxygen-based Doxverilog.
Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproject files for Eclipse
Simulation of this project requires some files from the Xilinx proprietary _unisims_ library (list of dependencies
is in this [blog post]( ).
[VDT plugin]( README file describes steps needed after installation of Xilinx software
(unisims library is not distributed separatly).
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