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Elphel
x393
Commits
a7004146
Commit
a7004146
authored
Apr 04, 2015
by
Andrey Filippov
Browse files
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Browse Files
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some cleanup, added command that runs full set of measurement/adjustment functions
parent
4a9e4b55
Changes
6
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Inline
Side-by-side
Showing
6 changed files
with
805 additions
and
231 deletions
+805
-231
get_test_dq_dqs_data.py
py393/get_test_dq_dqs_data.py
+23
-1
x393_lma.py
py393/x393_lma.py
+38
-63
x393_mcntrl_adjust.py
py393/x393_mcntrl_adjust.py
+718
-157
x393_mcntrl_buffers.py
py393/x393_mcntrl_buffers.py
+11
-8
x393_mcntrl_timing.py
py393/x393_mcntrl_timing.py
+12
-0
x393_pio_sequences.py
py393/x393_pio_sequences.py
+3
-2
No files found.
py393/get_test_dq_dqs_data.py
View file @
a7004146
...
...
@@ -914,7 +914,8 @@ def get_wlev_data():
{
'ldly'
:
68
,
'period'
:
0
,
'err'
:
0.032233890055650249
},
{
'ldly'
:
67
,
'period'
:
0
,
'err'
:
0.45716638330499393
},
{
'ldly'
:
64
,
'period'
:
0
,
'err'
:
-
0.23339414538470038
},
{
'ldly'
:
63
,
'period'
:
0
,
'err'
:
-
0.42992632596594405
},
{
'ldly'
:
62
,
'period'
:
0
,
'err'
:
-
0.004993832716600366
},
{
'ldly'
:
59
,
'period'
:
0
,
'err'
:
-
0.69555436140630178
},
{
'ldly'
:
59
,
'period'
:
0
,
'err'
:
0.81705889991982161
},
{
'ldly'
:
56
,
'period'
:
0
,
'err'
:
-
0.030778077807781301
},
{
'ldly'
:
57
,
'period'
:
0
,
'err'
:
1.0454592125879216
},
{
'ldly'
:
54
,
'period'
:
0
,
'err'
:
0.35489868389822021
}],
[{
'ldly'
:
50
,
'period'
:
-
1
,
'err'
:
0.90683082593974973
},
{
'ldly'
:
49
,
'period'
:
-
1
,
'err'
:
0.52528052805281789
},
{
'ldly'
:
54
,
'period'
:
0
,
'err'
:
0.35489868389822021
}],
[{
'ldly'
:
50
,
'period'
:
-
1
,
'err'
:
0.90683082593974973
},
{
'ldly'
:
49
,
'period'
:
-
1
,
'err'
:
0.52528052805281789
},
{
'ldly'
:
46
,
'period'
:
-
1
,
'err'
:
-
0.10166902404525047
},
{
'ldly'
:
45
,
'period'
:
-
1
,
'err'
:
0.38526466932408709
},
{
'ldly'
:
44
,
'period'
:
-
1
,
'err'
:
0.0037143714371552505
},
{
'ldly'
:
42
,
'period'
:
-
1
,
'err'
:
0.1118091809181081
},
{
'ldly'
:
40
,
'period'
:
-
1
,
'err'
:
-
0.13630148729157554
},
{
'ldly'
:
39
,
'period'
:
-
1
,
'err'
:
-
0.51785178517850738
},
{
'ldly'
:
37
,
'period'
:
-
1
,
'err'
:
-
0.40975697569755454
},
{
'ldly'
:
36
,
'period'
:
-
1
,
'err'
:
0.34800994385153672
},
{
'ldly'
:
35
,
'period'
:
-
1
,
'err'
:
0.83494363722087428
},
...
...
@@ -1025,6 +1026,27 @@ def get_dqsi_vs_phase(variant):
[(
None
,
None
,
'e'
),
(
150
,
0.75
,
'e'
)],
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
[(
20
,
None
,
'n'
),
(
7
,
-
0.25
,
'n'
)],
[(
29
,
0.25
,
'n'
),
(
5
,
None
,
'n'
)],
[(
25
,
None
,
'n'
),
(
10
,
0.75
,
'n'
)],
[(
25
,
None
,
'n'
),
(
14
,
0.25
,
'n'
)],
[(
31
,
0.75
,
'n'
),
(
10
,
None
,
'n'
)],
[(
34
,
0.0
,
'n'
),
(
16
,
-
0.25
,
'n'
)],
[(
30
,
None
,
'n'
),
(
17
,
0.0
,
'n'
)],
[(
30
,
None
,
'n'
),
(
19
,
-
0.75
,
'n'
)]]
elif
variant
==
1
:
return
[[(
36
,
0.5
,
'n'
),
(
15
,
None
,
'n'
)],
[(
39
,
0.25
,
'n'
),
(
22
,
0.5
,
'n'
)],
[(
35
,
None
,
'n'
),
(
24
,
0.0
,
'n'
)],
[(
35
,
None
,
'n'
),
(
20
,
None
,
'n'
)],
[(
38
,
None
,
'n'
),
(
26
,
0.75
,
'n'
)],
[(
44
,
0.0
,
'n'
),
(
28
,
-
0.25
,
'n'
)],
[(
40
,
None
,
'n'
),
(
29
,
-
0.5
,
'n'
)],
[(
45
,
0.0
,
'n'
),
(
30
,
0.5
,
'n'
)],
[(
46
,
0.25
,
'n'
),
(
32
,
0.25
,
'n'
)],
[(
45
,
None
,
'n'
),
(
33
,
-
0.25
,
'n'
)],
[(
45
,
None
,
'n'
),
(
30
,
None
,
'n'
)],
[(
45
,
None
,
'n'
),
(
35
,
0.75
,
'n'
)],
[(
53
,
0.75
,
'n'
),
(
38
,
-
0.25
,
'n'
)],
[(
50
,
None
,
'n'
),
(
39
,
-
0.75
,
'n'
)],
[(
50
,
None
,
'n'
),
(
41
,
0.5
,
'n'
)],
[(
56
,
0.75
,
'n'
),
(
44
,
0.5
,
'n'
)],
[(
55
,
None
,
'n'
),
(
40
,
None
,
'n'
)],
[(
55
,
None
,
'n'
),
(
40
,
None
,
'n'
)],
[(
56
,
None
,
'n'
),
(
47
,
-
0.25
,
'n'
)],
[(
63
,
0.25
,
'n'
),
(
45
,
None
,
'n'
)],
[(
60
,
None
,
'n'
),
(
45
,
None
,
'n'
)],
[(
65
,
0.25
,
'n'
),
(
54
,
0.25
,
'n'
)],
[(
66
,
0.0
,
'n'
),
(
54
,
-
0.25
,
'n'
)],
[(
65
,
None
,
'n'
),
(
50
,
None
,
'n'
)],
[(
65
,
None
,
'n'
),
(
56
,
0.0
,
'n'
)],
[(
70
,
0.5
,
'n'
),
(
59
,
-
0.5
,
'n'
)],
[(
71
,
0.25
,
'n'
),
(
55
,
None
,
'n'
)],
[(
70
,
None
,
'n'
),
(
55
,
None
,
'n'
)],
[(
70
,
None
,
'n'
),
(
64
,
0.25
,
'n'
)],
[(
76
,
0.5
,
'n'
),
(
60
,
None
,
'n'
)],
[(
75
,
None
,
'n'
),
(
60
,
None
,
'n'
)],
[(
75
,
None
,
'n'
),
(
65
,
-
0.5
,
'n'
)],
None
,
[(
84
,
0.0
,
'n'
),
(
65
,
None
,
'n'
)],
[(
80
,
None
,
'n'
),
(
71
,
-
0.25
,
'n'
)],
[(
None
,
None
,
'n'
),
(
73
,
-
0.75
,
'n'
)],
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
[(
127
,
0.5
,
'e'
),
(
116
,
-
0.75
,
'e'
)],
[(
125
,
None
,
'e'
),
(
115
,
None
,
'e'
)],
[(
125
,
None
,
'e'
),
(
120
,
0.5
,
'e'
)],
[(
130
,
0.5
,
'e'
),
(
123
,
0.0
,
'e'
)],
[(
131
,
0.0
,
'e'
),
(
119
,
None
,
'e'
)],
[(
134
,
0.0
,
'e'
),
(
120
,
None
,
'e'
)],
[(
130
,
None
,
'e'
),
(
120
,
None
,
'e'
)],
[(
131
,
None
,
'e'
),
(
127
,
0.0
,
'e'
)],
[(
135
,
None
,
'e'
),
(
124
,
None
,
'e'
)],
[(
135
,
None
,
'e'
),
(
125
,
None
,
'e'
)],
[(
140
,
0.25
,
'e'
),
(
131
,
0.25
,
'e'
)],
[(
141
,
0.25
,
'e'
),
(
134
,
0.0
,
'e'
)],
[(
140
,
None
,
'e'
),
(
130
,
None
,
'e'
)],
[(
140
,
None
,
'e'
),
(
130
,
None
,
'e'
)],
[(
140
,
None
,
'e'
),
(
135
,
-
0.5
,
'e'
)],
[(
149
,
0.25
,
'e'
),
(
135
,
None
,
'e'
)],
[(
145
,
None
,
'e'
),
(
135
,
None
,
'e'
)],
[(
145
,
None
,
'e'
),
(
135
,
None
,
'e'
)],
[(
151
,
0.75
,
'e'
),
(
141
,
0.0
,
'e'
)],
[(
150
,
None
,
'e'
),
(
140
,
None
,
'e'
)],
[(
150
,
None
,
'e'
),
(
145
,
0.75
,
'e'
)],
[(
155
,
0.0
,
'e'
),
(
145
,
0.25
,
'e'
)],
[(
158
,
0.0
,
'e'
),
(
149
,
-
0.5
,
'e'
)],
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
None
,
[(
26
,
0.25
,
'n'
),
(
9
,
-
0.5
,
'n'
)],
[(
29
,
0.25
,
'n'
),
(
10
,
0.0
,
'n'
)],
[(
25
,
None
,
'n'
),
(
13
,
0.5
,
'n'
)],
[(
25
,
None
,
'n'
),
(
10
,
None
,
'n'
)],
[(
33
,
0.25
,
'n'
),
(
10
,
None
,
'n'
)],
[(
30
,
None
,
'n'
),
(
17
,
-
0.25
,
'n'
)],
[(
30
,
None
,
'n'
),
(
18
,
-
0.5
,
'n'
)]]
def
get_dqsi_vs_phase_prim_steps
(
variant
=
0
):
# while scanning, compare this delay with 1 less by primary(not fine) step,
# save None for fraction in unknown (previous -0.5, next +0.5)
...
...
py393/x393_lma.py
View file @
a7004146
...
...
@@ -311,9 +311,12 @@ class X393LMA(object):
except
:
pass
if
not
numBits
:
# print("showENLresults(): No no-None data provided")
# print("DQvDQS=",DQvDQS)
# return
raise
Exception
(
"showENLresults(): No no-None data provided"
)
numLanes
=
numBits
//
8
# print ("numBits=%d"%(numBits))
# print ("
****
numBits=%d"%(numBits))
enl_list
=
[]
for
k
in
rslt_names
:
if
DQvDQS
[
k
]:
...
...
@@ -1036,7 +1039,7 @@ class X393LMA(object):
if
quiet
<
2
:
print
(
"parameters=
%
s"
%
(
str
(
parameters
)))
self
.
normalizeParameters
(
parameters
)
#isMask=False)
if
quiet
<
4
:
if
quiet
<
3
:
print
(
"normalized parameters=
%
s"
%
(
str
(
parameters
)))
"""
both ways work:
...
...
@@ -1069,12 +1072,13 @@ class X393LMA(object):
print
(
"
\n
fx (filtered):"
)
self
.
showYOrVector
(
ywp
,
True
,
fx
)
if
quiet
<
4
:
if
quiet
<
5
:
arms
=
self
.
getParAvgRMS
(
parameters
,
ywp
,
primary_set
,
# prima
quiet
+
1
)
print
(
"average(fx)=
%
fps, rms(fx)=
%
fps"
%
(
arms
[
'avg'
],
arms
[
'rms'
]))
print
(
"Before LMA (DQ lane
%
d): average(fx)=
%
fps, rms(fx)=
%
fps"
%
(
lane
,
arms
[
'avg'
],
arms
[
'rms'
]))
if
quiet
<
3
:
jByJT
=
np
.
dot
(
fxj
[
'jacob'
],
np
.
transpose
(
fxj
[
'jacob'
]))
print
(
"
\n
jByJT:"
)
...
...
@@ -1092,7 +1096,7 @@ class X393LMA(object):
self
.
lambdas
,
self
.
finalDiffRMS
,
quiet
)
if
(
quiet
<
4
)
or
((
quiet
<
5
)
and
finished
):
if
(
quiet
<
5
)
or
((
quiet
<
6
)
and
finished
):
arms
=
self
.
getParAvgRMS
(
parameters
,
ywp
,
primary_set
,
# prima
...
...
@@ -1126,36 +1130,6 @@ class X393LMA(object):
DQvDQS
=
DQvDQS_withErr
[
'dqForDqs'
]
DQvDQS_ERR
=
DQvDQS_withErr
[
'maxErrDqs'
]
if
quiet
<
4
:
# print ("DQvDQS_ERR=",DQvDQS_ERR)
enl_list
=
[]
for
i
in
range
(
3
):
if
not
DQvDQS
[
i
]
is
None
:
enl_list
.
append
(
i
)
print
(
"DQS"
,
end
=
" "
)
for
enl
in
enl_list
:
for
b
in
range
(
8
):
print
(
"
%
s
%
d"
%
((
'E'
,
'N'
,
'L'
)[
enl
],
b
),
end
=
" "
)
for
enl
in
enl_list
:
print
(
"
%
s-Err"
%
((
'E'
,
'N'
,
'L'
)[
enl
]),
end
=
" "
)
print
()
for
dly
in
range
(
DLY_STEPS
):
print
(
"
%
d"
%
(
dly
),
end
=
" "
)
for
enl
in
enl_list
:
if
DQvDQS
[
enl
][
dly
]
is
None
:
print
(
"? "
*
8
,
end
=
""
)
else
:
for
b
in
range
(
8
):
if
DQvDQS
[
enl
][
dly
][
b
]
is
None
:
print
(
"?"
,
end
=
" "
)
else
:
print
(
"
%
d"
%
(
DQvDQS
[
enl
][
dly
][
b
]),
end
=
" "
)
for
enl
in
enl_list
:
if
DQvDQS_ERR
[
enl
][
dly
]
is
None
:
print
(
"? "
,
end
=
""
)
else
:
print
(
"
%
f"
%
(
DQvDQS_ERR
[
enl
][
dly
]),
end
=
" "
)
print
()
rslt
=
{}
rslt_names
=
(
"early"
,
"nominal"
,
"late"
)
for
i
,
d
in
enumerate
(
DQvDQS
):
...
...
@@ -1165,15 +1139,13 @@ class X393LMA(object):
rslt
[
'maxErrDqs'
]
=
{}
# {enl}[dly]
for
i
,
d
in
enumerate
(
DQvDQS_ERR
):
rslt
[
'maxErrDqs'
][
rslt_names
[
i
]]
=
d
if
quiet
<
4
:
if
quiet
<
3
:
self
.
showDQDQSValues
(
parameters
)
# print ("DQvDQS_ERR=",DQvDQS_ERR)
# print ("rslt['maxErrDqs']=",rslt['maxErrDqs'])
if
quiet
<
3
:
print
(
"*** quiet="
,
quiet
)
self
.
showENLresults
(
rslt
)
# here DQvDQS already contain the needed data
return
rslt
# return DQvDQS
# Returns 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
# each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too)
def
getBestDQforDQS
(
self
,
...
...
@@ -1204,6 +1176,7 @@ class X393LMA(object):
asym_err
=
[]
for
i
in
range
(
8
):
asym_err
.
append
(
0.25
*
(
abs
(
tDQSHL
)
+
abs
(
tDQHL
[
i
])))
if
quiet
<
3
:
print
(
"asym_err="
,
asym_err
)
dqForDqs
=
[]
maxErrDqs
=
[]
...
...
@@ -1617,15 +1590,13 @@ class X393LMA(object):
lane
,
# byte lane
bin_size_ps
,
clk_period
,
# phase_step, # ~22ps
# dly_step_ds,
# primary_set,
dqsi_dqi_parameters
,
data_set
,
compare_prim_steps
,
scale_w
,
numPhaseSteps
,
quiet
=
1
):
# print("++++++lma_fit_dqsi_phase(), quiet=",quiet)
def
show_input_data
(
filtered
):
print
((
'unfiltered'
,
'filtered'
)[
filtered
])
for
phase
,
d
in
enumerate
(
data_set
):
...
...
@@ -1668,6 +1639,7 @@ class X393LMA(object):
SX
+=
binArr
[
i
]
*
i
if
S0
>
0
:
SX
/=
S0
if
quiet
<
3
:
print
(
"SX="
,
SX
)
return
minVal
+
bin_size_ps
*
(
SX
+
0.5
)
# ps
...
...
@@ -1686,7 +1658,7 @@ class X393LMA(object):
compare_prim_steps
,
scale_w
,
numPhaseSteps
,
quiet
=
1
)
quiet
)
for
name
in
rslt_names
:
rslt
[
name
]
.
append
(
rslt_lane
[
name
])
if
quiet
<
3
:
...
...
@@ -1713,8 +1685,9 @@ class X393LMA(object):
dbg_tSDQS
=
(
dqsi_dqi_parameters
[
0
][
'tSDQS'
],
dqsi_dqi_parameters
[
1
][
'tSDQS'
])
halfStep
=
0.5
*
(
1
,
compare_prim_steps
)[
compare_prim_steps
]
#phase_step/tSDQS
print
(
phase_step
,
dbg_tSDQS
)
# print("lma_fit_dqsi_phase(): quiet=",quiet
)
if
quiet
<
2
:
print
(
phase_step
,
dbg_tSDQS
)
for
filtered
in
range
(
2
):
show_input_data
(
filtered
)
...
...
@@ -1723,11 +1696,13 @@ class X393LMA(object):
minVal
=
-
clk_period
num_bins
=
int
((
maxVal
-
minVal
)
/
bin_size_ps
)
+
1
binArr
=
[
0
]
*
num_bins
if
quiet
<
2
:
print
(
"minVal="
,
minVal
)
print
(
"maxVal="
,
maxVal
)
print
(
"num_bins="
,
num_bins
)
#find main max
dly_max0
=
get_shift_by_hist
()
# delay in ps, corresponding to largest maximum
if
quiet
<
2
:
print
(
"max0=
%
f, (
%
f)"
%
(
dly_max0
,
dly_max0
/
tSDQS
))
periods
=
[
None
]
*
len
(
data_set
)
for
phase
,
d
in
enumerate
(
data_set
):
...
...
@@ -1751,19 +1726,19 @@ class X393LMA(object):
dl
=
d
[
lane
]
if
(
not
dl
is
None
)
and
(
not
dl
[
0
]
is
None
):
dly
=
dl
[
0
]
w
[
i
]
=
1.0
w
[
phase
]
=
1.0
if
dl
[
1
]
is
None
:
dly
+=
halfStep
w
[
i
]
=
scale_w
w
[
phase
]
=
scale_w
d
=
dly
*
tSDQS
-
periods
[
phase
]
*
clk_period
-
tFDQS
[
dl
[
0
]
%
FINE_STEPS
]
y
=
d
-
phase
*
phase_step
S0
+=
w
[
i
]
SY
+=
w
[
i
]
*
y
S0
+=
w
[
phase
]
SY
+=
w
[
phase
]
*
y
if
S0
>
0.0
:
SY
/=
S0
print
(
"shift="
,
SY
,
" ps"
)
if
quiet
<
2
:
print
(
"shift="
,
SY
,
" ps"
)
for
phase
,
d
in
enumerate
(
data_set
):
print
(
"
%
d"
%
(
phase
),
end
=
" "
)
if
not
d
is
None
:
...
...
py393/x393_mcntrl_adjust.py
View file @
a7004146
This diff is collapsed.
Click to expand it.
py393/x393_mcntrl_buffers.py
View file @
a7004146
...
...
@@ -132,13 +132,16 @@ class X393McntrlBuffers(object):
def
write_block_buf_chn
(
self
,
#
chn
,
# input integer chn; # buffer channel
page
,
# input [1:0] page;
num_words_or_data_list
):
# input integer num_words; # number of words to write (will be rounded up to multiple of 16)
num_words_or_data_list
,
# input integer num_words; # number of words to write (will be rounded up to multiple of 16)
quiet
=
1
):
"""
Fill specified buffer with the pattern data
@param chn 4-bit buffer channel (0..4) to write data to
@param page 2-bit buffer page to write to
@param num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
@param quiet reduce output
"""
if
quiet
<
2
:
print
(
"===write_block_buf_chn() chn=0x
%
x, page=0x
%
x"
%
(
chn
,
page
),
end
=
" "
)
if
isinstance
(
num_words_or_data_list
,
list
):
try
:
...
...
py393/x393_mcntrl_timing.py
View file @
a7004146
...
...
@@ -185,6 +185,7 @@ class X393McntrlTiming(object):
@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
if delay is None will restore default values
Alternatively it can be a one-level list/tuple covering all (16) delays
@param quiet reduce output
"""
# print("====axi_set_dq_idelay %s"%str(delay))
...
...
@@ -196,6 +197,11 @@ class X393McntrlTiming(object):
delay
[
1
]
.
append
(
vrlg
.
get_default_field
(
"DLY_LANE1_IDELAY"
,
i
))
if
isinstance
(
delay
,(
int
,
long
)):
delay
=
(
delay
,
delay
)
elif
len
(
delay
)
%
8
==
0
:
delay2
=
[]
for
lane
in
range
(
len
(
delay
)
//
8
):
delay2
.
append
(
delay
[
8
*
lane
:
8
*
(
lane
+
1
)])
delay
=
delay2
if
quiet
<
2
:
print
(
"SET DQ IDELAY="
+
hexMultiple
(
delay
))
# hexMultiple
self
.
axi_set_multiple_delays
(
vrlg
.
LD_DLY_LANE0_IDELAY
,
0
,
8
,
delay
[
0
],
"DLY_LANE0_IDELAY"
)
...
...
@@ -211,6 +217,7 @@ class X393McntrlTiming(object):
@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
if delay is None will restore default values
Alternatively it can be a one-level list/tuple covering all (16) delays
@param quiet reduce output
"""
if
delay
is
None
:
...
...
@@ -220,6 +227,11 @@ class X393McntrlTiming(object):
delay
[
1
]
.
append
(
vrlg
.
get_default_field
(
"DLY_LANE1_ODELAY"
,
i
))
if
isinstance
(
delay
,(
int
,
long
)):
delay
=
(
delay
,
delay
)
elif
len
(
delay
)
%
8
==
0
:
delay2
=
[]
for
lane
in
range
(
len
(
delay
)
//
8
):
delay2
.
append
(
delay
[
8
*
lane
:
8
*
(
lane
+
1
)])
delay
=
delay2
if
quiet
<
2
:
print
(
"SET DQ ODELAY="
+
hexMultiple
(
delay
))
# hexMultiple
self
.
axi_set_multiple_delays
(
vrlg
.
LD_DLY_LANE0_ODELAY
,
0
,
8
,
delay
[
0
],
"DLY_LANE0_ODELAY"
);
...
...
py393/x393_pio_sequences.py
View file @
a7004146
...
...
@@ -532,6 +532,7 @@ class X393PIOSequences(object):
@sel - 0 - early, 1 - late read command
@verbose print data being written (default: False)
"""
if
verbose
>
0
:
print
(
"===set_write_block ba=0x
%
x, ra=0x
%
x, ca=0x
%
x, num8=
%
d extraTgl=
%
d, sel=
%
d, verbose=
%
d"
%
(
ba
,
ra
,
ca
,
num8
,
extraTgl
,
sel
,
verbose
))
cmd_addr
=
vrlg
.
MCONTR_CMD_WR_ADDR
+
vrlg
.
WRITE_BLOCK_OFFSET
# activate
...
...
@@ -790,7 +791,7 @@ class X393PIOSequences(object):
<en_refresh> enable refresh immediately
<verbose> print data being written (default: False)
"""
print
(
"SET REFRESH: tRFC=
%
d, tREFI=
%
d"
%
(
t_rfc
,
t_refi
))
print
(
"
****
SET REFRESH: tRFC=
%
d, tREFI=
%
d"
%
(
t_rfc
,
t_refi
))
cmd_addr
=
vrlg
.
MCONTR_CMD_WR_ADDR
+
vrlg
.
REFRESH_OFFSET
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data
=
self
.
func_encode_cmd
(
0
,
0
,
6
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
)
...
...
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