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Commit a6df0611 authored by Andrey Filippov's avatar Andrey Filippov
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got images from Boson640

parent bf463e76
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cocotb/x393_dut.v
View file @ a6df0611
......@@ -1949,7 +1949,8 @@ simul_axi_hp_wr #(
`elsif BOSON
wire boson_single = 1;
reg boson_single = 1;
reg [3:0] boson_restart = 0; // extra reset to break the frame
wire [BOSON_OUT_BITS-1:0] boson_pxd1;
wire [BOSON_OUT_BITS-1:0] boson_pxd2;
wire [BOSON_OUT_BITS-1:0] boson_pxd3;
......@@ -1971,7 +1972,15 @@ simul_axi_hp_wr #(
wire boson_hsync3;
wire boson_hsync4;
// delay start of the sensor video (disable in external sync mode)
initial begin
#100000;
boson_single = 0;
#100000;
boson_restart = 4'b0101; // only 2 channels restarted
#1000;
boson_restart = 0;
end
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
......@@ -1986,6 +1995,7 @@ simul_axi_hp_wr #(
.mrst (sns1_dp[7]), // input
.single (boson_single), // input 1'b0), //
.ext_sync (sns1_ctl), // input
.bad_frame_end (boson_restart[0]), // input - just to introduce a bad_frame
.pxd (boson_pxd1), // output[15:0]
.pclk (boson_pclk1), // output
.dvalid (boson_dvalid1), // output
......@@ -2025,6 +2035,7 @@ simul_axi_hp_wr #(
.mrst (sns2_dp[7]), // input
.single (boson_single), // input 1'b0), //
.ext_sync (sns2_ctl), // input
.bad_frame_end (boson_restart[1]), // input - just to introduce a bad_frame
.pxd (boson_pxd2), // output[15:0]
.pclk (boson_pclk2), // output
.dvalid (boson_dvalid2), // output
......@@ -2064,6 +2075,7 @@ simul_axi_hp_wr #(
.mrst (sns3_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns3_ctl), // input
.bad_frame_end (boson_restart[2]), // input - just to introduce a bad_frame
.pxd (boson_pxd3), // output[15:0]
.pclk (boson_pclk3), // output
.dvalid (boson_dvalid3), // output
......@@ -2103,6 +2115,7 @@ simul_axi_hp_wr #(
.mrst (sns4_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns4_ctl), // input
.bad_frame_end (boson_restart[3]), // input - just to introduce a bad_frame
.pxd (boson_pxd4), // output[15:0]
.pclk (boson_pclk4), // output
.dvalid (boson_dvalid4), // output
......
fpga_version.vh
View file @ a6df0611
......@@ -35,7 +35,22 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930202; // Initial Boson implementation (cheating with 2.5V), open drain for Boson reset
parameter FPGA_VERSION = 32'h0393020f; // added test mode
// parameter FPGA_VERSION = 32'h0393020f; // changing MMCM phase -20.0 (use clk_fb) IBUF_LOW_PWR=FALSE
// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -20.0 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020d; // changing MMCM phase -18.0 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020c; // changing MMCM phase 18.0 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020b; // clock/feedback clock
// parameter FPGA_VERSION = 32'h0393020a; // 2.5, diff-term, no low-power, fixing delays
// parameter FPGA_VERSION = 32'h03930209; // 2.5, diff-term, no low-power
// parameter FPGA_VERSION = 32'h03930208; // 1.8V, no diff-term
// parameter FPGA_VERSION = 32'h03930207; // Debugging 2.5V, diff-term
// parameter FPGA_VERSION = 32'h03930206; // Debugging
// parameter FPGA_VERSION = 32'h03930205; // Fixing serial pairs order for 103993
// parameter FPGA_VERSION = 32'h03930204; // Testing
// parameter FPGA_VERSION = 32'h03930203; // Fixing serial receive with dual stop bits
// parameter FPGA_VERSION = 32'h03930202; // Initial Boson implementation (cheating with 2.5V), open drain for Boson reset
// parameter FPGA_VERSION = 32'h03930201; // Initial Boson implementation (cheating with 2.5V - as with HISPI)
// parameter FPGA_VERSION = 32'h03930200; // Initial Boson implementation (1.8V)
//BOSON
......
includes/x393_parameters.vh
View file @ a6df0611
......@@ -678,16 +678,18 @@
`ifdef SIMULATION
parameter UART_CLK_DIV = 22,
parameter UART_RX_DEBOUNCE = 6,
parameter UART_STOP_BITS = 2, // for testing, maybe change later back to 1
`else
parameter UART_CLK_DIV = 217,
parameter UART_RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1,
`endif
parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
// endof for BOSON:
// parameters for the sensor-synchronous clock PLL
// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
`define TWEAKING_IOSTANDARD
//`define TWEAKING_IOSTANDARD 1
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
......@@ -704,7 +706,8 @@
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
parameter CLKFBOUT_PHASE_SENSOR = -19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`ifdef TWEAKING_IOSTANDARD
......@@ -790,7 +793,11 @@
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
`ifdef BOSON
parameter HISPI_IBUF_LOW_PWR = "FALSE", // "TRUE",
`else
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`endif
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
......
py393/x393_sensor.py
View file @ a6df0611
......@@ -185,7 +185,8 @@ class X393Sensor(object):
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL))
def print_status_sensor_io (self,
num_sensor="All", sensorType = SENSOR_INTERFACE_PARALLEL):
num_sensor="All",
sensorType = SENSOR_INTERFACE_PARALLEL):
"""
Print sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
......@@ -212,7 +213,7 @@ class X393Sensor(object):
print (" busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
elif (sensorType == SENSOR_INTERFACE_BOSON):
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" ps_out = 0x%x"%((status>> 0) & 0xff))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" perr = %d"%((status>> 9) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
......@@ -600,7 +601,9 @@ class X393Sensor(object):
gpio0 = None,
gpio1 = None,
gpio2 = None,
gpio3 = None):
gpio3 = None,
test_patt = None,
test_mode = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -610,8 +613,16 @@ class X393Sensor(object):
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param test_patt - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param test_mode - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient
@return sensor i/o control word
"""
RESET_TEST_OUT = 24
SET_TEST_OUT = 25
SENS_TEST_MODES = 26
SENS_TEST_BITS = 3
SENS_TEST_SET= 29
rslt = 0
if not mrst is None:
rslt |= (3,2)[mrst] << vrlg.SENS_CTRL_MRST
......@@ -627,6 +638,12 @@ class X393Sensor(object):
rslt |= (4 | (gpio2 & 3)) << vrlg.SENS_CTRL_GP2
if not gpio3 is None:
rslt |= (4 | (gpio3 & 3)) << vrlg.SENS_CTRL_GP3
if not test_patt is None:
rslt |= 1 << (RESET_TEST_OUT, SET_TEST_OUT)[test_patt]
if not test_mode is None:
test_mode_masked = test_mode & ((1 << SENS_TEST_BITS) - 1)
rslt |= test_mode_masked << SENS_TEST_MODES
rslt |= 1 << SENS_TEST_SET
return rslt
def func_sensor_uart_ctl_boson (self,
......@@ -1312,7 +1329,9 @@ class X393Sensor(object):
gpio0 = None,
gpio1 = None,
gpio2 = None,
gpio3 = None):
gpio3 = None,
test_patt = None,
test_mode = None):
"""
Set sensor I/O controls, including I/O signals
@param num_sensor - sensor port number (0..3)
......@@ -1323,6 +1342,9 @@ class X393Sensor(object):
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param test_patt - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param test_mode - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1334,7 +1356,9 @@ class X393Sensor(object):
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3)
gpio3 = gpio3,
test_patt = test_patt,
test_mode = test_mode)
return
except:
pass
......@@ -1347,7 +1371,9 @@ class X393Sensor(object):
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3)
gpio3 = gpio3,
test_patt = test_patt,
test_mode = test_mode)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
......@@ -1396,7 +1422,7 @@ class X393Sensor(object):
num_sensor,
uart_tx_byte):
"""
Write byte tio the sensor UART transmit FIFO
Write byte to the sensor UART transmit FIFO
@param num_sensor - sensor port number (0..3)
@param uart_tx_byte - Byte to write to FIFO
"""
......@@ -1480,6 +1506,40 @@ class X393Sensor(object):
pass
if not mmcm_phase is None:
self.x393_axi_tasks.write_control_register(reg_addr + 3, mmcm_phase & 0xff)
def set_sensor_io_dly_boson (self,
num_sensor,
mmcm_phase = None, #24 steps in 3ns period
lane0_dly = None,
lane1_dly = None,
lane2_dly = None):
"""
Set sensor port input delays and mmcm phase
@param num_sensor - sensor port number (0..3) or all, 'A'
@param mmcm_phase - MMCM clock phase
@param lane0_dly - delay in the lane0 (3 LSB are not used) // All 4 lane delays should be set simultaneously
@param lane1_dly - delay in the lane1 (3 LSB are not used)
@param lane2_dly - delay in the lane2 (3 LSB are not used)
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_io_dly_boson (num_sensor = num_sensor,
mmcm_phase = mmcm_phase,
lane0_dly = lane0_dly,
lane1_dly = lane1_dly,
lane2_dly = lane2_dly)
return
except:
pass
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS
try: # if any delay is None - do not set
dlys=(lane0_dly & 0xff) | ((lane1_dly & 0xff) << 8) | ((lane2_dly & 0xff) << 16)
self.x393_axi_tasks.write_control_register(reg_addr + 2, dlys)
except:
return # do not apply delays
if not mmcm_phase is None:
self.x393_axi_tasks.write_control_register(reg_addr + 3, mmcm_phase & 0xff)
self.set_sensor_io_ctl_boson (num_sensor, set_delays = True)
def set_sensor_hispi_lanes(self,
num_sensor,
......
sensor/boson_uart.v
View file @ a6df0611
......@@ -42,7 +42,9 @@
module boson_uart #(
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
parameter RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
......@@ -78,7 +80,7 @@ module boson_uart #(
reg [1:0] rx_stb_r;
reg tx_busy_r;
reg tx_rq; // request to transmit
reg mrst_d;
// reg mrst_d;
reg tx_start;
reg tx_continue;
wire debounced;
......@@ -88,7 +90,9 @@ module boson_uart #(
wire rx_errw;
wire start_bit_rx;
wire stop_bit_rx;
wire stop_bit_tx;
/// wire stop_bit_tx;
wire stop_bit_last_tx;
wire stop_bits_tx; // never used?
wire tx_startw; // start next 10-bit transmission
wire tx_continuew;
assign debounced = (debounce_cntr == 0);
......@@ -97,15 +101,21 @@ module boson_uart #(
assign mark = &rx_sr & rxd_r; // all ones
assign start_bit_rx = (rx_bcntr == 0);
assign stop_bit_rx = (rx_bcntr == 9);
assign stop_bit_tx = (tx_bcntr == 9);
assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
/// assign tx_continuew = tx_bit[0] && !stop_bit_tx ;
assign tx_continuew = tx_bit[0] && !stop_bit_tx && tx_busy_r;
/// assign stop_bit_tx = (tx_bcntr == 9);
assign stop_bit_last_tx = (tx_bcntr == (8 + UART_STOP_BITS));
assign stop_bits_tx = tx_bcntr[3] && |tx_bcntr[2:0]; // >=9
/// assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
assign rx_errw = !rxd_r && stop_bit_rx; // 0 at stop (start may be delayed)
/// assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
/// assign tx_continuew = tx_bit[0] && !stop_bit_tx && tx_busy_r;
assign tx_startw = tx_bit[0] && stop_bit_last_tx && tx_rq;
// assign tx_continuew = tx_bit[0] && !stop_bits_tx && tx_busy_r; // verify
assign tx_continuew = tx_bit[0] && !stop_bit_last_tx && tx_busy_r; // verify
assign rx_byte = rx_sr[8:1];
assign rx_stb = rx_stb_r[1];
// assign tx_rdy = tx_rq;
assign tx_rdy = !tx_rq;
assign tx_busy = tx_busy_r || tx_rq; // !tx_rq;
assign txd = tx_sr[0];
......@@ -125,10 +135,12 @@ module boson_uart #(
rx_bit <= rx_bitw;
if (mrst) rx_sr <= 10'h3ff; // inactive "1"
else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RX232
else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RS232
if (mark || rx_err || (rx_bit && stop_bit_rx)) rx_bcntr <= 0;
else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
/// else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
// will wait at rx_bcntr == 0
else if (rx_bit && (!start_bit_rx || !rxd_r)) rx_bcntr <= rx_bcntr + 1;
if (mark) rx_err <= 0;
else if (rx_bit && rx_errw) rx_err <= 1;
......@@ -139,28 +151,27 @@ module boson_uart #(
always @(posedge mclk) begin
if (tx_stb) tx_r <= tx_byte;
mrst_d <= mrst;
/// mrst_d <= mrst;
tx_bit <= {tx_bit[0],tx_bitw};
if (mrst) clk_div_cntr_tx <= CLK_DIV - 3;
else if (tx_bit[1]) clk_div_cntr_tx <= CLK_DIV - 3;
else clk_div_cntr_tx <= clk_div_cntr_tx - 1;
// if (mrst) tx_sr <= 10'h3ff;
if (mrst || !tx_busy) tx_sr <= 10'h3ff;
else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
/// else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
else if (tx_bit[1] && stop_bit_last_tx) tx_busy_r <= 0;
if (mrst) tx_rq <= 0;
/// else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
else if (tx_stb) tx_rq <= 1; // 0;
else if (tx_start) tx_rq <= 0; // 1;
// if (mrst) tx_bcntr <= 0;
if (mrst || !tx_busy) tx_bcntr <= 9; // stop bit ?
/// if (mrst || !tx_busy) tx_bcntr <= 9; // stop bit ? //UART_STOP_BITS
if (mrst || !tx_busy) tx_bcntr <= 8 + UART_STOP_BITS;
else if (tx_start) tx_bcntr <= 0;
else if (tx_continue) tx_bcntr <= tx_bcntr + 1;
......
sensor/sens_103993.v
View file @ a6df0611
......@@ -130,6 +130,7 @@ module sens_103993 #(
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1,
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
output pclk, // global clock input, pixel rate (220MHz for MT9F002)
......@@ -179,36 +180,46 @@ module sens_103993 #(
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst
);
// wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
// wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
localparam RESET_TEST_OUT = 24;
localparam SET_TEST_OUT = 25;
localparam SENS_TEST_MODES = 26;
localparam SENS_TEST_BITS = 3;
localparam SENS_TEST_SET= 29;
localparam SENS_WIDTH_BITS = 10;
localparam SENS_HEIGHT_BITS = 10;
localparam SENS_WIDTH_INC = 3;
localparam SENS_HEIGHT_INC = 3;
wire dvalid_w;
wire [15:0] pxd_w;
wire [15:0] pxd_test;
reg [SENS_WIDTH_BITS-1:0] col_num_test;
reg [SENS_HEIGHT_BITS-1:0] row_num_test;
reg [7:0] col_num8_test;
reg [7:0] row_num8_test;
reg [3:0] col_div_test;
reg [3:0] row_div_test;
reg dvalid_r;
// wire vact_w;
// wire dvalid_w;
reg [31:0] data_r;
// reg [3:0] set_idelay;
// reg set_lanes_map; // set sequence of lanes im the composite pixel line
// reg set_fifo_dly; // set how long to wait after strating to fill FIFOs (in items) ~= 1/2 2^FIFO_DEPTH
reg set_uart_ctrl; // set UART control bits (both TX and receive)
reg set_uart_tx; // set UART tx data (full, starting witgh channel number = 0)
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
reg set_status_r;
// reg set_jtag_r;
wire perr; // parity error from deserializer
wire ps_rdy;
wire [7:0] ps_out;
// wire locked_pxd_mmcm;
wire [7:0] test_out; // should be 0x17 from unused serial signals
wire clkin_pxd_stopped_mmcm;
wire clkfb_pxd_stopped_mmcm;
......@@ -253,22 +264,27 @@ module sens_103993 #(
wire [3:0] gp;
wire [2:0] dummy; // to keep iostandard of unused pins in a bank
wire gp_comb = (^gp[3:0]) ^ (^dummy);
assign status = {recv_data[7:0], // [23:16]
reg test_patt;
reg [7:0] perr_cntr;
reg [SENS_TEST_BITS-1:0] test_mode;
//perr
assign status = {test_patt? perr_cntr[7:0]: recv_data[7:0], // [23:16]
recv_eop, // 15
recv_pav, // 14
imrst ? hact_alive : gp_comb,// 13 using gp_comb to keep
imrst ? hact_alive : gp_comb, // 13 using gp_comb to keep
locked_pclk, // 12 // wait after mrst
clkin_pxd_stopped_mmcm, // 11
clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
ps_rdy, // 8
ps_out[7:0], // [7:0]
test_patt? perr : ps_rdy, // 8
test_patt? test_out[7:0]:ps_out[7:0],// [7:0]
xmit_busy, // 25
senspgmin}; // 24
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
assign dvalid = dvalid_w;
assign pxd = (|test_mode)? pxd_test : pxd_w;
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
......@@ -279,6 +295,9 @@ module sens_103993 #(
always @(posedge pclk) begin
dvalid_r <= dvalid_w;
if (prst) perr_cntr <= 0;
if (perr) perr_cntr <= perr_cntr + 1;
end
//dvalid_r
......@@ -326,6 +345,12 @@ module sens_103993 #(
if (mrst) gp_r[7:6] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP3 + 2]) gp_r[7:6] <= data_r[SENS_CTRL_GP3+:2];
if (mrst) test_patt <= 0;
else if (set_ctrl_r && data_r[RESET_TEST_OUT]) test_patt <= 0;
else if (set_ctrl_r && data_r[SET_TEST_OUT]) test_patt <= 1;
if (mrst) test_mode <= 0;
else if (set_ctrl_r && data_r[SENS_TEST_SET]) test_mode <= data_r[SENS_TEST_MODES+:SENS_TEST_BITS];
if (mrst) extif_en <= 0;
......@@ -389,6 +414,7 @@ module sens_103993 #(
.INITIAL_CRC16 (INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (CLK_DIV), // 217),
.RX_DEBOUNCE (RX_DEBOUNCE), // 60),
.UART_STOP_BITS (UART_STOP_BITS), // 1)
.EXTIF_MODE (EXTIF_MODE) // 1)
) serial_103993_i (
.mrst (mrst), // input
......@@ -451,13 +477,12 @@ module sens_103993 #(
.sns_dn (sns_dn[2:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd), // output[15:0]
.pxd_out (pxd_w), // output[15:0]
.vsync (vsync), // output
.hsync (hsync), // output
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
// .dly_data (data_r[23:0]), // input[23:0]
.dly_data (data_r[23:0]), // input[23:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.ld_idelay (ld_idelay), // input
......@@ -466,11 +491,36 @@ module sens_103993 #(
.perr (perr), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.test_out (test_out), // output[7:0] // should be 0x17
.locked_pxd_mmcm (locked_pclk), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
// implement test gradient
assign pxd_test =
(test_mode == 1) ? {row_num8_test[7:0], col_num8_test[7:0]}:
((test_mode == 2) ? {6'b0,col_num_test[9:0]}:
{6'b0,row_num_test[9:0]});
always @(posedge pclk) begin
if (!dvalid_w) col_div_test <= SENS_WIDTH_INC-1;
else col_div_test <= (col_div_test == 0)? (SENS_WIDTH_INC-1) : (col_div_test - 1);
if (!dvalid_w) col_num8_test <= 0;
else if (col_div_test == 0) col_num8_test <= col_num8_test + 1;
if (!dvalid_w) col_num_test <= 0;
else col_num_test <= col_num_test + 1;
if (!vsync) row_div_test <= SENS_HEIGHT_INC-1;
else if (!dvalid_w && dvalid_r) row_div_test <= (row_div_test == 0)? (SENS_HEIGHT_INC-1) : (row_div_test - 1);
if (!vsync) row_num8_test <= 0;
else if (!dvalid_w && dvalid_r && (row_div_test == 0)) row_num8_test <= row_num8_test + 1;
if (!vsync) row_num_test <= 0;
else if (!dvalid_w && dvalid_r) row_num_test <= row_num_test + 1;
end
mpullup i_senspgm_pullup (sns_pgm);
iobuf #(
......
sensor/sens_103993_clock.v
View file @ a6df0611
......@@ -91,8 +91,10 @@ module sens_103993_clock#(
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
localparam BUF_CLK_FB = BUF_IPCLK2X;
wire pclk_pre;
wire ipclk2x_pre; // output
wire clk_fb_pre;
wire clk_fb;
wire prst = mrst;
wire clk_in;
......@@ -145,9 +147,12 @@ module sens_103993_clock#(
) clk_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_phase),
.ld (load),
.delay (phase[4:0]),
// .set (set_phase),
// .ld (load),
/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?)
.set (load),
.ld (set_phase),
.delay (phase[7:3]), // skip lsb, not MSB
.data_in (clk_int),
.data_out (clk_in)
);
......@@ -186,6 +191,7 @@ module sens_103993_clock#(
.clkin1 (clk_in), // input 27MHz
.clkin2 (1'b0), // input
.sel_clk2 (1'b0), // input
// .clkfbin (pclk), // clk_fb), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
......@@ -207,7 +213,7 @@ module sens_103993_clock#(
.clkout1b(), // output
.clkout2b(), // output
.clkout3b(), // output
.clkfbout (clk_fb), // output
.clkfbout (clk_fb_pre), // output
.clkfboutb(), // output
.locked (locked_pxd_mmcm),
.clkin_stopped (clkin_pxd_stopped_mmcm), // output
......@@ -229,6 +235,7 @@ module sens_103993_clock#(
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin (clk_in), // input
// .clkfbin (pclk), // clk_fb), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
......@@ -238,7 +245,7 @@ module sens_103993_clock#(
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout (clk_fb), // output
.clkfbout (clk_fb_pre), // output
.locked (locked_pxd_mmcm)
// output
);
......@@ -249,6 +256,17 @@ module sens_103993_clock#(
end
endgenerate
generate
if (BUF_CLK_FB == "BUFG") BUFG clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else if (BUF_CLK_FB == "BUFH") BUFH clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else if (BUF_CLK_FB == "BUFR") BUFR clk2x_i (.O(clk_fb), .I(clk_fb_pre), .CE(1'b1), .CLR(prst));
else if (BUF_CLK_FB == "BUFMR") BUFMR clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else if (BUF_CLK_FB == "BUFIO") BUFIO clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else assign clk_fb = clk_fb_pre;
endgenerate
generate
if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
......
sensor/sens_103993_din.v
View file @ a6df0611
......@@ -112,8 +112,11 @@ module sens_103993_din #(
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_idelay[i]),
.ld (ld_idelay),
//// .set (set_idelay[i]),
//// .ld (ld_idelay),
/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?)
.set (ld_idelay),
.ld (set_idelay[i]),
.delay (dly_data[3 + 8*i +: 5]),
.data_in (din[i]),
.data_out (din_dly[i])
......
sensor/sens_103993_l3.v
View file @ a6df0611
......@@ -96,6 +96,7 @@ module sens_103993_l3#(
output perr, // parity error
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output [7:0] test_out,
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
......@@ -114,6 +115,7 @@ module sens_103993_l3#(
assign hsync = hsync_r;
assign dvalid = dvalid_r;
assign perr = perr_r;
assign test_out = sns_d[29:22];
sens_103993_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -186,8 +188,10 @@ module sens_103993_l3#(
.ld_idelay (ld_idelay), // input
.pclk (pclk), // input
.ipclk2x (ipclk2x), // input
.din_p (sns_dp), // input[2:0]
.din_n (sns_dn), // input[2:0]
// .din_p (sns_dp), // input[2:0]
// .din_n (sns_dn), // input[2:0]
.din_p ({sns_dp[0],sns_dp[1],sns_dp[2]}), // input[2:0]
.din_n ({sns_dn[0],sns_dn[1],sns_dn[2]}), // input[2:0]
.dout (sns_d) // output[29:0]
);
always @(posedge pclk) begin
......@@ -195,8 +199,9 @@ module sens_103993_l3#(
vsync_r <= sns_d[1]; // input - active high
hsync_r <= sns_d[11]; // input - active high
dvalid_r <= sns_d[21]; // input - active hight
cp_r <= sns_d [0];
perr_r <= ~ cp_r ^ (^pxd_out_r) ^ vsync_r ^ hsync_r ^ dvalid_r;
cp_r <= sns_d[0];
// perr_r <= ~ cp_r ^ (^pxd_out_r) ^ vsync_r ^ hsync_r ^ dvalid_r;
perr_r <= ~ (^sns_d[9:0]) ^ (^sns_d[19:11]) ^ (^sns_d[29:21]); //DS: XOR of all selected bits result in odd parity
end
endmodule
......
sensor/sensor_channel.v
View file @ a6df0611
......@@ -445,6 +445,7 @@ module sensor_channel#(
parameter UART_INITIAL_CRC16 = 16'h1d0f,
parameter UART_CLK_DIV = 217,
parameter UART_RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1,
parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
`endif
......@@ -1243,6 +1244,7 @@ module sensor_channel#(
.INITIAL_CRC16 (UART_INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (UART_CLK_DIV), // 217),
.RX_DEBOUNCE (UART_RX_DEBOUNCE), // 60),
.UART_STOP_BITS (UART_STOP_BITS), //
.EXTIF_MODE (UART_EXTIF_MODE) // 1)
) sens_103993_i (
......
sensor/sensors393.v
View file @ a6df0611
......@@ -465,6 +465,7 @@ module sensors393 #(
parameter UART_INITIAL_CRC16 = 16'h1d0f,
parameter UART_CLK_DIV = 217,
parameter UART_RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1,
parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
`endif
......@@ -982,6 +983,7 @@ module sensors393 #(
.UART_INITIAL_CRC16 (UART_INITIAL_CRC16), // 16'h1d0f),
.UART_CLK_DIV (UART_CLK_DIV), // 217),
.UART_RX_DEBOUNCE (UART_RX_DEBOUNCE), // 60),
.UART_STOP_BITS (UART_STOP_BITS), // 1)
.UART_EXTIF_MODE (UART_EXTIF_MODE), // 1)
`endif
......
sensor/serial_103993.v
View file @ a6df0611
......@@ -48,6 +48,7 @@ module serial_103993#(
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1,
parameter EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
parameter RECV_CNTR_WIDTH = 8 // received packet counter width
)(
......@@ -237,7 +238,8 @@ module serial_103993#(
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE), // 'h91),
.INITIAL_CRC16 (INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (CLK_DIV), // 217),
.RX_DEBOUNCE (RX_DEBOUNCE) // 60)
.RX_DEBOUNCE (RX_DEBOUNCE), // 60)
.UART_STOP_BITS (UART_STOP_BITS) // 1)
) serial_fslp_i (
.mrst (mrst), // input
.mclk (mclk), // input
......
sensor/serial_fslp.v
View file @ a6df0611
......@@ -48,8 +48,8 @@ module serial_fslp #(
parameter INITIAL_CRC16 = 16'h1d0f,
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
parameter RX_DEBOUNCE = 60,
parameter UART_STOP_BITS = 1
)(
input mrst, // @posedge mclk, sync reset
......@@ -87,7 +87,8 @@ module serial_fslp #(
boson_uart #(
.CLK_DIV (CLK_DIV),
.RX_DEBOUNCE (RX_DEBOUNCE)
.RX_DEBOUNCE (RX_DEBOUNCE),
.UART_STOP_BITS (UART_STOP_BITS)
) boson_uart_i (
.mrst (mrst), // input
.mclk (mclk), // input
......
simulation_modules/simul_103993_serializer.v
View file @ a6df0611
......@@ -84,8 +84,13 @@ module simul_103993_serializer#(
reg [1:0] clk_r;
reg set_sr;
wire cp = (^red) ^ (^green) ^ (^blue) ^ vs ^ hs ^ de;
assign dp = {sr_blue[9],sr_green[9], sr_red[9]};
assign dn = ~{sr_blue[9],sr_green[9], sr_red[9]};
// PCB is routed swapping serial outputs
// assign dp = {sr_blue[9],sr_green[9], sr_red[9]};
// assign dn = ~{sr_blue[9],sr_green[9], sr_red[9]};
assign dp = {sr_red[9],sr_green[9], sr_blue[9]};
assign dn = ~{sr_red[9],sr_green[9], sr_blue[9]};
assign clkp = sr_clk [9];
assign clkn = ~sr_clk [9];
always @ (posedge pclk) begin
......
simulation_modules/simul_boson640.v
View file @ a6df0611
......@@ -49,9 +49,10 @@ module simul_boson640#(
parameter FP = 52, // FP_BP = 52+50
parameter VSW = 87 // with telemetry, in eows
)(
input mrst,// active low
inout mrst,// active low
input single,
input ext_sync,
input bad_frame_end, // just to introduce a bad_frame
output [15:0] pxd,
output pclk,
output dvalid,
......@@ -107,6 +108,12 @@ module simul_boson640#(
assign pxd = pxd_r;
assign vsync = frame_state != FSTATE_VSYNC; // active low
assign hsync = line_state != LSTATE_HS; // active low
wire mrst_w;
pullup (mrst_w);
buf (weak0,weak1) #(100,100) (mrst,mrst_w);
initial begin
$readmemh({`ROOTPATH,DATA_FILE},sensor_data);
end
......@@ -121,7 +128,7 @@ module simul_boson640#(
// frame_state_d <=frame_state;
if (!mrst) begin
if (!mrst || bad_frame_end) begin
frame_state <= FSTATE_IDLE;
end else begin
case (frame_state)
......@@ -139,7 +146,8 @@ module simul_boson640#(
line_cntr <= line_cntr - 1;
end
end
FSTATE_OUT: if (last_in_line) begin
FSTATE_OUT:
if (last_in_line) begin
if (line_cntr == 0) begin
frame_state <= (!single | (ext_sync && !ext_sync_d)) ? FSTATE_VSYNC : FSTATE_IDLE;
line_cntr <= VSW - 1;
......
wrap/idelay_nofine.v
View file @ a6df0611
......@@ -47,8 +47,8 @@ module idelay_nofine
) (
input clk,
input rst,
input set,
input ld,
input set, // apply pipeline register to delay
input ld, // load pipeline register
input [4:0] delay,
input data_in,
output data_out
......
x393.v
View file @ a6df0611
......@@ -2091,6 +2091,7 @@ assign axi_grst = axi_rst_pre;
.UART_CLK_DIV (UART_CLK_DIV), // 217),
.UART_RX_DEBOUNCE (UART_RX_DEBOUNCE), // 60),
.UART_EXTIF_MODE (UART_EXTIF_MODE), // 1)
.UART_STOP_BITS (UART_STOP_BITS),
`endif
`ifdef DEBUG_RING
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
......
x393_boson.bit
View file @ a6df0611
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