got images from Boson640 (a6df0611) · Commits · Elphel / x393

cocotb/x393_dut.v

+15 −2

Original line number	Diff line number	Diff line
		@@ -1949,7 +1949,8 @@ simul_axi_hp_wr #(


		`elsif BOSON
		wire boson_single = 1;
		reg boson_single = 1;
		reg [3:0] boson_restart = 0; // extra reset to break the frame
		wire [BOSON_OUT_BITS-1:0] boson_pxd1;
		wire [BOSON_OUT_BITS-1:0] boson_pxd2;
		wire [BOSON_OUT_BITS-1:0] boson_pxd3;
		@@ -1971,7 +1972,15 @@ simul_axi_hp_wr #(
		wire boson_hsync3;
		wire boson_hsync4;


		// delay start of the sensor video (disable in external sync mode)
		initial begin
		#100000;
		boson_single = 0;
		#100000;
		boson_restart = 4'b0101; // only 2 channels restarted
		#1000;
		boson_restart = 0;
		end
		simul_boson640 #(
		.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
		.WIDTH (BOSON_WIDTH), // 160), 640),
		@@ -1986,6 +1995,7 @@ simul_axi_hp_wr #(
		.mrst (sns1_dp[7]), // input
		.single (boson_single), // input 1'b0), //
		.ext_sync (sns1_ctl), // input
		.bad_frame_end (boson_restart[0]), // input - just to introduce a bad_frame
		.pxd (boson_pxd1), // output[15:0]
		.pclk (boson_pclk1), // output
		.dvalid (boson_dvalid1), // output
		@@ -2025,6 +2035,7 @@ simul_axi_hp_wr #(
		.mrst (sns2_dp[7]), // input
		.single (boson_single), // input 1'b0), //
		.ext_sync (sns2_ctl), // input
		.bad_frame_end (boson_restart[1]), // input - just to introduce a bad_frame
		.pxd (boson_pxd2), // output[15:0]
		.pclk (boson_pclk2), // output
		.dvalid (boson_dvalid2), // output
		@@ -2064,6 +2075,7 @@ simul_axi_hp_wr #(
		.mrst (sns3_dp[7]), // input
		.single (boson_single), // input
		.ext_sync (sns3_ctl), // input
		.bad_frame_end (boson_restart[2]), // input - just to introduce a bad_frame
		.pxd (boson_pxd3), // output[15:0]
		.pclk (boson_pclk3), // output
		.dvalid (boson_dvalid3), // output
		@@ -2103,6 +2115,7 @@ simul_axi_hp_wr #(
		.mrst (sns4_dp[7]), // input
		.single (boson_single), // input
		.ext_sync (sns4_ctl), // input
		.bad_frame_end (boson_restart[3]), // input - just to introduce a bad_frame
		.pxd (boson_pxd4), // output[15:0]
		.pclk (boson_pclk4), // output
		.dvalid (boson_dvalid4), // output

fpga_version.vh

+16 −1

Original line number	Diff line number	Diff line
		@@ -35,7 +35,22 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h03930202; // Initial Boson implementation (cheating with 2.5V), open drain for Boson reset
		parameter FPGA_VERSION = 32'h0393020f; // added test mode
		// parameter FPGA_VERSION = 32'h0393020f; // changing MMCM phase -20.0 (use clk_fb) IBUF_LOW_PWR=FALSE
		// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -20.0 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020d; // changing MMCM phase -18.0 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020c; // changing MMCM phase 18.0 (use clk_fb)
		// parameter FPGA_VERSION = 32'h0393020b; // clock/feedback clock
		// parameter FPGA_VERSION = 32'h0393020a; // 2.5, diff-term, no low-power, fixing delays
		// parameter FPGA_VERSION = 32'h03930209; // 2.5, diff-term, no low-power
		// parameter FPGA_VERSION = 32'h03930208; // 1.8V, no diff-term
		// parameter FPGA_VERSION = 32'h03930207; // Debugging 2.5V, diff-term
		// parameter FPGA_VERSION = 32'h03930206; // Debugging
		// parameter FPGA_VERSION = 32'h03930205; // Fixing serial pairs order for 103993
		// parameter FPGA_VERSION = 32'h03930204; // Testing
		// parameter FPGA_VERSION = 32'h03930203; // Fixing serial receive with dual stop bits
		// parameter FPGA_VERSION = 32'h03930202; // Initial Boson implementation (cheating with 2.5V), open drain for Boson reset
		// parameter FPGA_VERSION = 32'h03930201; // Initial Boson implementation (cheating with 2.5V - as with HISPI)
		// parameter FPGA_VERSION = 32'h03930200; // Initial Boson implementation (1.8V)
		//BOSON

includes/x393_parameters.vh

+14 −7

Original line number	Diff line number	Diff line
		@@ -678,16 +678,18 @@
		`ifdef SIMULATION
		parameter UART_CLK_DIV = 22,
		parameter UART_RX_DEBOUNCE = 6,
		parameter UART_STOP_BITS = 2, // for testing, maybe change later back to 1
		`else
		parameter UART_CLK_DIV = 217,
		parameter UART_RX_DEBOUNCE = 60,
		parameter UART_STOP_BITS = 1,
		`endif
		parameter UART_EXTIF_MODE = 1, // 1,2 or 3 if there are several different extif
		// endof for BOSON:

		// parameters for the sensor-synchronous clock PLL
		// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
		`define TWEAKING_IOSTANDARD
		//`define TWEAKING_IOSTANDARD 1
		`ifdef HISPI
		parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
		@@ -704,7 +706,8 @@
		`elsif BOSON
		parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
		parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
		parameter CLKFBOUT_PHASE_SENSOR = -19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,
		`ifdef TWEAKING_IOSTANDARD
		@@ -790,7 +793,11 @@
		parameter HISPI_CAPACITANCE = "DONT_CARE",
		parameter HISPI_DQS_BIAS = "TRUE",
		parameter HISPI_IBUF_DELAY_VALUE = "0",
		parameter HISPI_IBUF_LOW_PWR = "TRUE",
		`ifdef BOSON
		parameter HISPI_IBUF_LOW_PWR = "FALSE", // "TRUE",
		`else
		parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
		`endif
		parameter HISPI_IFD_DELAY_VALUE = "AUTO",
		// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
		// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)

py393/x393_sensor.py

+68 −8

Original line number	Diff line number	Diff line
		@@ -185,7 +185,8 @@ class X393Sensor(object):
		address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL))

		def print_status_sensor_io (self,
		num_sensor="All", sensorType = SENSOR_INTERFACE_PARALLEL):
		num_sensor="All",
		sensorType = SENSOR_INTERFACE_PARALLEL):
		"""
		Print sensor_io status word (no sync)
		@param num_sensor - number of the sensor port (0..3)
		@@ -212,7 +213,7 @@ class X393Sensor(object):
		print (" busy = %d"%((status>>25) & 1))
		print (" seq = %d"%((status>>26) & 0x3f))
		elif (sensorType == SENSOR_INTERFACE_BOSON):
		print (" ps_out = %d"%((status>> 0) & 0xff))
		print (" ps_out = 0x%x"%((status>> 0) & 0xff))
		print (" ps_rdy = %d"%((status>> 8) & 1))
		print (" perr = %d"%((status>> 9) & 1))
		print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
		@@ -600,7 +601,9 @@ class X393Sensor(object):
		gpio0 = None,
		gpio1 = None,
		gpio2 = None,
		gpio3 = None):
		gpio3 = None,
		test_patt = None,
		test_mode = None):
		"""
		Combine sensor I/O control parameters into a control word
		@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
		@@ -610,8 +613,16 @@ class X393Sensor(object):
		@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
		@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
		@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
		@param test_patt - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
		@param test_mode - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient
		@return sensor i/o control word
		"""
		RESET_TEST_OUT = 24
		SET_TEST_OUT = 25
		SENS_TEST_MODES = 26
		SENS_TEST_BITS = 3
		SENS_TEST_SET= 29

		rslt = 0
		if not mrst is None:
		rslt \|= (3,2)[mrst] << vrlg.SENS_CTRL_MRST
		@@ -627,6 +638,12 @@ class X393Sensor(object):
		rslt \|= (4 \| (gpio2 & 3)) << vrlg.SENS_CTRL_GP2
		if not gpio3 is None:
		rslt \|= (4 \| (gpio3 & 3)) << vrlg.SENS_CTRL_GP3
		if not test_patt is None:
		rslt \|= 1 << (RESET_TEST_OUT, SET_TEST_OUT)[test_patt]
		if not test_mode is None:
		test_mode_masked = test_mode & ((1 << SENS_TEST_BITS) - 1)
		rslt \|= test_mode_masked << SENS_TEST_MODES
		rslt \|= 1 << SENS_TEST_SET
		return rslt

		def func_sensor_uart_ctl_boson (self,
		@@ -1312,7 +1329,9 @@ class X393Sensor(object):
		gpio0 = None,
		gpio1 = None,
		gpio2 = None,
		gpio3 = None):
		gpio3 = None,
		test_patt = None,
		test_mode = None):
		"""
		Set sensor I/O controls, including I/O signals
		@param num_sensor - sensor port number (0..3)
		@@ -1323,6 +1342,9 @@ class X393Sensor(object):
		@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
		@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
		@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
		@param test_patt - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
		@param test_mode - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient

		"""
		try:
		if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
		@@ -1334,7 +1356,9 @@ class X393Sensor(object):
		gpio0 = gpio0,
		gpio1 = gpio1,
		gpio2 = gpio2,
		gpio3 = gpio3)
		gpio3 = gpio3,
		test_patt = test_patt,
		test_mode = test_mode)
		return
		except:
		pass
		@@ -1347,7 +1371,9 @@ class X393Sensor(object):
		gpio0 = gpio0,
		gpio1 = gpio1,
		gpio2 = gpio2,
		gpio3 = gpio3)
		gpio3 = gpio3,
		test_patt = test_patt,
		test_mode = test_mode)

		reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
		self.x393_axi_tasks.write_control_register(reg_addr, data)
		@@ -1396,7 +1422,7 @@ class X393Sensor(object):
		num_sensor,
		uart_tx_byte):
		"""
		Write byte tio the sensor UART transmit FIFO
		Write byte to the sensor UART transmit FIFO
		@param num_sensor - sensor port number (0..3)
		@param uart_tx_byte - Byte to write to FIFO
		"""
		@@ -1480,6 +1506,40 @@ class X393Sensor(object):
		pass
		if not mmcm_phase is None:
		self.x393_axi_tasks.write_control_register(reg_addr + 3, mmcm_phase & 0xff)
		def set_sensor_io_dly_boson (self,
		num_sensor,
		mmcm_phase = None, #24 steps in 3ns period
		lane0_dly = None,
		lane1_dly = None,
		lane2_dly = None):
		"""
		Set sensor port input delays and mmcm phase
		@param num_sensor - sensor port number (0..3) or all, 'A'
		@param mmcm_phase - MMCM clock phase
		@param lane0_dly - delay in the lane0 (3 LSB are not used) // All 4 lane delays should be set simultaneously
		@param lane1_dly - delay in the lane1 (3 LSB are not used)
		@param lane2_dly - delay in the lane2 (3 LSB are not used)
		"""
		try:
		if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
		for num_sensor in range(4):
		self.set_sensor_io_dly_boson (num_sensor = num_sensor,
		mmcm_phase = mmcm_phase,
		lane0_dly = lane0_dly,
		lane1_dly = lane1_dly,
		lane2_dly = lane2_dly)
		return
		except:
		pass
		reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS
		try: # if any delay is None - do not set
		dlys=(lane0_dly & 0xff) \| ((lane1_dly & 0xff) << 8) \| ((lane2_dly & 0xff) << 16)
		self.x393_axi_tasks.write_control_register(reg_addr + 2, dlys)
		except:
		return # do not apply delays
		if not mmcm_phase is None:
		self.x393_axi_tasks.write_control_register(reg_addr + 3, mmcm_phase & 0xff)
		self.set_sensor_io_ctl_boson (num_sensor, set_delays = True)

		def set_sensor_hispi_lanes(self,
		num_sensor,

sensor/boson_uart.v

+31 −20

Original line number	Diff line number	Diff line
		@@ -42,7 +42,9 @@
		module boson_uart #(
		// parameter BOSON_BAUD = 921600,
		parameter CLK_DIV = 217,
		parameter RX_DEBOUNCE = 60
		parameter RX_DEBOUNCE = 60,
		parameter UART_STOP_BITS = 1

		)(
		input mrst, // @posedge mclk, sync reset
		input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
		@@ -78,7 +80,7 @@ module boson_uart #(
		reg [1:0] rx_stb_r;
		reg tx_busy_r;
		reg tx_rq; // request to transmit
		reg mrst_d;
		// reg mrst_d;
		reg tx_start;
		reg tx_continue;
		wire debounced;
		@@ -88,7 +90,9 @@ module boson_uart #(
		wire rx_errw;
		wire start_bit_rx;
		wire stop_bit_rx;
		wire stop_bit_tx;
		/// wire stop_bit_tx;
		wire stop_bit_last_tx;
		wire stop_bits_tx; // never used?
		wire tx_startw; // start next 10-bit transmission
		wire tx_continuew;
		assign debounced = (debounce_cntr == 0);
		@@ -97,15 +101,21 @@ module boson_uart #(
		assign mark = &rx_sr & rxd_r; // all ones
		assign start_bit_rx = (rx_bcntr == 0);
		assign stop_bit_rx = (rx_bcntr == 9);
		assign stop_bit_tx = (tx_bcntr == 9);
		assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
		assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
		/// assign tx_continuew = tx_bit[0] && !stop_bit_tx ;
		assign tx_continuew = tx_bit[0] && !stop_bit_tx && tx_busy_r;
		/// assign stop_bit_tx = (tx_bcntr == 9);
		assign stop_bit_last_tx = (tx_bcntr == (8 + UART_STOP_BITS));
		assign stop_bits_tx = tx_bcntr[3] && \|tx_bcntr[2:0]; // >=9
		/// assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
		assign rx_errw = !rxd_r && stop_bit_rx; // 0 at stop (start may be delayed)
		/// assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
		/// assign tx_continuew = tx_bit[0] && !stop_bit_tx && tx_busy_r;

		assign tx_startw = tx_bit[0] && stop_bit_last_tx && tx_rq;
		// assign tx_continuew = tx_bit[0] && !stop_bits_tx && tx_busy_r; // verify
		assign tx_continuew = tx_bit[0] && !stop_bit_last_tx && tx_busy_r; // verify


		assign rx_byte = rx_sr[8:1];
		assign rx_stb = rx_stb_r[1];
		// assign tx_rdy = tx_rq;
		assign tx_rdy = !tx_rq;
		assign tx_busy = tx_busy_r \|\| tx_rq; // !tx_rq;
		assign txd = tx_sr[0];
		@@ -125,10 +135,12 @@ module boson_uart #(
		rx_bit <= rx_bitw;

		if (mrst) rx_sr <= 10'h3ff; // inactive "1"
		else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RX232
		else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RS232

		if (mark \|\| rx_err \|\| (rx_bit && stop_bit_rx)) rx_bcntr <= 0;
		else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
		/// else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
		// will wait at rx_bcntr == 0
		else if (rx_bit && (!start_bit_rx \|\| !rxd_r)) rx_bcntr <= rx_bcntr + 1;

		if (mark) rx_err <= 0;
		else if (rx_bit && rx_errw) rx_err <= 1;
		@@ -139,28 +151,27 @@ module boson_uart #(
		always @(posedge mclk) begin
		if (tx_stb) tx_r <= tx_byte;

		mrst_d <= mrst;
		/// mrst_d <= mrst;
		tx_bit <= {tx_bit[0],tx_bitw};
		if (mrst) clk_div_cntr_tx <= CLK_DIV - 3;
		else if (tx_bit[1]) clk_div_cntr_tx <= CLK_DIV - 3;
		else clk_div_cntr_tx <= clk_div_cntr_tx - 1;

		// if (mrst) tx_sr <= 10'h3ff;
		if (mrst \|\| !tx_busy) tx_sr <= 10'h3ff;
		else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
		else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};

		if (mrst) tx_busy_r <= 0;
		else if (tx_start) tx_busy_r <= 1;
		else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
		/// else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
		else if (tx_bit[1] && stop_bit_last_tx) tx_busy_r <= 0;

		if (mrst) tx_rq <= 0;
		/// else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
		else if (tx_stb) tx_rq <= 1; // 0;
		else if (tx_start) tx_rq <= 0; // 1;

		// if (mrst) tx_bcntr <= 0;
		if (mrst \|\| !tx_busy) tx_bcntr <= 9; // stop bit ?
		/// if (mrst \|\| !tx_busy) tx_bcntr <= 9; // stop bit ? //UART_STOP_BITS
		if (mrst \|\| !tx_busy) tx_bcntr <= 8 + UART_STOP_BITS;
		else if (tx_start) tx_bcntr <= 0;
		else if (tx_continue) tx_bcntr <= tx_bcntr + 1;

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