Commit a19b199c authored by Andrey Filippov's avatar Andrey Filippov

re-generated new versions of bitstream files

parent ea4d0389
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true VivadoBitstream_@_force=true
VivadoBitstream_@_rawfile=x393_hispi VivadoBitstream_@_rawfile=x393_parallel
com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@-> com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
...@@ -35,7 +35,9 @@ ...@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2% parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009a; // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)
// parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2%
// parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?% // parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?%
// parameter FPGA_VERSION = 32'h03930097; // serial, trying dct_chen - works // parameter FPGA_VERSION = 32'h03930097; // serial, trying dct_chen - works
// parameter FPGA_VERSION = 32'h03930096; // serial, next (before changing DCT) // parameter FPGA_VERSION = 32'h03930096; // serial, next (before changing DCT)
......
...@@ -46,7 +46,6 @@ ...@@ -46,7 +46,6 @@
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here // Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim `define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
`define DEBUG_COMPRESSOR_SCRAMBLE `define DEBUG_COMPRESSOR_SCRAMBLE
`define DEBUG_DCT1D // undefine after debugging is over `define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT // `define USE_OLD_DCT
...@@ -64,7 +63,7 @@ ...@@ -64,7 +63,7 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/ // `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
// `define USE_XCLK2X // `define USE_XCLK2X
...@@ -100,6 +99,12 @@ ...@@ -100,6 +99,12 @@
`define OPEN_SOURCE_ONLY `define OPEN_SOURCE_ONLY
`endif // CVC `endif // CVC
`ifndef SIMULATION
`undef DEBUG_COMPRESSOR_SCRAMBLE
`undef DEBUG_DCT1D // undefine after debugging is over
`endif
// will not use simultaneous reset in shift registers, just and input data with ~rst // will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1 `define SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch // synthesis does to recognize global clock as G input of the primitive latch
......
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