Commit a06aacce authored by Andrey Filippov's avatar Andrey Filippov
Browse files

added x393_sata project

parent 3dddcdb1

.gitignore

+1 −1
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@@ -15,7 +15,7 @@ x393.prj 
*.pyc

*.pickle

py393/dbg*



debug

includes/x393_cur_params_sim.vh

includes/x393_cur_params_target_*.vh

py393/exp_gpio.py

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+1 −1
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@@ -6,7 +6,7 @@ VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.x 
VivadoSynthesis_122_SkipSnapshotSynth=true

VivadoSynthesis_123_ResetProject=true

VivadoSynthesis_123_SkipSnapshotSynth=true

VivadoSynthesis_124_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->

VivadoSynthesis_124_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->x393_sata/ahci_timing.xdc<-@\#\#@->

VivadoSynthesis_127_verbose=true

VivadoSynthesis_81_parser_mode=1

VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->

.settings/com.elphel.vdt.iverilog.prefs

+1 −1
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@@ -11,7 +11,7 @@ iverilog_104_ExtraFiles=glbl.v<-@\#\#@-> 
iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->

iverilog_105_ExtraFiles=glbl.v<-@\#\#@->

iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->

iverilog_106_IncludeDir=${verilog_project_loc}_sata/x393/includes<-@\#\#@->${verilog_project_loc}_sata/x393/ddr3<-@\#\#@->

iverilog_106_IncludeDir=${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/x393/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata/includes<-@\#\#@->

iverilog_109_ShowNoProblem=true

iverilog_110_ShowNoProblem=true

iverilog_110_ShowWarnings=false

compressor_jp/compressor393.v

+3 −0
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@@ -226,6 +226,7 @@ module compressor393 # ( 
    output                        afi0_wrissuecap1en,

    

    // write address, second channel

    output                        afi1_clk,     // same as hclk if the second channel is used

    output                 [31:0] afi1_awaddr,

    output                        afi1_awvalid,

    input                         afi1_awready, // @SuppressThisWarning VEditor unused - used FIF0 level
@@ -638,6 +639,7 @@ module compressor393 # ( 
                .debug_di     (debug_ring[DEBUG_RING_LENGTH])        // input

`endif         

            );

            assign afi1_clk = hclk;

        end else begin

            cmprs_afi_mux #(

                .CMPRS_AFIMUX_ADDR            (CMPRS_GROUP_ADDR + CMPRS_AFIMUX_RADDR0),
@@ -723,6 +725,7 @@ module compressor393 # ( 
                .debug_di     (debug_ring[5])        // input

`endif         

            );

            assign afi1_clk = hclk;

            assign afi1_awaddr = 0;

            assign afi1_awvalid = 0;

            assign afi1_awid = 0;

system_defines.vh

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@@ -34,6 +34,17 @@ 
  // This file may be used to define same pre-processor macros to be included into each parsed file

`ifndef SYSTEM_DEFINES

  `define SYSTEM_DEFINES

// Parameters from x393_sata project

  `define USE_DRP

  `define ALIGN_CLOCKS

//  `define STRAIGHT_XCLK

  `define USE_DATASCOPE

//  `define DATASCOPE_INCOMING_RAW

  `define PRELOAD_BRAMS

//  `define AHCI_SATA 1

//  `define DEBUG_ELASTIC  

// End of parameters from x393_sata project

  

  `define PRELOAD_BRAMS

  `define DISPLAY_COMPRESSED_DATA  

  // if HISPI is not defined, parallel sensor interface is used for all channels