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Commit 9d60666b authored by Andrey Filippov's avatar Andrey Filippov
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vospi debug, implemented packet synchronization by signature

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cocotb/x393_cocotb_lwir_04.sav
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fpga_version.vh
View file @ 9d60666b
......@@ -35,7 +35,18 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930122; // Added debug output
parameter FPGA_VERSION = 32'h0393012d; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012c; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012b; // debugging
// parameter FPGA_VERSION = 32'h0393012a; // debugging
// parameter FPGA_VERSION = 32'h03930129; // adding synchronization by discard packets
// parameter FPGA_VERSION = 32'h03930128; // output dbg_segment_stb on [7]
// parameter FPGA_VERSION = 32'h03930127; // output vsync_use, reduced sclk to 10MHz
// parameter FPGA_VERSION = 32'h03930126; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930125; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930124; // more hardware debug circuitry
// parameter FPGA_VERSION = 32'h03930123; // Implementing VSYNC/GPIO3 input
// parameter FPGA_VERSION = 32'h03930122; // Added debug output
// parameter FPGA_VERSION = 32'h03930121; // VOSPI setting MOSI to low, according to DS
// parameter FPGA_VERSION = 32'h03930120; // VOSPI
// parameter FPGA_VERSION = 32'h03930108; // parallel - in master branch
......
includes/x393_parameters.vh
View file @ 9d60666b
......@@ -559,13 +559,17 @@
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28,
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -616,6 +620,13 @@
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
`ifdef use200Mhz
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
`else
......@@ -1017,8 +1028,8 @@
parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
`else
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
parameter CLKOUT_DIV_PCLK = 96, // 10MHz // 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 48, // 20 MHz // 24, // 40 MHz
`endif
`else
......
py393/vrlg.py
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py393/x393_export_c.py
View file @ 9d60666b
......@@ -1890,15 +1890,14 @@ class X393ExportC(object):
dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by command bit"))
dw.append(("fake_in", 11, 1,0, "Just to keep hardware"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by the command bit"))
dw.append(("sync_err", 11, 1,0, "At least 1 synchronization error happened since reset by the command bit"))
dw.append(("fake_in", 12, 1,0, "Just to keep hardware"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -2139,15 +2138,19 @@ class X393ExportC(object):
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("reset_err", vrlg.VOSPI_RESET_ERR, 1, 0, "Reset CRC and synchronization error status bits"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("fake", vrlg.VOSPI_FAKE_OUT, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("mosi", vrlg.VOSPI_MOSI, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("vsync_use", vrlg.VOSPI_VSYNC, 1, 0, "Wait for the VSYNC (GPIO3). Should be enabled via i2c"))
dw.append(("vsync_use_set",vrlg.VOSPI_VSYNC+1, 1, 0, "Enable vsync_use set/reset"))
dw.append(("noresync", vrlg.VOSPI_NORESYNC, 1, 0, "Disable re-synchronization by discard packets"))
dw.append(("noresync_set", vrlg.VOSPI_NORESYNC+1, 1, 0, "Enable noresync set/reset"))
dw.append(("dbg_src", vrlg.VOSPI_DBG_SRC, 3, 0, "Hardware debug source:0-running,1-vsync_rdy[0],2-vsync_rdy[1],3-discard_segment,4-in_busy,5-out_busy,6-hact,7-sof"))
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw
def _enc_sensio_jtag(self):
......
py393/x393_sensor.py
View file @ 9d60666b
......@@ -467,8 +467,9 @@ class X393Sensor(object):
gpio1 = None,
gpio2 = None,
gpio3 = None,
fake = None,
mosi = None):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -484,8 +485,16 @@ class X393Sensor(object):
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input
@param fake = Do not use, just for keeping hardware portsNone,
@param mosi = Do not use, just for keeping hardware portsNone,
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0]
2 - vsync_rdy[1]
3 - discard_segment
4 - in_busy
5 - out_busy
6 - hact
7 - sof
@return VOSPI sensor i/o control word
"""
rslt = 0
......@@ -504,7 +513,7 @@ class X393Sensor(object):
if out_single:
rslt |= 1 << vrlg.VOSPI_OUT_EN_SINGL
if reset_crc:
rslt |= 1 << vrlg.VOSPI_RESET_CRC
rslt |= 1 << vrlg.VOSPI_RESET_ERR
if not spi_clk is None:
rslt |= (2,3)[spi_clk] << vrlg.VOSPI_SPI_CLK
if not gpio0 is None:
......@@ -515,10 +524,20 @@ class X393Sensor(object):
rslt |= (gpio2 & 3) << (vrlg.VOSPI_GPIO + 4)
if not gpio3 is None:
rslt |= (gpio3 & 3) << (vrlg.VOSPI_GPIO + 6)
if fake:
rslt |= 1 << vrlg.VOSPI_FAKE_OUT
if fake:
mosi |= 1 << vrlg.VOSPI_MOSI
if not vsync_use is None:
rslt |= (2,3)[vsync_use] << vrlg.VOSPI_VSYNC
if not noresync is None:
rslt |= (2,3)[noresync] << vrlg.VOSPI_NORESYNC
if not dbg_src is None:
rslt |= ((dbg_src & (( 1 << (vrlg.VOSPI_DBG_SRC_BITS - 1)) -1 )) |
(1 << (vrlg.VOSPI_DBG_SRC_BITS - 1))) << vrlg.VOSPI_DBG_SRC
pass
# .VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 26, // source of the debug output
# .VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
return rslt
......@@ -1056,8 +1075,10 @@ class X393Sensor(object):
gpio1 = None,
gpio2 = None,
gpio3 = None,
fake = None,
mosi = None):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -1073,9 +1094,16 @@ class X393Sensor(object):
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input
@param fake = Do not use, just for keeping hardware portsNone,
@param mosi = Do not use, just for keeping hardware portsNone,
@return VOSPI sensor i/o control word
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0]
2 - vsync_rdy[1]
3 - discard_segment
4 - in_busy
5 - out_busy
6 - hact
7 - sof
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1094,8 +1122,9 @@ class X393Sensor(object):
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
fake = fake,
mosi = mosi)
vsync_use = vsync_use,
noresync = noresync,
dbg_src = dbg_src)
return
except:
pass
......@@ -1113,8 +1142,9 @@ class X393Sensor(object):
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
fake = fake,
mosi = mosi)
vsync_use = vsync_use,
noresync = noresync,
dbg_src = dbg_src)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
......
sensor/sens_lepton3.v
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sensor/sensor_channel.v
View file @ 9d60666b
......@@ -157,6 +157,10 @@ module sensor_channel#(
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
`ifdef LWIR
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
`else
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
......@@ -202,7 +206,7 @@ module sensor_channel#(
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
`endif
`endif
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
......@@ -229,6 +233,11 @@ module sensor_channel#(
`ifdef HISPI
`elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
......@@ -242,13 +251,17 @@ module sensor_channel#(
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -259,18 +272,22 @@ module sensor_channel#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7,
`endif
// start with comma!
`ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS25"
`else
// sens_parallel12 other parameters
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
,parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
......@@ -316,6 +333,9 @@ module sensor_channel#(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`endif
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
......@@ -981,10 +1001,13 @@ module sensor_channel#(
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
/*
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_WIDTH (SENSIO_WIDTH),
.SENSIO_DELAYS (SENSIO_DELAYS),
*/
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
/*
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
......@@ -1024,6 +1047,11 @@ module sensor_channel#(
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
*/
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -1037,13 +1065,17 @@ module sensor_channel#(
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // pot used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......
sensor/sensors393.v
View file @ 9d60666b
This diff is collapsed.
sensor/vospi_packet_80.v
View file @ 9d60666b
......@@ -48,11 +48,14 @@ module vospi_packet_80#(
output spi_clken, // enable clock on spi_clk
output spi_cs, // active low
input miso, // input from the sensor
input will_sync, // discard packet detected, sync_end will follow (from resync module)
output [15:0] dout, // 16-bit data received,valid at dv and 15 cycles after
output dv, // data valid strobe
output packet_done, // packet received,
output packet_busy, // packet busy (same as spi_clken, !spi_cs)
output crc_err, // crc error, valid with packet_done
output sync_err, // synchronization error, valid with packet_done
output [15:0] id, // packet ID (0x*f** - invlaid, if packet index = 20, 4 MSb - segment (- 0 invalid)
output packet_invalid, // set early, valid with packet done
output reg id_stb // id, packet invalid are set
......@@ -66,6 +69,7 @@ module vospi_packet_80#(
reg [1:0] cs_r;
wire pre_last_w;
reg last_r;
reg [ 2:0] packet_end;
reg set_id_r;
reg set_crc_r;
......@@ -81,6 +85,11 @@ module vospi_packet_80#(
reg [15:0] id_r;
wire [15:0] dmask;
reg packet_invalid_r;
reg will_sync_d;
wire sync_end; // last bit in a packet (turn off CS/spi_clken) (from resync module)
reg sync_err_r;
assign sync_end = !will_sync && will_sync_d; // trailing edge, so will fire if disabled
assign packet_busy = cs_r[0]; // clk_en_r;
assign spi_clken = cs_r[0]; // clk_en_r;
......@@ -93,29 +102,37 @@ module vospi_packet_80#(
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w);
assign sync_err = packet_end[2] && sync_err_r;
assign dv = dv_r;
assign dout = d_r;
assign packet_invalid = packet_invalid_r;
always @ (posedge clk) begin
if (rst || packet_end[0]) cs_r[0] <= 0;
will_sync_d <= will_sync;
/// if (rst || packet_end[0]) cs_r[0] <= 0;
if (rst || packet_end[0] || sync_end) cs_r[0] <= 0;
else if (start) cs_r[0] <= 1;
cs_r[1] <= cs_r[0];
if (rst || !cs_r[0] || packet_end[0]) bcntr <= 0;
else bcntr <= bcntr + 1;
else bcntr <= bcntr + 1; // keep running even for sync
if (rst || !cs_r[0] || packet_end[0]) lsb_r <= 0;
else lsb_r <= pre_lsb_w;
else lsb_r <= pre_lsb_w; // generate even for sync
copy_word <= !rst && lsb_r;
if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0;
else if (lsb_r) wcntr <= wcntr + 1;
else if (lsb_r) wcntr <= wcntr + 1; // keep running even for sync
if (rst || !cs_r[0] ) packet_end[1:0] <= 0;
else packet_end[1:0] <= {packet_end[0], pre_last_w};
/// else packet_end[1:0] <= {packet_end[0], pre_last_w};
else packet_end[1:0] <= {packet_end[0] | sync_end, pre_last_w & ~will_sync}; // do not generate premature if running sync
if (rst) packet_end[2] <= 0;
else packet_end[2] <= packet_end[1];
......@@ -139,9 +156,17 @@ module vospi_packet_80#(
dv_r <= set_d_r && !(packet_invalid_r && VOSPI_NO_INVALID);
if (rst || start) packet_invalid_r <= 0;
else if (will_sync) packet_invalid_r <= 1; // Will_sync disqualifies even started (erroneously) a good packet
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
last_r <= pre_last_w;
if (rst || start) sync_err_r <= 0;
else if (sync_end && ! last_r) sync_err_r <= 1;
id_stb <= set_id_r;
if (rst || start || packet_done) packet_header <= 2'b11;
else if (copy_word) packet_header <= {packet_header[0], 1'b0};
......
sensor/vospi_segment_61.v
View file @ 9d60666b
......@@ -58,6 +58,9 @@ module vospi_segment_61#(
input [3:0] exp_segment, // expected segment (1,2,3,4)
input segm0_ok, // OK to read segment 0 instead of the current ( exp_segment still has to be 1..4)
input out_en, // enable frame output generation (will finish current frame if disabled, single-pulse
input vsync, // from GPIO[3], 70 usec on, period ~10ms (should be re-sampled to pclk
input vsync_use, // if set - wait for vsync to read a segment
input resync_disable, // disable re-synchronizing packets using discard signature @pclk
// runs a single frame
// SPI signals
output spi_clken, // enable clock on spi_clk
......@@ -67,14 +70,19 @@ module vospi_segment_61#(
output in_busy, // waiting for or receiving a segment
output out_busy,
output reg segment_done, // finished receiving segment (good or bad). next after busy off
output discard_segment, // segment was disc arded
output discard_segment, // segment was discarded
output [15:0] dout, // 16-bit data received
output hact, // data valid
output sof, // start of frame
output eof, // end of frame
output crc_err, // crc error happened for any packet (valid at eos)
output sync_err, // sync error happened for any packet (valid at eos)
output [3:0] id, // segment number (valid at eos)
output dbg_running // debug output for segment_running
output dbg_running, // debug output for segment_running
output [1:0] dbg_vsync_rdy,
output dbg_segment_stb,
output dbg_will_sync,
output [ 4:0] dbg_state
);
localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
......@@ -91,7 +99,7 @@ module vospi_segment_61#(
reg [ 7:0] segment_start_packet; // full packet number in a fragment for the start of the segment
reg [ 7:0] full_packet; // current full packet number in a fragment
reg [ 7:0] full_packet_verified; // next packet verified (will not be discarded later)
reg full_packet_frame; // lsb of the input frame // not needed?
/// reg full_packet_frame; // lsb of the input frame // not needed?
reg discard_set; // start discard_segment_r
wire segment_good_w; // recognized expected segment, OK to read FIFO
reg segment_good; // recognized expected segment, OK to read FIFO
......@@ -111,6 +119,7 @@ module vospi_segment_61#(
wire segment_stb;
// reg crc_err_r;
wire packet_crc_err;
wire packet_sync_err;
reg packet_start;
wire we; // write data to buffer
wire segment_done_w;
......@@ -118,6 +127,8 @@ module vospi_segment_61#(
reg segment_running; // may be discarded
reg [3:0] segment_id_r;
wire frame_in_done;
reg [1:0] vsync_rdy;
// reg packet_running; // may be discarded
assign is_first_segment_w = (exp_segment == VOSPI_SEGMENT_FIRST);
......@@ -127,7 +138,11 @@ module vospi_segment_61#(
assign segment_good_w = (segment_id == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT);
assign we = segment_running && !discard_segment_r && packet_dv;
// these errors appear as pulses
assign crc_err = packet_done && packet_crc_err; // crc_err_r;
assign sync_err = packet_done && packet_sync_err; // crc_err_r;
assign segment_done_w = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ;
assign id = segment_id_r;
assign frame_in_done = segment_done_w && last_segment_in;
......@@ -136,10 +151,33 @@ module vospi_segment_61#(
assign discard_segment= discard_segment_r; // segment was disc arded
assign dbg_running = segment_running;
assign dbg_vsync_rdy[1:0] = vsync_rdy[1:0];
assign dbg_segment_stb = segment_stb;
// To Buffer
always @ (posedge clk) begin
// if (rst) first_segment_in <= 0;
// else if (start) first_segment_in <= is_first_segment_w;
// if (rst) vsync_rdy[0] <= 0;
// else if (start) vsync_rdy[0] <= ~vsync_use; // bypass
// else if (!vsync) vsync_rdy[0] <= 1;
if (rst) vsync_rdy[0] <= 0;
else if (!vsync_use) vsync_rdy[0] <= 1;
else if (start) vsync_rdy[0] <= 0; // ~vsync_use; // bypass
else if (!vsync) vsync_rdy[0] <= 1;
if (rst) vsync_rdy[1] <= 0;
else if (!vsync_use) vsync_rdy[1] <= 1;
else if (start) vsync_rdy[1] <= 0; // ~vsync_use; // bypass
else if (vsync && vsync_rdy[0]) vsync_rdy[1] <= 1;
// vsync_rdy[1] <= !rst && !start && vsync_rdy[0] && (vsync_rdy[1] || vsync || (start_d && !vsync_use)); // 1 - OK to read packets
/// vsync_rdy[0] <= !rst && (!vsync_use || (!start));
/// vsync_rdy[1] <= !rst && (!vsync_use || (!start && vsync_rdy[0] && (vsync_rdy[1] || vsync ))); // 1 - OK to read packets
if (rst) last_segment_in <= 0;
else if (start) last_segment_in <= is_last_segment_w;
......@@ -181,15 +219,15 @@ module vospi_segment_61#(
if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
// packet_start <= !rst && !packet_busy && segment_busy_r;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
/// packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start && vsync_rdy[1];
if (rst) waddr <= 0;
else if (discard_set) waddr <= segment_start_waddr;
else if (we) waddr <= waddr + 1;
if (rst) full_packet_frame <= 0; // not needed?
else if (frame_in_done) full_packet_frame <=~full_packet_frame;
/// if (rst) full_packet_frame <= 0; // not needed?
/// else if (frame_in_done) full_packet_frame <=~full_packet_frame;
end
// From buffer, generating frame
reg out_request;
......@@ -215,7 +253,9 @@ module vospi_segment_61#(
reg [2:0] hact_r;
reg pend_eof_r;
reg [10:0] raddr;
// wire sync_end;
wire will_sync;
// wire [ 4:0] dbg_state;
assign start_out_frame_w = segment_good && is_first_segment_w && out_request;
......@@ -231,7 +271,10 @@ module vospi_segment_61#(
assign hact = hact_r[2];
assign eof = eof_r[2];
assign sof = sof_r;
assign out_busy = out_request | out_frame;
assign out_busy = resync_disable; // out_request | out_frame;
assign dbg_will_sync = will_sync;
always @ (posedge clk) begin
if (rst) hact_r <= 0;
......@@ -273,6 +316,15 @@ module vospi_segment_61#(
end
reg resync_disable_r;
wire will_sync_masked;
assign will_sync_masked = !resync_disable_r && will_sync;
always @ (posedge clk) begin
if (rst || !will_sync) resync_disable_r <= resync_disable;
end
vospi_packet_80 #(
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS), // 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID) // 1
......@@ -283,16 +335,33 @@ module vospi_segment_61#(
.spi_clken (spi_clken), // output
.spi_cs (spi_cs), // output
.miso (miso), // input
.will_sync (will_sync_masked),// input
.dout (packet_dout), // output[15:0]
.dv (packet_dv), // output
.packet_done (packet_done), // output
.packet_busy (packet_busy), // output
.crc_err (packet_crc_err), // output
.sync_err (packet_sync_err), // output
.id (packet_id), // output[15:0]
.packet_invalid (packet_invalid), // output - not used, processed internally, no dv generated
.id_stb (id_stb) // output reg
);
vospi_resync #(
.VOSPI_PACKET_WORDS(80),
.VOSPI_RESYNC_ZEROS(11)
) vospi_resync_i (
.rst (rst), // input
.clk (clk), // input
.spi_clken (spi_clken), // input
.spi_cs (spi_cs), // input
.miso (miso), // input
// .sync_end (sync_end), // output
.will_sync (will_sync),
.dbg_state (dbg_state) // output[4:0]
);
ram_var_w_var_r #(
.COMMENT("vospi_segment"),
.REGISTERS(1),
......
simulation_modules/simul_lwir160x120_vospi.v
View file @ 9d60666b
......@@ -275,16 +275,26 @@ module simul_lwir160x120_vospi # (
`endif
`endif
integer i;
localparam DISCARD_GAP = 14;
initial begin
// $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
$readmemh(DATA_FILE,sensor_data,0);
// reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1];
packet_bad[0] = 'h0f00;
packet_bad[1] = 'h5220; // calculate and put crc?
// packet_bad[0] = 'h0f00;
// packet_bad[1] = 'h5220; // calculate and put crc?
packet_bad[0] = 'h0fff;
packet_bad[1] = 'hffff; // calculate and put crc?
for (i = 2; i < PACKET_WORDS; i = i+1) begin
packet_bad[i] = 0;
if (i == (DISCARD_GAP + 0)) packet_bad[i] = 16'h0137;
else if (i == (DISCARD_GAP + 1)) packet_bad[i] = 16'hb7c2;
else if (i == (DISCARD_GAP + 2)) packet_bad[i] = 16'ha004;
else if (i == (DISCARD_GAP + 3)) packet_bad[i] = 16'hdd9d;
else if (i == (DISCARD_GAP + 4)) packet_bad[i] = 16'h0001;
else if (i == (DISCARD_GAP + 5)) packet_bad[i] = 16'h0001;
else packet_bad[i] = 0;
end
packet_bad[1] = 'h5220; // calculate and put crc?
// packet_bad[1] = 'h5220; // calculate and put crc?
end
always @ (posedge mclk) begin
if (rst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1;
......
x393.v
View file @ 9d60666b
......@@ -1788,26 +1788,28 @@ assign axi_grst = axi_rst_pre;
.SENS_LENS_POST_SCALE_MASK (SENS_LENS_POST_SCALE_MASK),
.SENSIO_RADDR (SENSIO_RADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
`ifdef LWIR
`else
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`else
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
`endif
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
`ifdef HISPI
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`else
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
`endif
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
......@@ -1815,10 +1817,11 @@ assign axi_grst = axi_rst_pre;
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
`ifndef HISPI
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
`endif
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
......@@ -1836,6 +1839,10 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI
`elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -1849,13 +1856,17 @@ assign axi_grst = axi_rst_pre;
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......@@ -1887,20 +1898,30 @@ assign axi_grst = axi_rst_pre;
.SENS_SYNC_LBITS (SENS_SYNC_LBITS),
.SENS_SYNC_LATE_DFLT (SENS_SYNC_LATE_DFLT),
.SENS_SYNC_MINBITS (SENS_SYNC_MINBITS),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER),
.IDELAY_VALUE (IDELAY_VALUE),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER)
// start with comma
`ifdef LWIR
`else
,.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
`endif
// start with comma
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
,.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS)
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// start with comma
`ifdef LWIR
`else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......@@ -1922,6 +1943,9 @@ assign axi_grst = axi_rst_pre;
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`endif
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
......
x393_vospi.bit
View file @ 9d60666b
No preview for this file type
x393_vospi.timing_summary_impl 0 → 100644
View file @ 9d60666b
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x393_vospi_utilization.report 0 → 100644
View file @ 9d60666b
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