Commit 9b16ac66 authored by Andrey Filippov's avatar Andrey Filippov

debugging qith hardware

parent cd414e1d
......@@ -32,7 +32,6 @@ __status__ = "Development"
#import x393_mem
#from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem
#from verilog_utils import hx,concat, bits
from verilog_utils import hx
from time import time
import vrlg
......@@ -356,7 +355,7 @@ class X393AxiControlStatus(object):
"""
global mcntrl_en
en=(0,1)[en]
if self.verbose>0:
if self.verbose > -10: # 0:
print ("ENABLE MEMCTRL %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
mcntrl_en=en
......@@ -369,8 +368,8 @@ class X393AxiControlStatus(object):
global enabled_channels
enabled_channels = chnen # currently enabled memory channels
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
if self.verbose>0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word)"%enabled_channels)
if self.verbose > -10: # 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen))
def enable_memcntrl_en_dis(self,
chn, # input [3:0] chn;
......@@ -385,8 +384,8 @@ class X393AxiControlStatus(object):
enabled_channels |= 1<<chn;
else:
enabled_channels &= ~(1<<chn);
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + self. MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose>0:
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose > -10: #0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)
def configure_channel_priority(self,
......@@ -399,7 +398,7 @@ class X393AxiControlStatus(object):
"""
global channel_priority
self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
if self.verbose>0:
if self.verbose > -1: # 0:
print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
channel_priority[chn]=priority
......@@ -4996,7 +4996,7 @@ write_settings= {
def measure_all(self,
tasks="*ICWRPOASZB", # "ICWRPOA", #"ICWRPOASZB",
tasks="*DCWRPOASZB", # "ICWRPOA", #"ICWRPOASZB",
prim_steps=1,
primary_set_in=2,
primary_set_out=2,
......@@ -5007,7 +5007,8 @@ write_settings= {
quiet=3):
"""
@param tasks - "*" - load bitfile
"I" - initialize memory, set defaults
"D" - set defaults
"I" - initialize memory, set refresh
"C" cmda, "W' - write levelling, "R" - read levelling (DQI-DQSI), "P" - dqs input phase (DQSI-PHASE),
"O" - output timing (DQ odelay vs DQS odelay), "A" - address/bank lines output delays, "Z" - print results,
"B" - select R/W brances and get the optimal phase
......@@ -5056,11 +5057,17 @@ write_settings= {
'comment':'Load bitfile, initialize FPGA',
'params':{'bitfile':bitfile_path,
'quiet':quiet+1}},
{'key':'I',
{'key':'D',
'func':self.x393_pio_sequences.task_set_up,
'comment':'Initial setup - memory controller, sequences',
'params':{'dqs_pattern':dqs_pattern,
'quiet':quiet+1}},
{'key':'I', # Used when no calibration is needed - "*DI"
'func':self.x393_pio_sequences.init_ddr3,
'comment':'Initialize memory, turn on refresh (used when no calibration is needed)',
'params':{'refresh':True,
'wait_complete':True,
'quiet':quiet+1}},
{'key':'C',
'func':self.adjust_cmda_odelay,
'comment':'Measuring CMDA output delay for each clock phase',
......
......@@ -35,10 +35,6 @@ __status__ = "Development"
from x393_mem import X393Mem
#from x393_axi_control_status import X393AxiControlStatus
import x393_axi_control_status
#from verilog_utils import * # concat, bits
#from verilog_utils import hx, concat, bits, getParWidth
#from verilog_utils import concat, getParWidth
#from x393_axi_control_status import concat, bits
from verilog_utils import convert_w32_to_mem16 #,convert_mem16_to_w32
import vrlg
......
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This diff is collapsed.
......@@ -1235,6 +1235,25 @@ class X393PIOSequences(object):
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
def init_ddr3(self,
refresh=1,
wait_complete=True,
quiet=1):
"""
Enable address/command pins, remove SDRST, enable CKE,
Setup PS PIO
Set DDR3 MR0..MR3 registers
Optionally enable refresh
@param refresh - enable refresh
@param wait_complete Do not request a new transaction from the scheduler until previous memory transaction is finished
@param quiet reduce output
"""
self.restart_ddr3(wait_complete,quiet)
self.x393_axi_tasks.enable_refresh(refresh)
def restart_ddr3(self,
wait_complete=True,
quiet=1):
......@@ -1242,8 +1261,8 @@ class X393PIOSequences(object):
Activate SDRST, enable address/command pins, remove SDRST, enable CKE,
Setup PS PIO
Set DDR3 MR0..MR3 registers
<wait_complete> Do not request a new transaction from the scheduler until previous memory transaction is finished
<quiet> reduce output
@param wait_complete Do not request a new transaction from the scheduler until previous memory transaction is finished
@param quiet reduce output
"""
# enable output for address/commands to DDR chip
self.x393_axi_tasks.enable_cmda(1)
......@@ -1254,9 +1273,9 @@ class X393PIOSequences(object):
sleep(0.001) # actually 500 usec required
self.x393_axi_tasks.enable_cke(1);
self.x393_axi_tasks.enable_memcntrl_channels(0x3) # only channel 0 and 1 are enabled
self.x393_axi_tasks.enable_memcntrl_channels(0x1) # only channel 0 and 1 are enabled
self.x393_axi_tasks.configure_channel_priority(0,0) # lowest priority channel 0
self.x393_axi_tasks.configure_channel_priority(1,0) # lowest priority channel 1
# self.x393_axi_tasks.configure_channel_priority(1,0) # lowest priority channel 1
self.enable_reset_ps_pio(1,0) # enable, no reset
# set MR registers in DDR3 memory, run DCI calibration (long)
......
......@@ -51,7 +51,7 @@ class X393Utils(object):
DEBUG_MODE=1
# vpars=None
x393_mem=None
enabled_channels=0 # currently enable channels
enabled_channels=0 # currently enabled channels
saveFileName=None
x393_axi_tasks=None
# verbose=1
......
......@@ -580,8 +580,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
end
// protect from never end
initial begin
// #200000;
#50000;
#200000;
// #50000;
$display("finish testbench 2");
$finish;
end
......
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