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Commit 9b16ac66 authored by Andrey Filippov's avatar Andrey Filippov
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debugging qith hardware

parent cd414e1d
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Showing with 135 additions and 142 deletions
py393/x393_axi_control_status.py
View file @ 9b16ac66
......@@ -32,7 +32,6 @@ __status__ = "Development"
#import x393_mem
#from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem
#from verilog_utils import hx,concat, bits
from verilog_utils import hx
from time import time
import vrlg
......@@ -356,7 +355,7 @@ class X393AxiControlStatus(object):
"""
global mcntrl_en
en=(0,1)[en]
if self.verbose>0:
if self.verbose > -10: # 0:
print ("ENABLE MEMCTRL %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
mcntrl_en=en
......@@ -369,8 +368,8 @@ class X393AxiControlStatus(object):
global enabled_channels
enabled_channels = chnen # currently enabled memory channels
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
if self.verbose>0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word)"%enabled_channels)
if self.verbose > -10: # 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen))
def enable_memcntrl_en_dis(self,
chn, # input [3:0] chn;
......@@ -385,8 +384,8 @@ class X393AxiControlStatus(object):
enabled_channels |= 1<<chn;
else:
enabled_channels &= ~(1<<chn);
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + self. MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose>0:
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose > -10: #0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)
def configure_channel_priority(self,
......@@ -399,7 +398,7 @@ class X393AxiControlStatus(object):
"""
global channel_priority
self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
if self.verbose>0:
if self.verbose > -1: # 0:
print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
channel_priority[chn]=priority
py393/x393_mcntrl_adjust.py
View file @ 9b16ac66
......@@ -4996,7 +4996,7 @@ write_settings= {
def measure_all(self,
tasks="*ICWRPOASZB", # "ICWRPOA", #"ICWRPOASZB",
tasks="*DCWRPOASZB", # "ICWRPOA", #"ICWRPOASZB",
prim_steps=1,
primary_set_in=2,
primary_set_out=2,
......@@ -5007,7 +5007,8 @@ write_settings= {
quiet=3):
"""
@param tasks - "*" - load bitfile
"I" - initialize memory, set defaults
"D" - set defaults
"I" - initialize memory, set refresh
"C" cmda, "W' - write levelling, "R" - read levelling (DQI-DQSI), "P" - dqs input phase (DQSI-PHASE),
"O" - output timing (DQ odelay vs DQS odelay), "A" - address/bank lines output delays, "Z" - print results,
"B" - select R/W brances and get the optimal phase
......@@ -5056,11 +5057,17 @@ write_settings= {
'comment':'Load bitfile, initialize FPGA',
'params':{'bitfile':bitfile_path,
'quiet':quiet+1}},
{'key':'I',
{'key':'D',
'func':self.x393_pio_sequences.task_set_up,
'comment':'Initial setup - memory controller, sequences',
'params':{'dqs_pattern':dqs_pattern,
'quiet':quiet+1}},
{'key':'I', # Used when no calibration is needed - "*DI"
'func':self.x393_pio_sequences.init_ddr3,
'comment':'Initialize memory, turn on refresh (used when no calibration is needed)',
'params':{'refresh':True,
'wait_complete':True,
'quiet':quiet+1}},
{'key':'C',
'func':self.adjust_cmda_odelay,
'comment':'Measuring CMDA output delay for each clock phase',
......
py393/x393_mcntrl_buffers.py
View file @ 9b16ac66
......@@ -35,10 +35,6 @@ __status__ = "Development"
from x393_mem import X393Mem
#from x393_axi_control_status import X393AxiControlStatus
import x393_axi_control_status
#from verilog_utils import * # concat, bits
#from verilog_utils import hx, concat, bits, getParWidth
#from verilog_utils import concat, getParWidth
#from x393_axi_control_status import concat, bits
from verilog_utils import convert_w32_to_mem16 #,convert_mem16_to_w32
import vrlg
......
py393/x393_mcntrl_membridge.py
View file @ 9b16ac66
......@@ -43,8 +43,13 @@ BUFFER_ASSRESS_NAME='buffer_address'
BUFFER_PAGES_NAME='buffer_pages'
BUFFER_ADDRESS=None
BUFFER_LEN=None
#BUFFER_ADDRESS=0x27900000
#BUFFER_LEN= 0x6400000
PAGE_SIZE=4096
AFI_BASE_ADDR= 0xf8008000
'''
root@elphel393:/sys/devices/elphel393-mem.2# cat buffer_address
0x27900000
......@@ -70,10 +75,10 @@ def func_encode_mode_scanline(extra_pages, # input [1:0] extra_pages; # number
<chn_reset>): immediately reset all the internal circuitry
"""
return verilog_utils.concat ((extra_pages, 2), # extra_pages,
return verilog_utils.concat (((extra_pages, 2), # extra_pages,
((0,1)[write_mem],1), # write_mem,
((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)) # ~chn_reset};
((1,0)[chn_reset],1)))[0] # ~chn_reset};
class X393McntrlMembridge(object):
DRY_MODE= True # True
......@@ -87,6 +92,7 @@ class X393McntrlMembridge(object):
verbose=1
adjustment_state={}
def __init__(self, debug_mode=1,dry_mode=True): #, saveFileName=None):
global BUFFER_ADDRESS, BUFFER_LEN
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= x393_mem.X393Mem(debug_mode,dry_mode)
......@@ -94,6 +100,7 @@ class X393McntrlMembridge(object):
self.x393_pio_sequences= x393_pio_sequences.X393PIOSequences(debug_mode,dry_mode)
self.x393_mcntrl_timing= x393_mcntrl_timing.X393McntrlTiming(debug_mode,dry_mode)
self.x393_mcntrl_buffers= x393_mcntrl_buffers.X393McntrlBuffers(debug_mode,dry_mode)
# self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
try:
self.verbose=vrlg.VERBOSE
......@@ -116,6 +123,7 @@ class X393McntrlMembridge(object):
return
print('BUFFER_ADDRESS=0x%x'%(BUFFER_ADDRESS))
print('BUFFER_LEN=0x%x'%(BUFFER_LEN))
def afi_write_reg(self,
port_num, # input [1:0] port_num;
rel_baddr, # input integer rel_baddr; # relative byte address
......@@ -133,7 +141,7 @@ class X393McntrlMembridge(object):
quiet)
def afi_read_reg(self,
port_num, # input [1:0] port_num;
rel_baddr, # input integer rel_baddr; # relative byte address
rel_baddr=None, # input integer rel_baddr; # relative byte address
quiet=1): #input verbose;
'''
Read data from the AXI_HP (AFI) register
......@@ -142,6 +150,13 @@ class X393McntrlMembridge(object):
@param quiet - reduce output (>=1 - silent)
@return register data
'''
if rel_baddr is None:
rslt=[]
for baddr in (0,4,8,0xc,0x10,0x14,0x18,0x1c,0x20,0x24):
rslt.append(self.afi_read_reg(port_num,baddr,quiet-1))
return rslt
return self.x393_mem.read_mem(AFI_BASE_ADDR+ (port_num << 12) + (rel_baddr & 0xfffffffc),
quiet)
......@@ -168,8 +183,8 @@ class X393McntrlMembridge(object):
len64, # input [28:0] len64; # number of 64-bit words to transfer
width64, # input [28:0] width64; # frame width in 64-bit words
start64, # input [28:0] start64; # relative start adderss of the transfer (set to 0 when writing lo_addr64)
lo_addr64=BUFFER_ADDRESS // 8, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64=BUFFER_LEN // 8, # input [28:0] size64; # size of the system memory range in 64-bit words
lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
quiet=1):
'''
Set up membridge parameters for data transfer
......@@ -180,6 +195,11 @@ class X393McntrlMembridge(object):
@param size64 size of the system memory range in 64-bit words
@quiet - reduce output (>=1 - silent)
'''
if lo_addr64 is None:
lo_addr64 = BUFFER_ADDRESS//8 # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
if size64 is None:
size64 = BUFFER_LEN//8 # input [28:0] size64; # size of the system memory range in 64-bit words
if quiet <2:
print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet))
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);
......@@ -213,16 +233,17 @@ class X393McntrlMembridge(object):
def membridge_rw (self,
write_ddr3, # input write_ddr3;
# extra_pages, # input [1:0] extra_pages;
frame_start_addr, # input [21:0] frame_start_addr;
window_full_width, # input [15:0] window_full_width; # 13 bit - in 8*16=128 bit bursts
window_width, # input [15:0] window_width; # 13 bit - in 8*16=128 bit bursts
window_height, # input [15:0] window_height; # 16 bit (only 14 are used here)
window_left, # input [15:0] window_left;
window_top, # input [15:0] window_top;
start64, # input [28:0] start64; # relative start adderss of the transfer (set to 0 when writing lo_addr64)
lo_addr64=BUFFER_ADDRESS//8, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64=BUFFER_LEN//8, # input [28:0] size64; # size of the system memory range in 64-bit words
cont, # input continue; # 0 start from start64, 1 - continue from where it was
frame_start_addr = None, # input [21:0] frame_start_addr;
window_full_width = None, # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
window_width = None, # input [15:0] window_width; # 13 bit - in 8*16=128 bit bursts
window_height = None, # input [15:0] window_height; # 16 bit (only 14 are used here)
window_left = None, # input [15:0] window_left;
window_top = None, # input [15:0] window_top;
start64 = 0, # input [28:0] start64; # relative start address of the transfer (set to 0 when writing lo_addr64)
lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
cont = False, # input continue; # 0 start from start64, 1 - continue from where it was
wait_ready = False,
quiet=1):
'''
Set up and run data transfer between the system and videobuffer memory
......@@ -237,8 +258,26 @@ class X393McntrlMembridge(object):
@param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits
@param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
@param cont True: continue from the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
@param wait_ready poll status to see if the command finished
@param quiet Reduce output
'''
if frame_start_addr is None:
frame_start_addr = vrlg.FRAME_START_ADDRESS # input [21:0] frame_start_addr;
if window_full_width is None:
window_full_width = vrlg.FRAME_FULL_WIDTH # input [15:0] window_full_width;# 13 bit - in 8*16=128 bit bursts
if window_width is None:
window_width = vrlg.WINDOW_WIDTH # input [15:0] window_width; # 13 bit - in 8*16=128 bit bursts
if window_height is None:
window_height = vrlg.WINDOW_HEIGHT # input [15:0] window_height; # 16 bit (only 14 are used here)
if window_left is None:
window_left = vrlg.WINDOW_X0 # input [15:0] window_left;
if window_top is None:
window_top = vrlg.WINDOW_Y0 # input [15:0] window_top;
if lo_addr64 is None:
lo_addr64 = BUFFER_ADDRESS//8 # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
if size64 is None:
size64 = BUFFER_LEN//8 # input [28:0] size64; # size of the system memory range in 64-bit words
window_height &= 0x3fff
if window_height == 0:
window_height = 0x4000
......@@ -266,8 +305,8 @@ class X393McntrlMembridge(object):
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left) # WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
self.x393_axi_control_status.configure_channel_priority(1,0); # lowest priority channel 1
self.x393_axi_control_status.enable_memcntrl_en_dis(1,1);
self.x393_axi_tasks.configure_channel_priority(1,0); # lowest priority channel 1
self.x393_axi_tasks.enable_memcntrl_en_dis(1,1);
# write_contol_register(test_mode_address, TEST01_START_FRAME);
self.afi_setup(0)
self.membridge_setup(
......@@ -278,6 +317,7 @@ class X393McntrlMembridge(object):
size64)
self.membridge_start (cont)
# just wait done (default timeout = 10 sec)
if wait_ready:
self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
vrlg.MCNTRL_SCANLINE_CHN1_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
......
py393/x393_mcntrl_tests.py
View file @ 9b16ac66
......@@ -83,7 +83,7 @@ class X393McntrlTests(object):
(extra_pages, 2), # extra_pages,
((0,1)[write_mem],1), # write_mem,
((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)))# ~chn_reset};
((1,0)[chn_reset],1)))[0]# ~chn_reset};
def func_encode_mode_scanline(self, # function [4:0]
extra_pages, # input [1:0] extra_pages; # number of extra pages that need to stay (not to be overwritten) in the buffer
......@@ -100,82 +100,11 @@ class X393McntrlTests(object):
<chn_reset>): immediately reset all the internal circuitry
"""
return concat (
return concat ((
(extra_pages, 2), # extra_pages,
((0,1)[write_mem],1), # write_mem,
((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)) # ~chn_reset};
'''
def task_set_up(self,
set_per_pin_delays=0):
"""
Initial setup of the memory controller, including:
disable (and reset) memory controller
enable memory controller
setup status generation in all modules
tristate patterns
DQS/DQM patterns
all sequences
channel 0 buffer data
I/O delays
clock phase
write buffer latency
<set_per_pin_delays> - 1 - set individual (per-pin) I/O delays, 0 - use common for the whole class
Returns 1 if phase was set, 0 if it failed
#reset memory controller
self.x393_axi_tasks.enable_memcntrl(0)
#enable memory controller
self.x393_axi_tasks.enable_memcntrl(1)
#program status for all used modules to refresh at any bit change
self.x393_axi_tasks.program_status_all(3, 0)
# set dq /dqs tristate on/off patterns
self.x393_mcntrl_timing.axi_set_tristate_patterns()
# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
self.x393_mcntrl_timing.axi_set_dqs_dqm_patterns()
# prepare all sequences
self.x393_pio_sequences.set_all_sequences()
# prepare write buffer
self.x393_mcntrl_buffers.write_block_buf_chn(0,0,256); # fill block memory (channel, page, number)
# set all delays
##axi_set_delays - from tables, per-pin
# if set_per_pin_delays:
# Make it an only option TODO: do the same for the simulation!!
self.x393_mcntrl_timing.axi_set_delays() # set all individual delays, aslo runs axi_set_phase()
# else:
# self.x393_mcntrl_timing.axi_set_same_delays(vrlg.DLY_DQ_IDELAY,
# vrlg.DLY_DQ_ODELAY,
# vrlg.DLY_DQS_IDELAY,
# vrlg.DLY_DQS_ODELAY,
# vrlg.DLY_DM_ODELAY,
# vrlg.DLY_CMDA_ODELAY)
# set clock phase relative to DDR clk
# print("Debugging: sleeping for 1 second")
# sleep(1)
phaseOK=self.x393_mcntrl_timing.axi_set_phase(vrlg.DLY_PHASE,wait_phase_en=True); # wait for phase set
if not phaseOK:
print("Failed to set clock phase")
return 0
# read and print status (optional)
self.x393_mcntrl_timing.axi_set_wbuf_delay(vrlg.WBUF_DLY_DFLT)
self.x393_axi_tasks.read_all_status()
return 1
'''
def init_ddr3(self,
refresh=1,
wait_complete=True):
"""
Enable address/command pins, remove SDRST, enable CKE,
Setup PS PIO
Set DDR3 MR0..MR3 registers
Optionally enable refresh
<wait_complete> Do not request a new transaction from the scheduler until previous memory transaction is finished
"""
self.x393_pio_sequences.restart_ddr3(wait_complete)
self.x393_axi_tasks.enable_refresh(refresh)
((1,0)[chn_reset],1)))[0] # ~chn_reset};
def test_write_levelling(self,
dqs_odly= None,
......@@ -330,7 +259,7 @@ class X393McntrlTests(object):
"""
# integer startx,starty; # temporary - because of the vdt bug with integer ports
# pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
pages_per_row= (window_width>>vrlg.NUM_XFER_BITS)+(0,1)[(window_width & ((1<<vrlg.NUM_XFER_BITS))-1)==0] # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
pages_per_row= (window_width>>vrlg.NUM_XFER_BITS)+(1,0)[(window_width & ((1<<vrlg.NUM_XFER_BITS))-1)==0] # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
print("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d"%
(channel, extra_pages, wait_done))
'''
......@@ -357,11 +286,11 @@ class X393McntrlTests(object):
1, # write_mem,
1, # enable
0) # chn_reset
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height<<16) | window_width); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top<<16) | window_left); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX+(vrlg.SCANLINE_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode);
self.x393_axi_tasks.configure_channel_priority(channel,0); # lowest priority channel 3
......@@ -450,7 +379,7 @@ class X393McntrlTests(object):
result=[] # will be a 2-d array
# pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
pages_per_row= (window_width>>vrlg.NUM_XFER_BITS)+(0,1)[(window_width & ((1<<vrlg.NUM_XFER_BITS))-1)==0] # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
pages_per_row= (window_width>>vrlg.NUM_XFER_BITS)+(1,0)[(window_width & ((1<<vrlg.NUM_XFER_BITS))-1)==0] # (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
print("====== test_scanline_read: channel=%d, extra_pages=%d, show_data=%d"%
(channel, extra_pages, show_data))
......@@ -468,7 +397,7 @@ class X393McntrlTests(object):
test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
else:
print("**** ERROR: Invalid channel, only 3 is valid")
start_addr= vrlg.MCNTRL_SCANLINE_CHN1_ADDR
start_addr= vrlg.MCNTRL_SCANLINE_CHN3_ADDR
status_address= vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
......@@ -478,10 +407,11 @@ class X393McntrlTests(object):
1, # enable
0) # chn_reset
# program to the
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX+(vrlg.SCANLINE_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0); # lowest priority channel 3
......@@ -502,8 +432,8 @@ class X393McntrlTests(object):
(ii) << 16, # -TEST_INITIAL_BURST)<<16, # 4-bit page number
0xf << 16, #'hf << 16, # mask for the 4-bit page number
1, # not equal to
(0,1)[ii == 0]) # synchronize sequence number - only first time, next just wait fro auto update
# read block (if needed), for now just sikip
(0,1)[ii == 0]) # synchronize sequence number - only first time, next just wait for auto update
# read block (if needed), for now just skip
if (show_data):
print("########### test_scanline_read block %d: channel=%d"%(ii, channel));
result.append(self.x393_mcntrl_buffers.read_block_buf_chn (
......@@ -577,23 +507,24 @@ class X393McntrlTests(object):
1, # write_mem,
1, # enable
0) # chn_reset
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
vrlg.FRAME_FULL_WIDTH)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
concat(((window_height,16),
(window_width, 16)))) # {window_height,window_width});
(window_width, 16)))[0]) # {window_height,window_width});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
concat(((window_top, 16),
(window_left, 16)))) # {window_top,window_left});
(window_left, 16)))[0]) # {window_top,window_left});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
concat(((vrlg.TILED_STARTY, 16),
(vrlg.TILED_STARTX, 16)))) # TILED_STARTX+(TILED_STARTY<<16));
(vrlg.TILED_STARTX, 16)))[0]) # TILED_STARTX+(TILED_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_TILE_WHS,
concat(((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8)))) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
(tile_width, 8)))[0]) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0) # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
......@@ -704,23 +635,24 @@ class X393McntrlTests(object):
0, # write_mem,
1, # enable
0) # chn_reset
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
vrlg.FRAME_FULL_WIDTH)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
concat(((window_height,16),
(window_width, 16)))) # {window_height,window_width});
(window_width, 16)))[0]) # {window_height,window_width});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
concat(((window_top, 16),
(window_left, 16)))) # {window_top,window_left});
(window_left, 16)))[0]) # {window_top,window_left});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
concat(((vrlg.TILED_STARTY, 16),
(vrlg.TILED_STARTX, 16)))) # TILED_STARTX+(TILED_STARTY<<16));
(vrlg.TILED_STARTX, 16)))[0]) # TILED_STARTX+(TILED_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_TILE_WHS,
concat(((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8)))) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
(tile_width, 8)))[0]) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0) # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
......
py393/x393_pio_sequences.py
View file @ 9b16ac66
......@@ -1235,6 +1235,25 @@ class X393PIOSequences(object):
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
def init_ddr3(self,
refresh=1,
wait_complete=True,
quiet=1):
"""
Enable address/command pins, remove SDRST, enable CKE,
Setup PS PIO
Set DDR3 MR0..MR3 registers
Optionally enable refresh
@param refresh - enable refresh
@param wait_complete Do not request a new transaction from the scheduler until previous memory transaction is finished
@param quiet reduce output
"""
self.restart_ddr3(wait_complete,quiet)
self.x393_axi_tasks.enable_refresh(refresh)
def restart_ddr3(self,
wait_complete=True,
quiet=1):
......@@ -1242,8 +1261,8 @@ class X393PIOSequences(object):
Activate SDRST, enable address/command pins, remove SDRST, enable CKE,
Setup PS PIO
Set DDR3 MR0..MR3 registers
<wait_complete> Do not request a new transaction from the scheduler until previous memory transaction is finished
<quiet> reduce output
@param wait_complete Do not request a new transaction from the scheduler until previous memory transaction is finished
@param quiet reduce output
"""
# enable output for address/commands to DDR chip
self.x393_axi_tasks.enable_cmda(1)
......@@ -1254,9 +1273,9 @@ class X393PIOSequences(object):
sleep(0.001) # actually 500 usec required
self.x393_axi_tasks.enable_cke(1);
self.x393_axi_tasks.enable_memcntrl_channels(0x3) # only channel 0 and 1 are enabled
self.x393_axi_tasks.enable_memcntrl_channels(0x1) # only channel 0 and 1 are enabled
self.x393_axi_tasks.configure_channel_priority(0,0) # lowest priority channel 0
self.x393_axi_tasks.configure_channel_priority(1,0) # lowest priority channel 1
# self.x393_axi_tasks.configure_channel_priority(1,0) # lowest priority channel 1
self.enable_reset_ps_pio(1,0) # enable, no reset
# set MR registers in DDR3 memory, run DCI calibration (long)
......
py393/x393_utils.py
View file @ 9b16ac66
......@@ -51,7 +51,7 @@ class X393Utils(object):
DEBUG_MODE=1
# vpars=None
x393_mem=None
enabled_channels=0 # currently enable channels
enabled_channels=0 # currently enabled channels
saveFileName=None
x393_axi_tasks=None
# verbose=1
......
x393_testbench01.tf
View file @ 9b16ac66
......@@ -580,8 +580,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
end
// protect from never end
initial begin
// #200000;
#50000;
#200000;
// #50000;
$display("finish testbench 2");
$finish;
end
......
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