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Commit 9a17dbfa authored by Andrey Filippov's avatar Andrey Filippov
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Added Python modules to setup memory channels for sensors and compressors, rtc

parent 2adfbae2
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Showing with 424 additions and 15 deletions
py393/test_mcntrl.py
View file @ 9a17dbfa
...@@ -64,6 +64,7 @@ import x393_cmprs_afi ...@@ -64,6 +64,7 @@ import x393_cmprs_afi
import x393_cmprs import x393_cmprs
import x393_frame_sequencer import x393_frame_sequencer
import x393_sensor import x393_sensor
import x393_rtc
import vrlg import vrlg
__all__ = [] __all__ = []
__version__ = 0.1 __version__ = 0.1
...@@ -346,6 +347,7 @@ USAGE ...@@ -346,6 +347,7 @@ USAGE
x393Cmprs = x393_cmprs.X393Cmprs(verbose,args.simulated,args.localparams) x393Cmprs = x393_cmprs.X393Cmprs(verbose,args.simulated,args.localparams)
x393FrameSequencer = x393_frame_sequencer.X393FrameSequencer(verbose,args.simulated,args.localparams) x393FrameSequencer = x393_frame_sequencer.X393FrameSequencer(verbose,args.simulated,args.localparams)
x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams) x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams)
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
''' '''
print ("----------------------") print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__)) print("x393_mem.__dict__="+str(x393_mem.__dict__))
...@@ -377,6 +379,7 @@ USAGE ...@@ -377,6 +379,7 @@ USAGE
extractTasks(x393_cmprs.X393Cmprs, x393Cmprs) extractTasks(x393_cmprs.X393Cmprs, x393Cmprs)
extractTasks(x393_frame_sequencer.X393FrameSequencer, x393FrameSequencer) extractTasks(x393_frame_sequencer.X393FrameSequencer, x393FrameSequencer)
extractTasks(x393_sensor.X393Sensor, x393Sensor) extractTasks(x393_sensor.X393Sensor, x393Sensor)
extractTasks(x393_rtc.X393Rtc, x393Rtc)
for cmdLine in commands: for cmdLine in commands:
print ('Running task: '+str(cmdLine)) print ('Running task: '+str(cmdLine))
......
py393/x393_cmprs.py
View file @ 9a17dbfa
...@@ -39,6 +39,7 @@ import x393_utils ...@@ -39,6 +39,7 @@ import x393_utils
#import time #import time
import vrlg import vrlg
import x393_mcntrl
class X393Cmprs(object): class X393Cmprs(object):
DRY_MODE= True # True DRY_MODE= True # True
DEBUG_MODE=1 DEBUG_MODE=1
...@@ -252,4 +253,74 @@ class X393Cmprs(object): ...@@ -252,4 +253,74 @@ class X393Cmprs(object):
focus_mode = focus_mode) focus_mode = focus_mode)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG, self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG,
data) data)
def setup_compressor_memory (self,
num_sensor,
frame_sa,
frame_sa_inc,
last_frame_num,
frame_full_width,
window_width,
window_height,
window_left,
window_top,
byte32,
tile_width,
extra_pages,
disable_need):
"""
Setup memory controller for a compressor channel
@param num_sensor - sensor port number (0..3)
@param frame_sa - 22-bit frame start address ((3 CA LSBs==0. BA==0)
@param frame_sa_inc - 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
@param last_frame_num - 16-bit number of the last frame in a buffer
@param frame_full_width - 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
@param window_width - 13-bit - in 8*16=128 bit bursts
@param window_height - 16-bit window height (in scan lines)
@param window_left - 13-bit window left margin in 8-bursts (16 bytes)
@param window_top - 16-bit window top margin (in scan lines
@param byte32 - 32-byte columns
@param tile_width tile width,
@param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sesnor channels - they can not wait
"""
tile_vstep = 16
tile_height= 18
base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = disable_need,
repetitive= True,
single = False,
reset_frame = False,
byte32 = byte32,
keep_open = False,
extra_pages = extra_pages,
write_mem = False,
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_STARTADDR,
frame_sa) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_SIZE,
frame_sa_inc)
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_LAST,
last_frame_num)
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
frame_full_width)
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
((window_height & 0xffff) << 16) | (window_width & 0xffff)) #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
((window_top & 0xffff) << 16) | (window_left & 0xffff)) #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
0)
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_TILE_WHS,
((tile_vstep & 0xff) <<16) | ((tile_height & 0xff) <<8) | (tile_width & 0xff)) #//(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(
base_addr + vrlg.MCNTRL_TILED_MODE,
mode);
py393/x393_mcntrl.py 0 → 100644
View file @ 9a17dbfa
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
# Class to set memory controller channels
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
#import sys
#import pickle
#from x393_mem import X393Mem
#import x393_axi_control_status
#import x393_utils
#import time
import vrlg
def func_encode_mode_scan_tiled (disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
byte32 = True,
keep_open = False,
extra_pages = 0,
write_mem = False,
enable = True,
chn_reset = False):
"""
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param disable_need - disable 'need' generation, only 'want' (compressor channels),
@param repetitive - run repetitive frames (add this to older 'master' tests)
@param single - run single frame
@param reset_frame - reset frame number
@param byte32 - 32-byte columns (False - 16-byte columns) (not used in scanline mode)
@param keep_open- for 8 or less rows - do not close page between accesses (not used in scanline mode)
@param extra_pages 2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
This argument can be used for read access with horizontal overlapping tiles
@param write_mem, write to memory mode (0 - read from memory)
@param enable, enable requests from this channel ( 0 will let current to finish, but not raise want/need)
@param chn_reset): immediately reset all the internal circuitry
"""
rslt = 0;
rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_EN # inverted
rslt |= (0,1)[enable] << vrlg.MCONTR_LINTILE_NRESET
rslt |= (0,1)[write_mem] << vrlg.MCONTR_LINTILE_WRITE
rslt |= (extra_pages & ((1 << vrlg.MCONTR_LINTILE_EXTRAPG_BITS) - 1)) << vrlg.MCONTR_LINTILE_EXTRAPG
rslt |= (0,1)[keep_open] << vrlg.MCONTR_LINTILE_KEEP_OPEN
rslt |= (0,1)[byte32] << vrlg.MCONTR_LINTILE_BYTE32
rslt |= (0,1)[reset_frame] << vrlg.MCONTR_LINTILE_RST_FRAME
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
return rslt
'''
class X393Mcntrl(object):
DRY_MODE= True # True
DEBUG_MODE=1
x393_mem=None
x393_axi_tasks=None #x393X393AxiControlStatus
x393_utils=None
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
try:
self.verbose=vrlg.VERBOSE
except:
pass
'''
py393/x393_mcntrl_membridge.py
View file @ 9a17dbfa
...@@ -37,7 +37,7 @@ import x393_pio_sequences ...@@ -37,7 +37,7 @@ import x393_pio_sequences
import x393_mcntrl_timing import x393_mcntrl_timing
import x393_mcntrl_buffers import x393_mcntrl_buffers
import verilog_utils import verilog_utils
import x393_mcntrl
MEM_PATH='/sys/devices/elphel393-mem.2/' MEM_PATH='/sys/devices/elphel393-mem.2/'
BUFFER_ASSRESS_NAME='buffer_address' BUFFER_ASSRESS_NAME='buffer_address'
BUFFER_PAGES_NAME='buffer_pages' BUFFER_PAGES_NAME='buffer_pages'
...@@ -60,6 +60,7 @@ BUFFER_LEN= 104857600 ...@@ -60,6 +60,7 @@ BUFFER_LEN= 104857600
BUFFER_ADDRESS=0x27900000 BUFFER_ADDRESS=0x27900000
BUFFER_LEN=0x6400000 BUFFER_LEN=0x6400000
'''
''' '''
def func_encode_mode_scanline(extra_pages, # input [1:0] extra_pages; # number of extra pages that need to stay (not to be overwritten) in the buffer def func_encode_mode_scanline(extra_pages, # input [1:0] extra_pages; # number of extra pages that need to stay (not to be overwritten) in the buffer
# can be used for overlapping tile read access # can be used for overlapping tile read access
...@@ -68,18 +69,18 @@ def func_encode_mode_scanline(extra_pages, # input [1:0] extra_pages; # number ...@@ -68,18 +69,18 @@ def func_encode_mode_scanline(extra_pages, # input [1:0] extra_pages; # number
chn_reset): # input chn_reset; # immediately reset all the internal circuitry chn_reset): # input chn_reset; # immediately reset all the internal circuitry
""" """
Combines arguments to create a 5-bit encoded data for scanline mode memory R/W Combines arguments to create a 5-bit encoded data for scanline mode memory R/W
<extra_pages>, 2-bit number of extra pages that need to stay (not to be overwritten) in the buffer @param extra_pages 2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
This argument can be used for read access with horizontal overlapping tiles This argument can be used for read access with horizontal overlapping tiles
<write_mem>, write to memory mode (0 - read from memory) @param write_mem, write to memory mode (0 - read from memory)
<enable>, enable requests from this channel ( 0 will let current to finish, but not raise want/need) @param enable, enable requests from this channel ( 0 will let current to finish, but not raise want/need)
<chn_reset>): immediately reset all the internal circuitry @param chn_reset): immediately reset all the internal circuitry
""" """
return verilog_utils.concat (((extra_pages, 2), # extra_pages, return verilog_utils.concat (((extra_pages, 2), # extra_pages,
((0,1)[write_mem],1), # write_mem, ((0,1)[write_mem],1), # write_mem,
((0,1)[enable], 1), #enable, ((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)))[0] # ~chn_reset}; ((1,0)[chn_reset],1)))[0] # ~chn_reset};
'''
class X393McntrlMembridge(object): class X393McntrlMembridge(object):
DRY_MODE= True # True DRY_MODE= True # True
DEBUG_MODE=1 DEBUG_MODE=1
...@@ -299,11 +300,23 @@ class X393McntrlMembridge(object): ...@@ -299,11 +300,23 @@ class X393McntrlMembridge(object):
(window_width << 1)*window_height, (window_width << 1)*window_height,
(window_width << 1), (window_width << 1),
start64, lo_addr64, size64,cache)) start64, lo_addr64, size64,cache))
'''
mode= func_encode_mode_scanline( mode= func_encode_mode_scanline(
0, # extra_pages, 0, # extra_pages,
write_ddr3, # write_mem, write_ddr3, # write_mem,
1, # enable 1, # enable
0) # chn_reset 0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
extra_pages = 0,
write_mem = write_ddr3,
enable = True,
chn_reset = False)
# self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64); # self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
# self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address # self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
......
py393/x393_mcntrl_tests.py
View file @ 9a17dbfa
...@@ -35,6 +35,7 @@ from x393_mcntrl_timing import X393McntrlTiming ...@@ -35,6 +35,7 @@ from x393_mcntrl_timing import X393McntrlTiming
from x393_mcntrl_buffers import X393McntrlBuffers from x393_mcntrl_buffers import X393McntrlBuffers
from verilog_utils import concat,convert_w32_to_mem16 #, getParWidth from verilog_utils import concat,convert_w32_to_mem16 #, getParWidth
import vrlg import vrlg
import x393_mcntrl
class X393McntrlTests(object): class X393McntrlTests(object):
DRY_MODE= True # True DRY_MODE= True # True
DEBUG_MODE=1 DEBUG_MODE=1
...@@ -57,7 +58,7 @@ class X393McntrlTests(object): ...@@ -57,7 +58,7 @@ class X393McntrlTests(object):
self.verbose=vrlg.VERBOSE self.verbose=vrlg.VERBOSE
except: except:
pass pass
'''
def func_encode_mode_tiled(self, # function [6:0] def func_encode_mode_tiled(self, # function [6:0]
byte32, # input byte32; # 32-byte columns (0 - 16-byte columns) byte32, # input byte32; # 32-byte columns (0 - 16-byte columns)
keep_open, # input keep_open; # for 8 or less rows - do not close page between accesses keep_open, # input keep_open; # for 8 or less rows - do not close page between accesses
...@@ -105,7 +106,7 @@ class X393McntrlTests(object): ...@@ -105,7 +106,7 @@ class X393McntrlTests(object):
((0,1)[write_mem],1), # write_mem, ((0,1)[write_mem],1), # write_mem,
((0,1)[enable], 1), #enable, ((0,1)[enable], 1), #enable,
((1,0)[chn_reset],1)))[0] # ~chn_reset}; ((1,0)[chn_reset],1)))[0] # ~chn_reset};
'''
def test_write_levelling(self, def test_write_levelling(self,
dqs_odly= None, dqs_odly= None,
wbuf_dly = None, wbuf_dly = None,
...@@ -281,11 +282,24 @@ class X393McntrlTests(object): ...@@ -281,11 +282,24 @@ class X393McntrlTests(object):
status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
'''
mode= self.func_encode_mode_scanline( mode= self.func_encode_mode_scanline(
extra_pages, extra_pages,
1, # write_mem, 1, # write_mem,
1, # enable 1, # enable
0) # chn_reset 0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
extra_pages = extra_pages,
write_mem = True,
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH); self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
...@@ -416,11 +430,23 @@ class X393McntrlTests(object): ...@@ -416,11 +430,23 @@ class X393McntrlTests(object):
status_address= vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR status_address= vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR
status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_STATUS_CNTRL
test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN3_MODE
'''
mode= self.func_encode_mode_scanline( mode= self.func_encode_mode_scanline(
extra_pages, extra_pages,
0, # write_mem, 0, # write_mem,
1, # enable 1, # enable
0) # chn_reset 0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
extra_pages = extra_pages,
write_mem = False,
enable = True,
chn_reset = False)
# program to the # program to the
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
...@@ -516,6 +542,7 @@ class X393McntrlTests(object): ...@@ -516,6 +542,7 @@ class X393McntrlTests(object):
status_address= vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR; status_address= vrlg.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL; status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE; test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE;
'''
mode= self.func_encode_mode_tiled( mode= self.func_encode_mode_tiled(
byte32, byte32,
keep_open, keep_open,
...@@ -523,6 +550,19 @@ class X393McntrlTests(object): ...@@ -523,6 +550,19 @@ class X393McntrlTests(object):
1, # write_mem, 1, # write_mem,
1, # enable 1, # enable
0) # chn_reset 0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
byte32 = byte32,
keep_open = keep_open,
extra_pages = extra_pages,
write_mem = True,
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR, self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
...@@ -644,6 +684,7 @@ class X393McntrlTests(object): ...@@ -644,6 +684,7 @@ class X393McntrlTests(object):
status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL; status_control_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE; test_mode_address= vrlg.MCNTRL_TEST01_ADDR + vrlg.MCNTRL_TEST01_CHN2_MODE;
'''
mode= self.func_encode_mode_tiled( mode= self.func_encode_mode_tiled(
byte32, byte32,
keep_open, keep_open,
...@@ -651,6 +692,19 @@ class X393McntrlTests(object): ...@@ -651,6 +692,19 @@ class X393McntrlTests(object):
0, # write_mem, 0, # write_mem,
1, # enable 1, # enable
0) # chn_reset 0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
byte32 = byte32,
keep_open = keep_open,
extra_pages = extra_pages,
write_mem = False,
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR, self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
......
py393/x393_rtc.py 0 → 100644
View file @ 9a17dbfa
from __future__ import division
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
# Class to control 10393 FPGA-based real time clock
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http:#www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
#import sys
#import pickle
from x393_mem import X393Mem
import x393_axi_control_status
import x393_utils
#import time
import vrlg
class X393Rtc(object):
DRY_MODE= True # True
DEBUG_MODE=1
x393_mem=None
x393_axi_tasks=None #x393X393AxiControlStatus
x393_utils=None
verbose=1
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
try:
self.verbose=vrlg.VERBOSE
except:
pass
def program_status_rtc(self,
mode, # input [1:0] mode;
seq_num): # input [5:0] seq_num;
"""
Set status generation mode for RTC. It also takes a snapshot that will
be available before status is read back (so use non-auto mode)
@param mode - status generation mode:
0: disable status generation,
1: single status request,
2: auto status, keep specified seq number,
4: auto, inc sequence number
@param seq_number - 6-bit sequence number of the status message to be sent
"""
self.x393_axi_tasks.program_status (vrlg.RTC_ADDR,
vrlg.RTC_SET_STATUS,
mode,
seq_num)
def set_rtc(self,
sec,
usec,
corr):
"""
Set RTC time and correction
@param sec - number of seconds (usually epoch)
@param usec - number of microseconds
@parame corr signed 16-bit correction (full range is +/- 1/256
"""
self.x393_axi_tasks.write_contol_register(vrlg.RTC_ADDR + vrlg.RTC_SET_CORR, corr);
self.x393_axi_tasks.write_contol_register(vrlg.RTC_ADDR + vrlg.RTC_SET_USEC, usec);
self.x393_axi_tasks.write_contol_register(vrlg.RTC_ADDR + vrlg.RTC_SET_SEC, sec);
py393/x393_sens_cmprs.py
View file @ 9a17dbfa
...@@ -34,6 +34,13 @@ __status__ = "Development" ...@@ -34,6 +34,13 @@ __status__ = "Development"
#import pickle #import pickle
from x393_mem import X393Mem from x393_mem import X393Mem
import x393_axi_control_status import x393_axi_control_status
import x393_camsync
import x393_gpio
import x393_cmprs_afi
import x393_cmprs
import x393_frame_sequencer
import x393_sensor
import x393_rtc
import x393_utils import x393_utils
...@@ -42,18 +49,36 @@ import vrlg ...@@ -42,18 +49,36 @@ import vrlg
SI5338_PATH = "/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070" SI5338_PATH = "/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070"
POWER393_PATH = "/sys/devices/elphel393-pwr.1" POWER393_PATH = "/sys/devices/elphel393-pwr.1"
class X393SensCmprs(object): class X393SensCmprs(object):
DRY_MODE= True # True DRY_MODE = True # True
DEBUG_MODE=1 DEBUG_MODE = 1
x393_mem=None x393_mem = None
x393_axi_tasks=None #x393X393AxiControlStatus x393_axi_tasks = None #x393X393AxiControlStatus
x393_utils=None x393_utils = None
verbose=1 verbose = 1
x393Camsync = None
x393GPIO = None
x393CmprsAfi = None
x393Cmprs = None
x393FrameSequencer = None
x393Sensor = None
x393Rtc = None
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None): def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode) self.x393_mem= X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode) self.x393_axi_tasks= x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
self.x393Camsync = x393_camsync.X393Camsync(debug_mode,dry_mode, saveFileName)
self.x393GPIO = x393_gpio.X393GPIO(debug_mode,dry_mode, saveFileName)
self.x393CmprsAfi = x393_cmprs_afi.X393CmprsAfi(debug_mode,dry_mode, saveFileName)
self.x393Cmprs = x393_cmprs.X393Cmprs(debug_mode,dry_mode, saveFileName)
self.x393FrameSequencer = x393_frame_sequencer.X393FrameSequencer(debug_mode,dry_mode, saveFileName)
self.x393Sensor = x393_sensor.X393Sensor(debug_mode,dry_mode, saveFileName)
self.x393Rtc = x393_rtc.X393Rtc(debug_mode,dry_mode, saveFileName)
try: try:
self.verbose=vrlg.VERBOSE self.verbose=vrlg.VERBOSE
except: except:
......
py393/x393_sensor.py
View file @ 9a17dbfa
...@@ -39,6 +39,7 @@ import x393_utils ...@@ -39,6 +39,7 @@ import x393_utils
#import time #import time
import vrlg import vrlg
import x393_mcntrl
class X393Sensor(object): class X393Sensor(object):
DRY_MODE= True # True DRY_MODE= True # True
DEBUG_MODE=1 DEBUG_MODE=1
...@@ -685,3 +686,51 @@ class X393Sensor(object): ...@@ -685,3 +686,51 @@ class X393Sensor(object):
""" """
channel = ((num_sensor & 3) << 2) + (subchannel & 3) channel = ((num_sensor & 3) << 2) + (subchannel & 3)
self.x393_axi_tasks.write_contol_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,page) self.x393_axi_tasks.write_contol_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,page)
def setup_sensor_memory (self,
num_sensor,
frame_sa,
frame_sa_inc,
last_frame_num,
frame_full_width,
window_width,
window_height,
window_left,
window_top):
"""
Setup memory controller for a sensor channel
@param num_sensor - sensor port number (0..3)
@param frame_sa - 22-bit frame start address ((3 CA LSBs==0. BA==0)
@param frame_sa_inc - 22-bit frame start address increment ((3 CA LSBs==0. BA==0)
@param last_frame_num - 16-bit number of the last frame in a buffer
@param frame_full_width - 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
@param window_width - 13-bit - in 8*16=128 bit bursts
@param window_height - 16-bit window height (in scan lines)
@param window_left - 13-bit window left margin in 8-bursts (16 bytes)
@param window_top - 16-bit window top margin (in scan lines
"""
base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
extra_pages = 0,
write_mem = True,
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_STARTADDR,
frame_sa); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_FRAME_SIZE,
frame_sa_inc);
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_FRAME_LAST,
last_frame_num);
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH,
frame_full_width);
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH,
((window_height & 0xffff) << 16) | (window_width & 0xffff)) #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0,
((window_top & 0xffff) << 16) | (window_left & 0xffff)) #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
self.x393_axi_tasks.write_contol_register(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode)
x393_testbench02.tf
View file @ 9a17dbfa
...@@ -3356,6 +3356,7 @@ function [STATUS_DEPTH-1:0] func_status_addr_sensor_io; ...@@ -3356,6 +3356,7 @@ function [STATUS_DEPTH-1:0] func_status_addr_sensor_io;
endfunction endfunction
// RTC tasks // RTC tasks
// x393_rtc.py
task program_status_rtc; // set status mode, and take a time snapshot (wait response and read time) task program_status_rtc; // set status mode, and take a time snapshot (wait response and read time)
input [1:0] mode; input [1:0] mode;
input [5:0] seq_num; input [5:0] seq_num;
...@@ -3368,6 +3369,7 @@ task program_status_rtc; // set status mode, and take a time snapshot (wait resp ...@@ -3368,6 +3369,7 @@ task program_status_rtc; // set status mode, and take a time snapshot (wait resp
endtask endtask
// x393_rtc.py
task set_rtc; task set_rtc;
input [31:0] sec; input [31:0] sec;
input [19:0] usec; input [19:0] usec;
......
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