Commit 98c7d0ea authored by Andrey Filippov's avatar Andrey Filippov

debugging receive uart, before adding packet separation

parent b78d4000
......@@ -55,9 +55,12 @@ module boson_uart #(
output [7:0] rx_byte, // received byte
output rx_stb // received data strobe (valid 1 cycle before and later for 1 bit)
);
/*
`ifdef SIMULATION
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
`endif
*/
localparam CLK_DIV_BITS = clogb2(CLK_DIV); // + 1);
localparam RX_DEBOUNCE_BITS = clogb2(RX_DEBOUNCE + 1);
reg [CLK_DIV_BITS-1:0] clk_div_cntr_rx;
......@@ -91,7 +94,7 @@ module boson_uart #(
assign debounced = (debounce_cntr == 0);
assign rx_bitw = (clk_div_cntr_rx == 0);
assign tx_bitw = (clk_div_cntr_tx == 0);
assign mark = &rx_sr; // all ones
assign mark = &rx_sr & rxd_r; // all ones
assign start_bit_rx = (rx_bcntr == 0);
assign stop_bit_rx = (rx_bcntr == 9);
assign stop_bit_tx = (tx_bcntr == 9);
......
......@@ -82,9 +82,6 @@ module serial_103993#(
output [7:0] recv_data
);
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
wire [ 7:0] xmit_fifo_out;
wire [ 1:0] xmit_fifo_re_regen;
wire [10:0] xmit_fifo_waddr;
......
......@@ -75,9 +75,10 @@ module serial_destuffer#(
assign flsp_end = in_stb[0] && (rxd_in_r == END_FRAME_BYTE);
assign is_esc_w = rxd_in_r == ESCAPE_BYTE;
assign replaced_w = {
(rxd_in_r == REPLACED_START_FRAME_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_ESCAPE_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_END_FRAME_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_ESCAPE_BYTE) ? 1'b1: 1'b0};
(rxd_in_r == REPLACED_START_FRAME_BYTE) ? 1'b1: 1'b0
};
assign packet_run = packet_run_r[0];
assign rxd_out = rxd_r;
......
......@@ -68,9 +68,11 @@ module serial_fslp #(
output rx_packet_run, // run received packet
output rx_packet_done // finished receiving packet (last 2 bytes - crc16)
);
/*
`ifdef SIMULATION
wire[7:0]debug_UART_CLK_DIV = CLK_DIV; // = 22,
wire[7:0]debug_UART_RX_DEBOUNCE = RX_DEBOUNCE; // 6,
`endif*/
wire [7:0] uart_txd;
wire [7:0] uart_rxd;
wire uart_tx_stb;
......
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