before adding extra register layer between channel buffers outputs and memory controller

address_map.txt

+    parameter MCONTR_WR_MASK =       'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
+    parameter MCONTR_RD_MASK =       'h3c00, // AXI read address mask to generate busy
+    parameter MCONTR_CMD_WR_ADDR =   'h0000, // AXI write to command sequence memory
+    parameter MCONTR_BUF0_RD_ADDR =  'h0400, // AXI read address from buffer 0 (PS sequence, memory read) 
+    parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
+    parameter MCONTR_BUF1_RD_ADDR =  'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
+    parameter MCONTR_BUF1_WR_ADDR =  'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
+    parameter MCONTR_BUF2_RD_ADDR =  'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
+    parameter MCONTR_BUF2_WR_ADDR =  'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
+    parameter MCONTR_BUF3_RD_ADDR =  'h1000, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
+    parameter MCONTR_BUF3_WR_ADDR =  'h1000, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
+    parameter MCONTR_BUF4_RD_ADDR =  'h1400, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
+    parameter MCONTR_BUF4_WR_ADDR =  'h1400, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
+    parameter CONTROL_ADDR =         'h2000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =    'h3800, // AXI write address of control registers
+    // so 'h2000..'h23ff (CONTROL_ADDR) - no busy when writing, 'h2400..'h27ff (CONTROL_ADDR | BUSY_WR_ADDR) generates busy if fifo half full
+    parameter BUSY_WR_ADDR =         'h1400, // AXI write address to generate busy
+    parameter BUSY_WR_ADDR_MASK =    'h3c00, // AXI write address mask to generate busy during memory controller register write
+    parameter STATUS_ADDR =          'h2800, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =     'h3c00, // AXI write address of status registers
+    parameter AXI_WR_ADDR_BITS =        14,
+    parameter AXI_RD_ADDR_BITS =        14,
+    parameter STATUS_DEPTH=              8,  // 256 cells, maybe just 16..64 are enough?
+
+
+--------------
+        .MCONTR_WR_MASK                    (MCONTR_WR_MASK),
+        .MCONTR_RD_MASK                    (MCONTR_RD_MASK),
+        .MCONTR_CMD_WR_ADDR                (MCONTR_CMD_WR_ADDR),
+        .MCONTR_BUF0_RD_ADDR               (MCONTR_BUF0_RD_ADDR),
+        .MCONTR_BUF0_WR_ADDR               (MCONTR_BUF0_WR_ADDR),
+        .MCONTR_BUF1_RD_ADDR               (MCONTR_BUF1_RD_ADDR),
+        .MCONTR_BUF1_WR_ADDR               (MCONTR_BUF1_WR_ADDR),
+        .MCONTR_BUF2_RD_ADDR               (MCONTR_BUF2_RD_ADDR),
+        .MCONTR_BUF2_WR_ADDR               (MCONTR_BUF2_WR_ADDR),
+        .MCONTR_BUF3_RD_ADDR               (MCONTR_BUF3_RD_ADDR),
+        .MCONTR_BUF3_WR_ADDR               (MCONTR_BUF3_WR_ADDR),
+        .MCONTR_BUF4_RD_ADDR               (MCONTR_BUF4_RD_ADDR),
+        .MCONTR_BUF4_WR_ADDR               (MCONTR_BUF4_WR_ADDR),
+        .CONTROL_ADDR                      (CONTROL_ADDR),
+        .CONTROL_ADDR_MASK                 (CONTROL_ADDR_MASK),
+        .BUSY_WR_ADDR                      (BUSY_WR_ADDR),
+        .BUSY_WR_ADDR_MASK                 (BUSY_WR_ADDR_MASK),
+        .STATUS_ADDR                       (STATUS_ADDR),
+        .STATUS_ADDR_MASK                  (STATUS_ADDR_MASK),
+        .AXI_WR_ADDR_BITS                  (AXI_WR_ADDR_BITS),
+        .AXI_RD_ADDR_BITS                  (AXI_RD_ADDR_BITS),
+        .STATUS_DEPTH                      (STATUS_DEPTH),
+
+ddrc_control        
+    parameter BUSY_WR_ADDR =        'h1800, // AXI write address to generate busy
+    parameter BUSY_WR_ADDR_MASK =   'h1c00, // AXI write address mask to generate busy
+        
+        
+
 //0x1080..10ff - 8- bit data - to set various delay values
     parameter DLY_LD =            'h080,  // address to generate delay load 
     parameter DLY_LD_MASK =       'h380,  // address mask to generate delay load

cmd_mux.v

@@ -21,9 +21,9 @@
 `timescale 1ns/1ps
 
 module  cmd_mux #(
-    parameter AXI_WR_ADDR_BITS=    13,
-    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
-    parameter CONTROL_ADDR_MASK =   'h1400, // AXI write address of control registers
+    parameter AXI_WR_ADDR_BITS=    14,
+    parameter CONTROL_ADDR =         'h2000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =    'h3c00, // AXI write address of control registers
     parameter NUM_CYCLES_LOW_BIT=   6, // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
     parameter NUM_CYCLES_00 =       9, // single-cycle
     parameter NUM_CYCLES_01 =       2, // 2-cycle

includes/x393_parameters.vh

@@ -18,17 +18,11 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-    parameter MCONTR_WR_MASK =       'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
-    parameter MCONTR_RD_MASK =       'h1c00, // AXI read address mask to generate busy
-
+    parameter MCONTR_WR_MASK =       'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
+    parameter MCONTR_RD_MASK =       'h3c00, // AXI read address mask to generate busy
     parameter MCONTR_CMD_WR_ADDR =   'h0000, // AXI write to command sequence memory
     parameter MCONTR_BUF0_RD_ADDR =  'h0400, // AXI read address from buffer 0 (PS sequence, memory read) 
     parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
-//    parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
-//    parameter MCONTR_BUF2_RD_ADDR =  'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
-//    parameter MCONTR_BUF3_WR_ADDR =  'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
-//    parameter MCONTR_BUF4_RD_ADDR =  'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
-//    parameter MCONTR_BUF5_WR_ADDR =  'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF1_RD_ADDR =  'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
     parameter MCONTR_BUF1_WR_ADDR =  'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF2_RD_ADDR =  'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
@@ -37,6 +31,14 @@
     parameter MCONTR_BUF3_WR_ADDR =  'h1000, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF4_RD_ADDR =  'h1400, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
     parameter MCONTR_BUF4_WR_ADDR =  'h1400, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
+    parameter CONTROL_ADDR =         'h2000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =    'h3c00, // AXI write address of control registers
+    parameter STATUS_ADDR =          'h2400, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =     'h3c00, // AXI write address of status registers
+    parameter AXI_WR_ADDR_BITS =        14,
+    parameter AXI_RD_ADDR_BITS =        14,
+    parameter STATUS_DEPTH=              8,  // 256 cells, maybe just 16..64 are enough?
+    
 //command interface parameters
     parameter DLY_LD =            'h080,  // address to generate delay load
     parameter DLY_LD_MASK =       'h380,  // address mask to generate delay load
@@ -151,14 +153,6 @@
     parameter CMD_PAUSE_BITS=       10,
     parameter CMD_DONE_BIT=         10,
     
-    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
-    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
-    parameter STATUS_DEPTH=         8,  // 256 cells, maybe just 16..64 are enough?
-    
-    parameter AXI_WR_ADDR_BITS =    13,
-    parameter AXI_RD_ADDR_BITS =    13,
-    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
-    parameter CONTROL_ADDR_MASK =   'h1400, // AXI write address of control registers
     parameter NUM_CYCLES_LOW_BIT=   'h6,    // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
 // TODO: put actual data    
     parameter NUM_CYCLES_00 =       2, // 2-cycle 000.003f

memctrl/ddrc_status.v

-/*******************************************************************************
- * Module: ddrc_status
- * Date:2014-05-19  
- * Author: Andrey Filippov
- * Description: Read status/radback information from the DDR controller
- *
- * Copyright (c) 2014 Elphel, Inc.
- * ddrc_status.v is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- *  ddrc_status.v is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/> .
- *******************************************************************************/
-`timescale 1ns/1ps
-
-module  ddrc_status
-//#(
-//    parameter AXI_RD_ADDR_BITS=   12
-//    parameter SELECT_ADDR =      'h800, // address to select this module
-//    parameter SELECT_ADDR_MASK = 'h800, // address mask to select this  module
-//    parameter BUSY_ADDR =        'hc00, // address to generate busy
-//    parameter BUSY_ADDR_MASK =   'hc00  // address mask to generate busy
-//)
- (
-//    input                         clk,
-//    input                         mclk,
-//    input                         rst,
-//    input  [AXI_RD_ADDR_BITS-1:0] pre_raddr,     // AXI reade address, before actual reads (to generate busy), valid@start_burst
-//    input                         start_rburst,  // burst start - should generate ~ready (should be AND-ed with !busy internally) 
-//    input  [AXI_RD_ADDR_BITS-1:0] raddr,         // read address, valid with rd_en
-//    input                         rd_en,         // read enable
-    output                 [31:0] rdata,         // read data, should valid with raddr and rd_en
-    output                        busy,          // interface busy (combinatorial delay from start_wburst and pre_addr
-// status/readback signals
-//    input                         run_done,      // sequencer done (add busy?)
-    input                         run_busy,       // sequencer busy
-    input                         locked,        // MMCM and PLL locked
-    input                         locked_mmcm,
-    input                         locked_pll,
-    input                         dly_ready,
-    input                         dci_ready,
-    input                         ps_rdy,        // MMCM phase shift control ready
-    input                  [ 7:0] ps_out         // MMCM phase shift value (in 1/56 of the Fvco period)
-);
-    assign busy=0;
-    assign rdata={17'b0,dly_ready,dci_ready, locked_mmcm, locked_pll, run_busy,locked,ps_rdy,ps_out[7:0]};
-    
-
-endmodule
-

memctrl/mcntrl393.v

@@ -22,20 +22,11 @@
 
 module  mcntrl393 #(
 // AXI
-    parameter AXI_WR_ADDR_BITS =    13,
-    parameter AXI_RD_ADDR_BITS =    13,
-// buffers (1k='h400 each) map, addresses and masks are in 32-bit words, not bytes
-    parameter MCONTR_WR_MASK =       'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
-    parameter MCONTR_RD_MASK =       'h1c00, // AXI read address mask to generate busy
-
+    parameter MCONTR_WR_MASK =       'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
+    parameter MCONTR_RD_MASK =       'h3c00, // AXI read address mask to generate busy
     parameter MCONTR_CMD_WR_ADDR =   'h0000, // AXI write to command sequence memory
     parameter MCONTR_BUF0_RD_ADDR =  'h0400, // AXI read address from buffer 0 (PS sequence, memory read) 
     parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
-//    parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
-//    parameter MCONTR_BUF2_RD_ADDR =  'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
-//    parameter MCONTR_BUF3_WR_ADDR =  'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
-//    parameter MCONTR_BUF4_RD_ADDR =  'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
-//    parameter MCONTR_BUF5_WR_ADDR =  'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF1_RD_ADDR =  'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
     parameter MCONTR_BUF1_WR_ADDR =  'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF2_RD_ADDR =  'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
@@ -44,6 +35,8 @@ module  mcntrl393 #(
     parameter MCONTR_BUF3_WR_ADDR =  'h1000, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF4_RD_ADDR =  'h1400, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
     parameter MCONTR_BUF4_WR_ADDR =  'h1400, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
+    parameter AXI_WR_ADDR_BITS =        14,
+    parameter AXI_RD_ADDR_BITS =        14,
 
     
 //command interface parameters

memctrl/mcntrl_linear_rw.v

@@ -363,7 +363,7 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
         
         if (rst)                                          need_r <= 0;
         else if (chn_rst || xfer_grant)                   need_r <= 0;
-        else if (pre_want && (page_cntr>=3)) need_r <= 1;
+        else if ((pre_want  || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
 
         if (rst)                                                 want_r <= 0;
         else if (chn_rst || xfer_grant)                          want_r <= 0;

memctrl/mcntrl_tiled_rw.v

@@ -393,7 +393,7 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
         
         if (rst)                                          need_r <= 0;
         else if (chn_rst || xfer_grant)                   need_r <= 0;
-        else if (pre_want && (page_cntr>=3)) need_r <= 1;
+        else if ((pre_want  || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
 
         if (rst)                                                 want_r <= 0;
         else if (chn_rst || xfer_grant)                          want_r <= 0;

status_read.v

@@ -29,9 +29,9 @@
 `timescale 1ns/1ps
 
 module  status_read#(
-    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
-    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
-    parameter AXI_RD_ADDR_BITS =    13,
+    parameter STATUS_ADDR =           'h2400, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =      'h3c00, // AXI write address of status registers
+    parameter AXI_RD_ADDR_BITS =      14,
     parameter integer STATUS_DEPTH=   8 // 256 cells, maybe just 16..64 are enough?
 )(
     input rst,

x393.v

@@ -23,17 +23,11 @@
 //`define DEBUG_FIFO 1
 `include ".editor_defines.vh" 
 module  x393 #(
-    parameter MCONTR_WR_MASK =       'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
-    parameter MCONTR_RD_MASK =       'h1c00, // AXI read address mask to generate busy
-
+    parameter MCONTR_WR_MASK =       'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
+    parameter MCONTR_RD_MASK =       'h3c00, // AXI read address mask to generate busy
     parameter MCONTR_CMD_WR_ADDR =   'h0000, // AXI write to command sequence memory
     parameter MCONTR_BUF0_RD_ADDR =  'h0400, // AXI read address from buffer 0 (PS sequence, memory read) 
     parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
-//    parameter MCONTR_BUF0_WR_ADDR =  'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
-//    parameter MCONTR_BUF2_RD_ADDR =  'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
-//    parameter MCONTR_BUF3_WR_ADDR =  'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
-//    parameter MCONTR_BUF4_RD_ADDR =  'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
-//    parameter MCONTR_BUF5_WR_ADDR =  'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF1_RD_ADDR =  'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
     parameter MCONTR_BUF1_WR_ADDR =  'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF2_RD_ADDR =  'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
@@ -42,6 +36,14 @@ module  x393 #(
     parameter MCONTR_BUF3_WR_ADDR =  'h1000, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
     parameter MCONTR_BUF4_RD_ADDR =  'h1400, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
     parameter MCONTR_BUF4_WR_ADDR =  'h1400, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
+    parameter CONTROL_ADDR =         'h2000, // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =    'h3c00, // AXI write address of control registers
+    parameter STATUS_ADDR =          'h2400, // AXI write address of status read registers
+    parameter STATUS_ADDR_MASK =     'h3c00, // AXI write address of status registers
+    parameter AXI_WR_ADDR_BITS =        14,
+    parameter AXI_RD_ADDR_BITS =        14,
+    parameter STATUS_DEPTH=              8,  // 256 cells, maybe just 16..64 are enough?
+    
 //command interface parameters
     parameter DLY_LD =            'h080,  // address to generate delay load
     parameter DLY_LD_MASK =       'h380,  // address mask to generate delay load
@@ -155,15 +157,6 @@ module  x393 #(
     parameter SS_MOD_PERIOD =       10000,
     parameter CMD_PAUSE_BITS=       10,
     parameter CMD_DONE_BIT=         10,
-    
-    parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
-    parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers
-    parameter STATUS_DEPTH=         8,  // 256 cells, maybe just 16..64 are enough?
-    
-    parameter AXI_WR_ADDR_BITS =    13,
-    parameter AXI_RD_ADDR_BITS =    13,
-    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
-    parameter CONTROL_ADDR_MASK =   'h1400, // AXI write address of control registers
     parameter NUM_CYCLES_LOW_BIT=   'h6,    // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
 // TODO: put actual data    
     parameter NUM_CYCLES_00 =       2, // 2-cycle 000.003f
@@ -610,10 +603,10 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
     );
 
     status_read #(
-        .STATUS_ADDR(STATUS_ADDR),
-        .STATUS_ADDR_MASK(STATUS_ADDR_MASK),
-        .AXI_RD_ADDR_BITS(AXI_RD_ADDR_BITS),
-        .STATUS_DEPTH(STATUS_DEPTH)
+        .STATUS_ADDR      (STATUS_ADDR),
+        .STATUS_ADDR_MASK (STATUS_ADDR_MASK),
+        .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
+        .STATUS_DEPTH     (STATUS_DEPTH)
     ) status_read_i (
         .rst              (axi_rst), // input
         .clk              (mclk), // input
@@ -647,8 +640,6 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
 
     /* Instance template for module mcntrl393 */
     mcntrl393 #(
-        .AXI_WR_ADDR_BITS                  (AXI_WR_ADDR_BITS),
-        .AXI_RD_ADDR_BITS                  (AXI_RD_ADDR_BITS),
         .MCONTR_WR_MASK                    (MCONTR_WR_MASK),
         .MCONTR_RD_MASK                    (MCONTR_RD_MASK),
         .MCONTR_CMD_WR_ADDR                (MCONTR_CMD_WR_ADDR),
@@ -662,6 +653,8 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .MCONTR_BUF3_WR_ADDR               (MCONTR_BUF3_WR_ADDR),
         .MCONTR_BUF4_RD_ADDR               (MCONTR_BUF4_RD_ADDR),
         .MCONTR_BUF4_WR_ADDR               (MCONTR_BUF4_WR_ADDR),
+        .AXI_WR_ADDR_BITS                  (AXI_WR_ADDR_BITS),
+        .AXI_RD_ADDR_BITS                  (AXI_RD_ADDR_BITS),
        
         .DLY_LD                            (DLY_LD),
         .DLY_LD_MASK                       (DLY_LD_MASK),

x393_testbench01.tf

@@ -466,6 +466,13 @@ assign bresp=                              x393_i.ps7_i.MAXIGP0BRESP;
         .MCONTR_BUF3_WR_ADDR               (MCONTR_BUF3_WR_ADDR),
         .MCONTR_BUF4_RD_ADDR               (MCONTR_BUF4_RD_ADDR),
         .MCONTR_BUF4_WR_ADDR               (MCONTR_BUF4_WR_ADDR),
+        .CONTROL_ADDR                      (CONTROL_ADDR),
+        .CONTROL_ADDR_MASK                 (CONTROL_ADDR_MASK),
+        .STATUS_ADDR                       (STATUS_ADDR),
+        .STATUS_ADDR_MASK                  (STATUS_ADDR_MASK),
+        .AXI_WR_ADDR_BITS                  (AXI_WR_ADDR_BITS),
+        .AXI_RD_ADDR_BITS                  (AXI_RD_ADDR_BITS),
+        .STATUS_DEPTH                      (STATUS_DEPTH),
         .DLY_LD                            (DLY_LD),
         .DLY_LD_MASK                       (DLY_LD_MASK),
         .MCONTR_PHY_0BIT_ADDR              (MCONTR_PHY_0BIT_ADDR),
@@ -535,13 +542,6 @@ assign bresp=                              x393_i.ps7_i.MAXIGP0BRESP;
         .SS_MOD_PERIOD                     (SS_MOD_PERIOD),
         .CMD_PAUSE_BITS                    (CMD_PAUSE_BITS),
         .CMD_DONE_BIT                      (CMD_DONE_BIT),
-        .STATUS_ADDR                       (STATUS_ADDR),
-        .STATUS_ADDR_MASK                  (STATUS_ADDR_MASK),
-        .STATUS_DEPTH                      (STATUS_DEPTH),
-        .AXI_WR_ADDR_BITS                  (AXI_WR_ADDR_BITS),
-        .AXI_RD_ADDR_BITS                  (AXI_RD_ADDR_BITS),
-        .CONTROL_ADDR                      (CONTROL_ADDR),
-        .CONTROL_ADDR_MASK                 (CONTROL_ADDR_MASK),
         .NUM_CYCLES_LOW_BIT                (NUM_CYCLES_LOW_BIT),
         .NUM_CYCLES_00                     (NUM_CYCLES_00),
         .NUM_CYCLES_01                     (NUM_CYCLES_01),
@@ -1149,6 +1149,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
                     )
                 ):
                 (WINDOW_WIDTH));
+           $display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
            write_block_scanline_chn(
             channel,
             (ii & 3),
@@ -1177,6 +1178,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
                         )
                     ):
                     (WINDOW_WIDTH));
+                $display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
                 write_block_scanline_chn(
                     channel,
                     (ii & 3),
@@ -1271,6 +1273,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
                  (ii == 0)); // synchronize sequence number - only first time, next just wait fro auto update
 // read block (if needed), for now just sikip  
                 if (show_data) begin
+                    $display("########### test_scanline_read block %d: channel=%d, @%t", ii, channel, $time);
                     read_block_buf_chn (
                         channel,
                         (ii & 3),
@@ -1339,6 +1342,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
         write_contol_register(test_mode_address,            TEST01_START_FRAME);
     
         for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
+            $display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
             write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
                 channel, // channel
                 (ii & 3),
@@ -1357,6 +1361,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
                     'hf << 16,  // mask for the 4-bit page number
                     1, // not equal to
                     (ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
+                $display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
                 write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
                     channel, // channel
                     (ii & 3),
@@ -1447,6 +1452,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
                 1, // not equal to
                 (ii == 0)); // synchronize sequence number - only first time, next just wait fro auto update
                 if (show_data) begin 
+                    $display("########### test_tiled_read block %d: channel=%d, @%t", ii, channel, $time);
                     read_block_buf_chn (
                         channel,
                         (ii & 3),