copied CVC-related changes from master branch

axi/axibram_write.v

@@ -21,7 +21,9 @@
  *******************************************************************************/
 //`define DEBUG_FIFO 1 
 `include "system_defines.vh" 
-`undef DEBUG_FIFO
+`ifdef DEBUG_FIFO
+  `undef DEBUG_FIFO
+`endif
 module  axibram_write #(
     parameter ADDRESS_BITS = 10 // number of memory address bits
 )(

ddr3/4096Mb_ddr3_parameters.vh

@@ -477,10 +477,22 @@
     parameter TDQSL            =    0.45; // tDQSL      tCK   DQS input Low Pulse Width
     parameter TWPRE            =    0.90; // tWPRE      tCK   DQS Write Preamble
     parameter TWPST            =    0.30; // tWPST      tCK   DQS Write Postamble
+`ifdef CVC
+    integer TZQCS;
+    integer TZQINIT;
+    integer TZQOPER;
+    initial
+    begin
+        TZQCS   =  max( 64, ceil( 80000/TCK_MIN)); // tZQCS      tCK   ZQ Cal (Short) time
+        TZQINIT =  max(512, ceil(640000/TCK_MIN)); // tZQinit    tCK   ZQ Cal (Long) time
+        TZQOPER =  max(256, ceil(320000/TCK_MIN)); // tZQoper    tCK   ZQ Cal (Long) time
+    end
+`else
     // Command and Address
     integer TZQCS              =  max( 64, ceil( 80000/TCK_MIN)); // tZQCS      tCK   ZQ Cal (Short) time
     integer TZQINIT            =  max(512, ceil(640000/TCK_MIN)); // tZQinit    tCK   ZQ Cal (Long) time
     integer TZQOPER            =  max(256, ceil(320000/TCK_MIN)); // tZQoper    tCK   ZQ Cal (Long) time
+`endif
     parameter TCCD             =       4; // tCCD       tCK   Cas to Cas command delay
     parameter TCCD_DG          =       2; // tCCD_DG    tCK   Cas to Cas command delay to different group
     parameter TRAS_MAX         =    60e9; // tRAS       ps    Maximum Active to Precharge command time

ddr3/ddr3.v

@@ -529,9 +529,21 @@ module ddr3 (
     integer                rdqen_cntr;
     integer                rdq_cntr;
     
-    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});
-    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
-    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});
+`ifdef CVC
+    wire [DQS_BITS-1:0] dqs_in0 = dqs_out_dly;
+    wire [DQS_BITS-1:0] dqs_in1 = ~dqs_out_dly;
+    wire [DQ_BITS-1:0] dq_in2 = dq_out_dly;
+    wire [DQS_BITS-1:0] dqs_en0 = dqs_out_en_dly & {DQS_BITS{out_en}};
+    wire [DQS_BITS-1:0] dqs_en1 = dqs_out_en_dly & {DQS_BITS{out_en}};
+    wire [DQ_BITS-1:0] dq_en2 = dq_out_en_dly & {DQS_BITS{out_en}};
+    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,   dqs_in0  ,dqs_en0  );
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n, dqs_in1  ,dqs_en1 );
+    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,  dq_in2    , dq_en2 );
+`else
+    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}     }); 
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}     }); 
+    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}     });
+`endif
     assign tdqs_n = {DQS_BITS{1'bz}};
 
     initial begin
@@ -539,8 +551,11 @@ module ddr3 (
             $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);
         if ((1<<BO_BITS) > BL_MAX) 
             $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
-
+`ifdef CVC
+        $timeformat (-12, 1, " ps", 10);
+`else
         $timeformat (-12, 1, " ps", 1);
+`endif
         seed = RANDOM_SEED;
 
         ck_cntr = 0;
@@ -644,6 +659,9 @@ module ddr3 (
         integer offset; 
         reg [1024:1] msg;
         reg [RFF_BITS:1] read_value;
+`ifdef CVC
+        reg [RFF_BITS*2+8:1] read_str;
+`endif
     
         begin
             offset = index * RFF_CHUNK;
@@ -654,8 +672,12 @@ module ddr3 (
                 $display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
                 $finish;
             end
-        
+`ifdef CVC
+            code = $fgets(read_str, fd);
+            code = $sscanf(read_str, "%h", read_value);
+`else
             code = $fscanf(fd, "%z", read_value);
+`endif
             // $fscanf returns number of items read
             if (code != 1)
             begin
@@ -673,12 +695,21 @@ module ddr3 (
             * Use 0 in bit 1 as indicator that invalid data has been read.
             * A true 0 is encoded as Z.
             */
+`ifdef CVC
+            if (read_value[4:1] === 4'bzzzz)
+                // true 0 encoded as Z, data is valid
+                read_value[4:1] = 4'b0000;
+            else if (read_value[4:1] === 4'b0000)
+                // read from file section that has not been written
+                read_value = 'hx;
+`else
             if (read_value[1] === 1'bz)
                 // true 0 encoded as Z, data is valid
                 read_value[1] = 1'b0;
             else if (read_value[1] === 1'b0)
                 // read from file section that has not been written
                 read_value = 'hx;
+`endif
 
             read_from_file = read_value;
         end
@@ -708,6 +739,15 @@ module ddr3 (
                 $finish;
             end
         
+`ifdef CVC
+            // encode a valid data 
+            if (data[4:1] === 4'bzzzz)
+                data[4:1] = 4'bxxxx;
+            else if (data[4:1] === 4'b0000)
+                data[4:1] = 4'bzzzz;
+
+            $fwrite( fd, "%h", data );
+`else
             // encode a valid data 
             if (data[1] === 1'bz)
                 data[1] = 1'bx;
@@ -715,6 +755,7 @@ module ddr3 (
                 data[1] = 1'bz;
 
             $fwrite( fd, "%z", data );
+`endif
         end
     endtask
 `else
@@ -2229,7 +2270,11 @@ module ddr3 (
                             $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
 
                         // check tCL
+`ifdef CVC
+                        if ((tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) && (tm_ck_neg > $time))
+`else
                         if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) 
+`endif
                             $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
                         if (tcl_avg < TCL_AVG_MIN*tck_avg) 
                             $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);

includes/x393_tasks_status.vh

@@ -19,7 +19,41 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
 
- 
+// CVC bug that is supposed to be already fixed 
+`ifdef CVC 
+task wait_status_condition;
+    input [STATUS_DEPTH-1:0] status_address;
+    input [29:0] status_control_address;
+    input  [1:0] status_mode;
+    input [25:0] pattern;        // bits as in read registers
+    input [25:0] mask;           // which bits to compare
+    input        invert_match;   // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
+    input        wait_seq;
+    reg          match;
+    reg    [5:0] seq_num;
+    reg [31:0] pattern1;
+    reg [31:0] mask1;
+    begin
+        WAITING_STATUS = 1;
+        pattern1 = {6'h0,pattern};
+        mask1 = {6'h0,mask};
+        for (match=0; !match; match = invert_match ^ (((registered_rdata ^ pattern1) & mask1)==0)) begin
+            read_status(status_address);
+            if (wait_seq) begin 
+                seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
+                write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
+                read_status(status_address);
+                while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
+                    read_status(status_address);
+                end
+            end
+        pattern1 = {6'h0,pattern};
+        mask1 = {6'h0,mask};
+        end
+        WAITING_STATUS = 0;
+    end
+endtask
+`else
 task wait_status_condition;
     input [STATUS_DEPTH-1:0] status_address;
     input [29:0] status_control_address;
@@ -46,6 +80,7 @@ task wait_status_condition;
         WAITING_STATUS = 0;
     end
 endtask    
+`endif
 /*
 task wait_status_condition_auto; // assumes status is already updating
     input [STATUS_DEPTH-1:0] status_address;

system_defines.vh

   // This file may be used to define same pre-processor macros to be included into each parsed file
 `ifndef SYSTEM_DEFINES
   `define SYSTEM_DEFINES
+  
+// Enviroment-dependent options
+  `ifdef IVERILOG
+    `define SIMULATION
+    `define OPEN_SOURCE_ONLY
+  `else
+    `ifdef CVC
+      `define SIMULATION
+      `define OPEN_SOURCE_ONLY
+    `endif // CVC
+  `endif // IVERILOG
+  
 // will not use simultaneous reset in shift registers, just and input data with ~rst  
  `define SHREG_SEQUENTIAL_RESET 1
 // synthesis does to recognize global clock as G input of the primitive latch 

wrap/idelay_fine_pipe.v

@@ -44,11 +44,11 @@ module  idelay_fine_pipe
         if (rst)      fdly <= DELAY_VALUE[2:0];
         else if (set) fdly <= fdly_pre;
     end
-    `ifdef IVERILOG
+    `ifdef SIMULATION
         always @ (fdly_pre) begin
             if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
-    `endif
+    `endif // SIMULATION
 `ifndef IGNORE_ATTR
     (* IODELAY_GROUP = IODELAY_GRP *)
 `endif    

wrap/iserdes_mem.v

@@ -36,7 +36,7 @@ module  iserdes_mem #
     output       comb_out  // combinatorial output copies selected input to be used in the fabric     
 );
 
-`ifndef IVERILOG  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           
+`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )           
      ISERDESE2 #(
          .DATA_RATE                  ("DDR"),
          .DATA_WIDTH                 (4),
@@ -88,7 +88,7 @@ module  iserdes_mem #
          .SHIFTIN1                   (1'b0),
          .SHIFTIN2                   (1'b0)
          );
-`else // Simulating, use Virtex 6 module that does not have encrypted functionality
+`else //  OPEN_SOURCE_ONLY : Simulating, use Virtex 6 module that does not have encrypted functionality
      ISERDESE1 #(
          .DATA_RATE                  ("DDR"),
          .DATA_WIDTH                 (4),

wrap/odelay_fine_pipe.v

@@ -43,11 +43,11 @@ module  odelay_fine_pipe
         if (rst)      fdly <= DELAY_VALUE[2:0];
         else if (set) fdly <= fdly_pre;
     end
-    `ifdef IVERILOG
+    `ifdef SIMULATION
         always @ (fdly_pre) begin
             if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
-    `endif
+    `endif //SIMULATION
  
 `ifndef IGNORE_ATTR
     (* IODELAY_GROUP = IODELAY_GRP *)

x393_testbench01.tf

@@ -53,13 +53,26 @@ module  x393_testbench01 #(
 );
 `ifdef IVERILOG              
 //    $display("IVERILOG is defined");
+    `ifdef NON_VDT_ENVIROMENT
+        parameter lxtname="x393.lxt";
+    `else
         `include "IVERILOG_INCLUDE.v"
-`else
+    `endif // NON_VDT_ENVIROMENT
+`else // IVERILOG
 //    $display("IVERILOG is not defined");
+    `ifdef CVC
+        `ifdef NON_VDT_ENVIROMENT
+            parameter lxtname = "x393.fst";
+        `else // NON_VDT_ENVIROMENT
+            `include "IVERILOG_INCLUDE.v"
+        `endif // NON_VDT_ENVIROMENT
+    `else
         parameter lxtname = "x393.lxt";
-`endif
+    `endif // CVC
+`endif // IVERILOG
 `define DEBUG_WR_SINGLE 1  
 `define DEBUG_RD_DATA 1  
+
 //`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
 `include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
 `include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used