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Commit 8dd16a59 authored by Andrey Filippov's avatar Andrey Filippov
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Preparing for the HiSPi sensor testing

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.project
View file @ 8dd16a59
...@@ -62,47 +62,47 @@ ...@@ -62,47 +62,47 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150725144907208.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151105233458943.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
......
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 8dd16a59
...@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000 ...@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@-> VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_123_SkipSnapshotSynth=true
......
ddrc_test01.xdc
View file @ 8dd16a59
...@@ -203,10 +203,6 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}] ...@@ -203,10 +203,6 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}] set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging #not yet used, just for debugging
# input MEMCLK, // to keep PS7 signals from "optimization" # input MEMCLK, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}] set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
......
fpga_version.vh
View file @ 8dd16a59
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%) // parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
// parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range) // parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
// parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range) // parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
// parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong! // parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
......
includes/x393_parameters.vh
View file @ 8dd16a59
...@@ -143,15 +143,11 @@ ...@@ -143,15 +143,11 @@
`else `else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif `endif
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new
...@@ -480,7 +476,6 @@ ...@@ -480,7 +476,6 @@
//sensor_i2c_io other parameters //sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12, parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI //`ifndef HISPI
...@@ -516,7 +511,6 @@ ...@@ -516,7 +511,6 @@
parameter integer IDELAY_VALUE = 0, parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
`ifdef use200Mhz `ifdef use200Mhz
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
...@@ -542,27 +536,35 @@ ...@@ -542,27 +536,35 @@
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
// parameter PXD_IOSTANDARD = "LVCMOS25",
// parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`else `else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 // parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR", // parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR", parameter BUF_IPCLK2X_SENS0 = "BUFIO", /// "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR", parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 parameter BUF_IPCLK_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR", parameter BUF_IPCLK2X_SENS2 = "BUFIO", ///"BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR", parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999) parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
...@@ -574,14 +576,26 @@ ...@@ -574,14 +576,26 @@
//`ifdef HISPI //`ifdef HISPI
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK0= "TRUE",
parameter HISPI_DELAY_CLK1= "TRUE",
parameter HISPI_DELAY_CLK2= "TRUE",
parameter HISPI_DELAY_CLK3= "TRUE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", // parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif DIFF_HSTL_II_18
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60 parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
...@@ -801,12 +815,43 @@ ...@@ -801,12 +815,43 @@
parameter DEBUG_SET_STATUS = 'h2, // program status (mode 3?)// SuppressThisWarning VEditor parameter DEBUG_SET_STATUS = 'h2, // program status (mode 3?)// SuppressThisWarning VEditor
parameter DEBUG_CMD_LATENCY = 2, // >0 extra registers in the debug_sl (distriburted in parallel)// SuppressThisWarning VEditor parameter DEBUG_CMD_LATENCY = 2, // >0 extra registers in the debug_sl (distriburted in parallel)// SuppressThisWarning VEditor
//`endif //`endif
// setting system clock generated by a single PLL
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200 parameter MULTICLK_IN_PERIOD = 20, // 50MHz
parameter DIVCLK_DIVIDE_AXIHP = 1, parameter MULTICLK_DIVCLK = 1, //
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter MULTICLK_MULT = 24, //1200MHz
parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock `ifdef use200Mhz
parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE" parameter MULTICLK_DIV_DLYREF = 6, // 6 - 200MHz I/O delay reference clock (4 - 300MHz)
`else
parameter MULTICLK_DIV_DLYREF = 4, // 4 - 300MHz I/O delay reference clock (6 - 200MHz)
`endif
parameter MULTICLK_DIV_AXIHP = 8, // 150 MHz for AXI HP
`ifdef USE_XCLK2X
parameter MULTICLK_DIV_XCLK = 12, // 100 MHz for compressor
parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
`else
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
`endif
parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
// Additional parameters for multi-clock PLL (phases and buffer types)
parameter MULTICLK_PHASE_FB = 0.0,
parameter MULTICLK_PHASE_DLYREF = 0.0,
parameter MULTICLK_BUF_DLYREF = "BUFG",
parameter MULTICLK_PHASE_AXIHP = 0.0,
parameter MULTICLK_BUF_AXIHP = "BUFG",
parameter MULTICLK_PHASE_XCLK = 0.0,
parameter MULTICLK_BUF_XCLK = "BUFG",
`ifdef USE_XCLK2X
parameter MULTICLK_PHASE_XCLK2X = 0.0,
parameter MULTICLK_BUF_XCLK2X = "BUFG",
`endif
parameter MULTICLK_PHASE_SYNC = 0.0,
parameter MULTICLK_BUF_SYNC = "BUFG",
// parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
// parameter DIVCLK_DIVIDE_AXIHP = 1,
// parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
// parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
// parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
`ifdef HISPI `ifdef HISPI
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444 parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444
parameter DIVCLK_DIVIDE_PCLK = 1, parameter DIVCLK_DIVIDE_PCLK = 1,
...@@ -824,45 +869,39 @@ ...@@ -824,45 +869,39 @@
parameter BUF_CLK1X_PCLK = "BUFG", parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG", parameter BUF_CLK1X_PCLK2X = "BUFG",
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
`else
parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
`endif
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz // parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1, // parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz // parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_SYNC = 10, // 100 MHz //`ifdef USE_XCLK2X
parameter BUF_CLK1X_SYNC = "BUFG", // parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
//`else
// parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
//`endif
// parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
// parameter PHASE_CLK2X_XCLK = 0.000,
// parameter BUF_CLK1X_XCLK = "BUFG",
// parameter BUF_CLK1X_XCLK2X = "BUFG",
// parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
// parameter DIVCLK_DIVIDE_SYNC = 1,
// parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
// parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
// parameter BUF_CLK1X_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE", parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_DELAY_VALUE = "0",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE", parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IFD_DELAY_VALUE = "AUTO",
parameter MEMCLK_IOSTANDARD = "SSTL15", parameter MEMCLK_IOSTANDARD = "SSTL15",
parameter FFCLK0_CAPACITANCE = "DONT_CARE", parameter FFCLK0_CAPACITANCE = "DONT_CARE",
parameter FFCLK0_DIFF_TERM = "FALSE", parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_DQS_BIAS = "FALSE",
parameter FFCLK0_IBUF_DELAY_VALUE = "0",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE", parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK0_IOSTANDARD = "RSDS_25", parameter FFCLK0_IOSTANDARD = "RSDS_25",
parameter FFCLK1_CAPACITANCE = "DONT_CARE", parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE", parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_DQS_BIAS = "FALSE",
parameter FFCLK1_IBUF_DELAY_VALUE = "0",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE", parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK1_IOSTANDARD = "RSDS_25" parameter FFCLK1_IOSTANDARD = "RSDS_25"
......
memctrl/mcntrl393.v
View file @ 8dd16a59
...@@ -142,15 +142,11 @@ module mcntrl393 #( ...@@ -142,15 +142,11 @@ module mcntrl393 #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
...@@ -251,7 +247,7 @@ module mcntrl393 #( ...@@ -251,7 +247,7 @@ module mcntrl393 #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// programming interface // programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
...@@ -402,9 +398,6 @@ module mcntrl393 #( ...@@ -402,9 +398,6 @@ module mcntrl393 #(
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU //, inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
...@@ -1814,8 +1807,6 @@ module mcntrl393 #( ...@@ -1814,8 +1807,6 @@ module mcntrl393 #(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -1835,7 +1826,7 @@ module mcntrl393 #( ...@@ -1835,7 +1826,7 @@ module mcntrl393 #(
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.locked (locked), // output .locked (locked), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0] .cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input .cmd_stb (cmd_mcontr_stb), // input
......
memctrl/memctrl16.v
View file @ 8dd16a59
...@@ -115,15 +115,11 @@ module memctrl16 #( ...@@ -115,15 +115,11 @@ module memctrl16 #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
...@@ -144,7 +140,7 @@ module memctrl16 #( ...@@ -144,7 +140,7 @@ module memctrl16 #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// programming interface // programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
...@@ -541,8 +537,6 @@ module memctrl16 #( ...@@ -541,8 +537,6 @@ module memctrl16 #(
output SDDMU, // UDM I/O pad (actually only output) output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU //, inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data // temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
...@@ -903,8 +897,6 @@ end ...@@ -903,8 +897,6 @@ end
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -942,7 +934,7 @@ end ...@@ -942,7 +934,7 @@ end
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.locked (locked), // output .locked (locked), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), .idelay_ctrl_reset (idelay_ctrl_reset),
.cmd0_clk (cmd0_clk), // input .cmd0_clk (cmd0_clk), // input
......
memctrl/phy/mcontr_sequencer.v
View file @ 8dd16a59
...@@ -77,8 +77,6 @@ module mcontr_sequencer #( ...@@ -77,8 +77,6 @@ module mcontr_sequencer #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -118,7 +116,7 @@ module mcontr_sequencer #( ...@@ -118,7 +116,7 @@ module mcontr_sequencer #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk, sync reset (should not interrupt mclk!) input mrst, // @posedge mclk, sync reset (should not interrupt mclk!)
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
input cmd0_clk, input cmd0_clk,
...@@ -549,8 +547,6 @@ module mcontr_sequencer #( ...@@ -549,8 +547,6 @@ module mcontr_sequencer #(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -586,7 +582,7 @@ module mcontr_sequencer #( ...@@ -586,7 +582,7 @@ module mcontr_sequencer #(
.rst_in (rst_in), // input .rst_in (rst_in), // input
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.dly_data (dly_data[7:0]), // input[7:0] .dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0] .dly_addr (dly_addr[6:0]), // input[6:0]
......
memctrl/phy/phy_cmd.v
View file @ 8dd16a59
...@@ -33,8 +33,6 @@ module phy_cmd#( ...@@ -33,8 +33,6 @@ module phy_cmd#(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -73,7 +71,7 @@ module phy_cmd#( ...@@ -73,7 +71,7 @@ module phy_cmd#(
input rst_in, input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// inteface to control I/O delays and mmcm // inteface to control I/O delays and mmcm
input [7:0] dly_data, // delay value (3 LSB - fine delay) input [7:0] dly_data, // delay value (3 LSB - fine delay)
...@@ -377,8 +375,6 @@ module phy_cmd#( ...@@ -377,8 +375,6 @@ module phy_cmd#(
.BANDWIDTH ("OPTIMIZED"), .BANDWIDTH ("OPTIMIZED"),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -413,7 +409,7 @@ module phy_cmd#( ...@@ -413,7 +409,7 @@ module phy_cmd#(
.clk_div (clk_div), // output .clk_div (clk_div), // output
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.rst_in (rst_in), // input .rst_in (rst_in), // input
......
memctrl/phy/phy_top.v
View file @ 8dd16a59
...@@ -40,8 +40,6 @@ module phy_top #( ...@@ -40,8 +40,6 @@ module phy_top #(
// Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk // Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same) parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -78,7 +76,7 @@ module phy_top #( ...@@ -78,7 +76,7 @@ module phy_top #(
output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output
output mclk, // same as clk_div, through separate BUFG and static phase adjust output mclk, // same as clk_div, through separate BUFG and static phase adjust
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
input rst_in, // reset delays/serdes - global reset? input rst_in, // reset delays/serdes - global reset?
input ddr_rst, // active high - generate NRST to memory input ddr_rst, // active high - generate NRST to memory
...@@ -120,14 +118,9 @@ module phy_top #( ...@@ -120,14 +118,9 @@ module phy_top #(
output ps_rdy, output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out output [PHASE_WIDTH-1:0] ps_out
); );
assign locked_pll = 1; // not used anymore, reference clock generation moved to other module
reg rst= 1'b1; reg rst= 1'b1;
// always @(negedge clk_div or posedge rst_in) begin // Why is it @ negedge clk_div?
// if (rst_in) rst <= 1'b1;
// else rst <= 1'b0;
// end
// always @(negedge clk_div) begin // Why is it @ negedge clk_div?
always @(posedge clk_div) begin // Why is it @ negedge clk_div? always @(posedge clk_div) begin // Why is it @ negedge clk_div?
if (mrst) rst <= 1'b1; if (mrst) rst <= 1'b1;
else rst <= 1'b0; else rst <= 1'b0;
...@@ -137,27 +130,15 @@ module phy_top #( ...@@ -137,27 +130,15 @@ module phy_top #(
wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ; wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ; wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ; wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ;
wire clkfb_ref, clk_ref_pre; // wire clkfb_ref, clk_ref_pre;
// wire ref_clk; // 200MHz/300Mhz to calibrate I/O delays
// wire locked_mmcm,locked_pll, dly_ready, dci_ready;
// assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
wire clkin_stopped_mmcm; wire clkin_stopped_mmcm;
wire clkfb_stopped_mmcm; wire clkfb_stopped_mmcm;
reg dbg1=0; reg dbg1=0;
reg dbg2=0; reg dbg2=0;
/*
always @ (posedge rst_in or posedge mclk) begin
if (rst_in) dbg1 <= 0;
else dbg1 <= ~dbg1;
end
always @ (posedge rst_in or posedge clk_div) begin
if (rst_in) dbg2 <= 0;
else dbg2 <= ~dbg2;
end
*/
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) dbg1 <= 0; if (mrst) dbg1 <= 0;
else dbg1 <= ~dbg1; else dbg1 <= ~dbg1;
...@@ -316,10 +297,7 @@ BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre)); ...@@ -316,10 +297,7 @@ BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
//BUFIO clk_buf_i (.O(clk), .I(clk_pre)); //BUFIO clk_buf_i (.O(clk), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre)); BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) ); BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
//BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre)); ///BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
//assign ref_clk=clk_ref_pre;
//BUFH clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG mclk_i (.O(mclk),.I(mclk_pre) ); BUFG mclk_i (.O(mclk),.I(mclk_pre) );
mmcm_phase_cntr #( mmcm_phase_cntr #(
.PHASE_WIDTH (PHASE_WIDTH), .PHASE_WIDTH (PHASE_WIDTH),
...@@ -390,30 +368,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) ); ...@@ -390,30 +368,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.clkfb_stopped (clkfb_stopped_mmcm) // output .clkfb_stopped (clkfb_stopped_mmcm) // output
// output // output
); );
// Generate reference clock for the I/O delays
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_REF),
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_REF),
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_ref), // input
// .rst(rst), // input
.rst(rst_in), // input
.pwrdwn(1'b0), // input
.clkout0(clk_ref_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_ref), // output
.locked(locked_pll) // output
);
// Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset // Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset
assign idelay_ctrl_reset = rst || dly_rst; assign idelay_ctrl_reset = rst || dly_rst;
idelay_ctrl# ( idelay_ctrl# (
......
sensor/sens_10398.v
View file @ 8dd16a59
...@@ -76,18 +76,21 @@ module sens_10398 #( ...@@ -76,18 +76,21 @@ module sens_10398 #(
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// Other (non-HiSPi) sensor I/Os // Other (non-HiSPi) sensor I/Os
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT", // 1.8V single-ended parameter PXD_IOSTANDARD = "LVCMOS18", // 1.8V single-ended
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE", parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
...@@ -324,6 +327,8 @@ module sens_10398 #( ...@@ -324,6 +327,8 @@ module sens_10398 #(
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -356,16 +361,43 @@ module sens_10398 #( ...@@ -356,16 +361,43 @@ module sens_10398 #(
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output .clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output .clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
); );
/*
obufds #( obufds #(
.CAPACITANCE("DONT_CARE"), .CAPACITANCE("DONT_CARE"),
.IOSTANDARD("DEFAULT"), .IOSTANDARD(PXD_IOSTANDARD), // not diff, just opposite phase signals
.SLEW("SLOW") .SLEW("SLOW")
) obufds_i ( ) obufds_i (
.o (sens_ext_clk_p), // output .o (sens_ext_clk_p), // output
.ob (sens_ext_clk_n), // output .ob (sens_ext_clk_n), // output
.i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input .i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input
); );
*/
// reg [1:0] ext_clk_r;
// always @(posedge pclk) begin
// ext_clk_r <= {pxd_clk_cntr[PXD_CLK_DIV_BITS-1], !pxd_clk_cntr[PXD_CLK_DIV_BITS-1]};
// end
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_clk_p_i (
.O (sens_ext_clk_p), // output
.I (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) //ext_clk_r[0]) // input
);
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_clk_n_i (
.O (sens_ext_clk_n), // output
.I (iarst) // ~pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // ext_clk_r[1]) // input
);
// Probe programmable/ control PROGRAM pin // Probe programmable/ control PROGRAM pin
reg [1:0] xpgmen_d; reg [1:0] xpgmen_d;
reg force_senspgm=0; reg force_senspgm=0;
......
sensor/sens_hispi12l4.v
View file @ 8dd16a59
...@@ -46,13 +46,15 @@ module sens_hispi12l4#( ...@@ -46,13 +46,15 @@ module sens_hispi12l4#(
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot) parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
)( )(
input pclk, // global clock input, pixel rate (220MHz for MT9F002) input pclk, // global clock input, pixel rate (220MHz for MT9F002)
...@@ -112,6 +114,14 @@ module sens_hispi12l4#( ...@@ -112,6 +114,14 @@ module sens_hispi12l4#(
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -124,6 +134,7 @@ module sens_hispi12l4#( ...@@ -124,6 +134,7 @@ module sens_hispi12l4#(
.mrst (mrst), // input .mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0] .phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input .set_phase (set_clk_phase), // input
.load (ld_idelay), // input
.rst_mmcm (rst_mmcm), // input .rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input .clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input .clk_n (sns_clkn), // input
......
sensor/sens_hispi_clock.v
View file @ 8dd16a59
...@@ -23,9 +23,7 @@ ...@@ -23,9 +23,7 @@
module sens_hispi_clock#( module sens_hispi_clock#(
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors) parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW" parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
...@@ -40,22 +38,28 @@ module sens_hispi_clock#( ...@@ -40,22 +38,28 @@ module sens_hispi_clock#(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// Used with delay
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)( )(
input mclk, input mclk,
input mrst, input mrst,
input [7:0] phase, input [7:0] phase,
input set_phase, input set_phase,
input load, // only used when delay, not phase
input rst_mmcm, input rst_mmcm,
input clp_p, input clp_p,
input clk_n, input clk_n,
...@@ -72,6 +76,15 @@ module sens_hispi_clock#( ...@@ -72,6 +76,15 @@ module sens_hispi_clock#(
wire clk_fb; wire clk_fb;
wire prst = mrst; wire prst = mrst;
wire clk_in; wire clk_in;
wire clk_int;
wire set_phase_w = (HISPI_DELAY_CLK == "TRUE") ? 1'b0: set_phase;
wire [7:0] phase_w = (HISPI_DELAY_CLK == "TRUE") ? 8'b0: phase;
wire ps_rdy_w;
wire [7:0] ps_out_w;
assign ps_rdy = (HISPI_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (HISPI_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
ibufds_ibufgds #( ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE), .CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM), .DIFF_TERM (HISPI_DIFF_TERM),
...@@ -81,69 +94,127 @@ module sens_hispi_clock#( ...@@ -81,69 +94,127 @@ module sens_hispi_clock#(
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE), .IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD) .IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i ( ) ibufds_ibufgds0_i (
.O (clk_in), // output .O (clk_int), // output
.I (clp_p), // input .I (clp_p), // input
.IB (clk_n) // input .IB (clk_n) // input
); );
generate
if (HISPI_DELAY_CLK == "TRUE") begin
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) clk_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_phase),
.ld (load),
.delay (phase[4:0]),
.data_in (clk_int),
.data_out (clk_in)
);
end else begin
assign clk_in = clk_int;
end
endgenerate
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock // generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor) // received from the sensor (may need to reset MMCM after resetting sensor)
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH), generate
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR), if (HISPI_MMCM == "TRUE") begin
.BANDWIDTH (SENS_BANDWIDTH), mmcm_phase_cntr #(
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4 .PHASE_WIDTH (SENS_PHASE_WIDTH),
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), .CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR), .BANDWIDTH (SENS_BANDWIDTH),
.CLKOUT0_PHASE (IPCLK_PHASE), .CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
.CLKOUT1_PHASE (IPCLK2X_PHASE), .DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS("FALSE"), .CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT0_PHASE (IPCLK_PHASE),
.CLKOUT1_USE_FINE_PS ("TRUE"), .CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR * 2), // 6 // 8.000), .CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR ), // 3 // 4), .CLKOUT0_USE_FINE_PS ("TRUE"),
.COMPENSATION ("ZHOLD"), .CLKOUT1_USE_FINE_PS ("TRUE"),
.REF_JITTER1 (SENS_REF_JITTER1), .CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR * 2), // 6 // 8.000),
.REF_JITTER2 (SENS_REF_JITTER2), .CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR ), // 3 // 4),
.SS_EN (SENS_SS_EN), .COMPENSATION ("ZHOLD"),
.SS_MODE (SENS_SS_MODE), .REF_JITTER1 (SENS_REF_JITTER1),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .REF_JITTER2 (SENS_REF_JITTER2),
.STARTUP_WAIT ("FALSE") .SS_EN (SENS_SS_EN),
.SS_MODE (SENS_SS_MODE),
) mmcm_phase_cntr_i ( .SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.clkin1 (clk_in), // input .STARTUP_WAIT ("FALSE")
.clkin2 (1'b0), // input ) mmcm_or_pll_i (
.sel_clk2 (1'b0), // input .clkin1 (clk_in), // input
.clkfbin (clk_fb), // input .clkin2 (1'b0), // input
.rst (rst_mmcm), // input .sel_clk2 (1'b0), // input
.pwrdwn (1'b0), // input .clkfbin (clk_fb), // input
.psclk (mclk), // input .rst (rst_mmcm), // input
.ps_we (set_phase), // input .pwrdwn (1'b0), // input
.ps_din (phase), // input[7:0]
.ps_ready (ps_rdy), // output .psclk (mclk), // input
.ps_dout (ps_out), // output[7:0] reg .ps_we (set_phase_w), // input
.clkout0 (ipclk_pre), // output .ps_din (phase_w), // input[7:0]
.clkout1 (ipclk2x_pre), // output .ps_ready (ps_rdy_w), // output
.clkout2(), // output .ps_dout (ps_out_w), // output[7:0] reg
.clkout3(), // output
.clkout4(), // output .clkout0 (ipclk_pre), // output
.clkout5(), // output .clkout1 (ipclk2x_pre), // output
.clkout6(), // output .clkout2(), // output
.clkout0b(), // output .clkout3(), // output
.clkout1b(), // output .clkout4(), // output
.clkout2b(), // output .clkout5(), // output
.clkout3b(), // output .clkout6(), // output
.clkfbout (clk_fb), // output .clkout0b(), // output
.clkfboutb(), // output .clkout1b(), // output
.locked (locked_pxd_mmcm), .clkout2b(), // output
.clkin_stopped (clkin_pxd_stopped_mmcm), // output .clkout3b(), // output
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output .clkfbout (clk_fb), // output
// output .clkfboutb(), // output
); .locked (locked_pxd_mmcm),
.clkin_stopped (clkin_pxd_stopped_mmcm), // output
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
// output
);
end else begin
pll_base #(
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (IPCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR * 2), // 6 // 8.000),
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR ), // 3 // 4),
.REF_JITTER1 (SENS_REF_JITTER1),
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin (clk_in), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.clkout0 (ipclk_pre), // output
.clkout1 (ipclk2x_pre), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout (clk_fb), // output
.locked (locked_pxd_mmcm)
// output
);
assign clkin_pxd_stopped_mmcm = 0;
assign clkfb_pxd_stopped_mmcm = 0;
assign ps_rdy_w = 1;
assign ps_out_w = 0; // alternatively - register delay written
end
endgenerate
generate generate
if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre)); if (BUF_IPCLK == "BUFR2") BUFR #(.BUFR_DIVIDE(2)) clk1x_i (.O(ipclk), .I(ipclk2x_pre), .CE(1'b1), .CLR(rst_mmcm));
else if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre)); else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst)); else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre)); else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre));
......
sensor/sens_hispi_din.v
View file @ 8dd16a59
...@@ -33,7 +33,7 @@ module sens_hispi_din #( ...@@ -33,7 +33,7 @@ module sens_hispi_din #(
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)( )(
input mclk, input mclk,
input mrst, input mrst,
......
sensor/sensor_channel.v
View file @ 8dd16a59
...@@ -181,7 +181,6 @@ module sensor_channel#( ...@@ -181,7 +181,6 @@ module sensor_channel#(
//sensor_i2c_io other parameters //sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12, parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI `ifndef HISPI
...@@ -197,7 +196,6 @@ module sensor_channel#( ...@@ -197,7 +196,6 @@ module sensor_channel#(
parameter integer IDELAY_VALUE = 0, parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0, parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE", parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
...@@ -219,12 +217,16 @@ module sensor_channel#( ...@@ -219,12 +217,16 @@ module sensor_channel#(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
parameter BUF_IPCLK = "BUFR", parameter BUF_IPCLK = "BUFR",
...@@ -240,13 +242,15 @@ module sensor_channel#( ...@@ -240,13 +242,15 @@ module sensor_channel#(
`ifdef HISPI `ifdef HISPI
,parameter HISPI_MSB_FIRST = 0, ,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
...@@ -266,12 +270,16 @@ module sensor_channel#( ...@@ -266,12 +270,16 @@ module sensor_channel#(
input prst, // @posedge pclk, sync reset input prst, // @posedge pclk, sync reset
// I/O pads, pin names match circuit diagram // I/O pads, pin names match circuit diagram
inout [7:0] sns_dp,
inout [7:0] sns_dn,
`ifdef HISPI `ifdef HISPI
input [3:0] sns_dp,
input [3:0] sns_dn,
inout [7:4] sns_dp74,
inout [7:4] sns_dn74,
input sns_clkp, input sns_clkp,
input sns_clkn, input sns_clkn,
`else `else
inout [7:0] sns_dp,
inout [7:0] sns_dn,
inout sns_clkp, inout sns_clkp,
inout sns_clkn, inout sns_clkn,
`endif `endif
...@@ -732,6 +740,8 @@ module sensor_channel#( ...@@ -732,6 +740,8 @@ module sensor_channel#(
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -763,16 +773,16 @@ module sensor_channel#( ...@@ -763,16 +773,16 @@ module sensor_channel#(
.sns_dn (sns_dn[3:0]), // input[3:0] .sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input .sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input .sns_clkn (sns_clkn), // input
.sens_ext_clk_p (sns_dp[6]), // output .sens_ext_clk_p (sns_dp74[6]), // output
.sens_ext_clk_n (sns_dn[6]), // output .sens_ext_clk_n (sns_dn74[6]), // output
.sns_pgm (sns_pg), // inout .sns_pgm (sns_pg), // inout
.sns_ctl_tck (sns_ctl), // output .sns_ctl_tck (sns_ctl), // output
.sns_mrst (sns_dp[7]), // output .sns_mrst (sns_dp74[7]), // output
.sns_arst_tms (sns_dn[7]), // output .sns_arst_tms (sns_dn74[7]), // output
.sns_gp0_tdi (sns_dp[5]), // output .sns_gp0_tdi (sns_dp74[5]), // output
.sns_gp1 (sns_dn[5]), // output .sns_gp1 (sns_dn74[5]), // output
.sns_flash_tdo (sns_dp[4]), // input .sns_flash_tdo (sns_dp74[4]), // input
.sns_shutter_done (sns_dn[4]), // input .sns_shutter_done (sns_dn74[4]), // input
.pxd (pxd), // output[11:0] .pxd (pxd), // output[11:0]
.hact (hact), // output .hact (hact), // output
.sof (sof), // output .sof (sof), // output
...@@ -806,7 +816,6 @@ module sensor_channel#( ...@@ -806,7 +816,6 @@ module sensor_channel#(
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD), .PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
...@@ -819,6 +828,7 @@ module sensor_channel#( ...@@ -819,6 +828,7 @@ module sensor_channel#(
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE), .IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE), .IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK), .BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X), .BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), .SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
......
sensor/sensor_i2c_io.v
View file @ 8dd16a59
...@@ -56,7 +56,11 @@ module sensor_i2c_io#( ...@@ -56,7 +56,11 @@ module sensor_i2c_io#(
// I/O parameters // I/O parameters
parameter integer SENSI2C_DRIVE = 12, parameter integer SENSI2C_DRIVE = 12,
parameter SENSI2C_IBUF_LOW_PWR = "TRUE", parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT", `ifdef HISPI
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
parameter SENSI2C_SLEW = "SLOW" parameter SENSI2C_SLEW = "SLOW"
)( )(
input mrst, // @mclk input mrst, // @mclk
......
sensor/sensors393.v
View file @ 8dd16a59
...@@ -181,7 +181,6 @@ module sensors393 #( ...@@ -181,7 +181,6 @@ module sensors393 #(
//sensor_i2c_io other parameters //sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12, parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI `ifndef HISPI
...@@ -215,7 +214,6 @@ module sensors393 #( ...@@ -215,7 +214,6 @@ module sensors393 #(
parameter integer IDELAY_VALUE = 0, parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0, parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE", parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
...@@ -235,12 +233,16 @@ module sensors393 #( ...@@ -235,12 +233,16 @@ module sensors393 #(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
// parameter BUF_IPCLK = "BUFR", // parameter BUF_IPCLK = "BUFR",
// parameter BUF_IPCLK2X = "BUFR", // parameter BUF_IPCLK2X = "BUFR",
...@@ -266,13 +268,21 @@ module sensors393 #( ...@@ -266,13 +268,21 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
,parameter HISPI_MSB_FIRST = 0, ,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK0= "FALSE",
parameter HISPI_DELAY_CLK1= "FALSE",
parameter HISPI_DELAY_CLK2= "FALSE",
parameter HISPI_DELAY_CLK3= "FALSE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
...@@ -301,12 +311,16 @@ module sensors393 #( ...@@ -301,12 +311,16 @@ module sensors393 #(
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
// I/O pads, pin names match circuit diagram (each sensor) // I/O pads, pin names match circuit diagram (each sensor)
inout [31:0] sns_dp,
inout [31:0] sns_dn,
`ifdef HISPI `ifdef HISPI
inout [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode input [15:0] sns_dp,
inout [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode input [15:0] sns_dn,
inout [15:0] sns_dp74,
inout [15:0] sns_dn74,
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`else `else
inout [31:0] sns_dp,
inout [31:0] sns_dn,
inout [3:0] sns_clkp, inout [3:0] sns_clkp,
inout [3:0] sns_clkn, inout [3:0] sns_clkn,
`endif `endif
...@@ -580,6 +594,10 @@ module sensors393 #( ...@@ -580,6 +594,10 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST), ,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -599,11 +617,19 @@ module sensors393 #( ...@@ -599,11 +617,19 @@ module sensors393 #(
`endif `endif
.mrst (mrst), // input .mrst (mrst), // input
.prst (prst), // input .prst (prst), // input
`ifdef HISPI
.sns_dp (sns_dp[i * 4 +: 4]), // input[3:0]
.sns_dn (sns_dn[i * 4 +: 4]), // input[3:0]
.sns_dp74 (sns_dp74[i * 4 +: 4]), // input[3:0]
.sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0]
.sns_clkp (sns_clkp[i]), // input
.sns_clkn (sns_clkn[i]), // input
`else
.sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0] .sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0]
.sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0] .sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0]
.sns_clkp (sns_clkp[i]), // inout .sns_clkp (sns_clkp[i]), // inout
.sns_clkn (sns_clkn[i]), // inout .sns_clkn (sns_clkn[i]), // inout
`endif
.sns_scl (sns_scl[i]), // inout .sns_scl (sns_scl[i]), // inout
.sns_sda (sns_sda[i]), // inout .sns_sda (sns_sda[i]), // inout
.sns_ctl (sns_ctl[i]), // inout .sns_ctl (sns_ctl[i]), // inout
......
system_defines.vh
View file @ 8dd16a59
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI `define HISPI
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
// `define USE_XCLK2X // `define USE_XCLK2X
......
unisims_extra/IBUFG.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: IBUFG
* Date:2015-11-06
* Author: andrey
* Description: Module name "known" to synthesis, but missing in unisims
*
* Copyright (c) 2015 Elphel, Inc .
* IBUFG.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* IBUFG.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module IBUFG #(
parameter CAPACITANCE = "DONT_CARE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I
);
ibuf_ibufg #(
.CAPACITANCE (CAPACITANCE),
// .IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUF_i (
.O (O), // output
.I (I) // input
);
endmodule
unisims_extra/IBUFGDS.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: IBUFGDS
* Date:2015-11-06
* Author: andrey
* Description: Module name "known" to synthesis, but missing in unisims
*
* Copyright (c) 2015 Elphel, Inc .
* IBUFGDS.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* IBUFGDS.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module IBUFGDS # (
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
// parameter DQS_BIAS = "FALSE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
ibufds_ibufgds #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
// .DQS_BIAS (HISPI_DQS_BIAS),
// .IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) ibufds_ibufgds_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
util_modules/clocks393.v
View file @ 8dd16a59
...@@ -63,25 +63,17 @@ module clocks393#( ...@@ -63,25 +63,17 @@ module clocks393#(
parameter BUF_CLK1X_SYNC = "BUFG", parameter BUF_CLK1X_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE", parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_DELAY_VALUE = "0",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE", parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IFD_DELAY_VALUE = "AUTO",
parameter MEMCLK_IOSTANDARD = "DEFAULT", parameter MEMCLK_IOSTANDARD = "DEFAULT",
parameter FFCLK0_CAPACITANCE = "DONT_CARE", parameter FFCLK0_CAPACITANCE = "DONT_CARE",
parameter FFCLK0_DIFF_TERM = "FALSE", parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_DQS_BIAS = "FALSE",
parameter FFCLK0_IBUF_DELAY_VALUE = "0",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE", parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK0_IOSTANDARD = "DEFAULT", parameter FFCLK0_IOSTANDARD = "DEFAULT",
parameter FFCLK1_CAPACITANCE = "DONT_CARE", parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE", parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_DQS_BIAS = "FALSE",
parameter FFCLK1_IBUF_DELAY_VALUE = "0",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE", parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK1_IOSTANDARD = "DEFAULT" parameter FFCLK1_IOSTANDARD = "DEFAULT"
)( )(
...@@ -275,9 +267,7 @@ module clocks393#( ...@@ -275,9 +267,7 @@ module clocks393#(
ibuf_ibufg #( ibuf_ibufg #(
.CAPACITANCE (MEMCLK_CAPACITANCE), .CAPACITANCE (MEMCLK_CAPACITANCE),
.IBUF_DELAY_VALUE (MEMCLK_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR), .IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (MEMCLK_IFD_DELAY_VALUE),
.IOSTANDARD (MEMCLK_IOSTANDARD) .IOSTANDARD (MEMCLK_IOSTANDARD)
) ibuf_ibufg_i ( ) ibuf_ibufg_i (
.O (memclk), // output .O (memclk), // output
...@@ -287,10 +277,7 @@ module clocks393#( ...@@ -287,10 +277,7 @@ module clocks393#(
ibufds_ibufgds #( ibufds_ibufgds #(
.CAPACITANCE (FFCLK0_CAPACITANCE), .CAPACITANCE (FFCLK0_CAPACITANCE),
.DIFF_TERM (FFCLK0_DIFF_TERM), .DIFF_TERM (FFCLK0_DIFF_TERM),
.DQS_BIAS (FFCLK0_DQS_BIAS),
.IBUF_DELAY_VALUE (FFCLK0_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR), .IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (FFCLK0_IFD_DELAY_VALUE),
.IOSTANDARD (FFCLK0_IOSTANDARD) .IOSTANDARD (FFCLK0_IOSTANDARD)
) ibufds_ibufgds0_i ( ) ibufds_ibufgds0_i (
.O (ffclk0), // output .O (ffclk0), // output
...@@ -301,10 +288,7 @@ module clocks393#( ...@@ -301,10 +288,7 @@ module clocks393#(
ibufds_ibufgds #( ibufds_ibufgds #(
.CAPACITANCE (FFCLK1_CAPACITANCE), .CAPACITANCE (FFCLK1_CAPACITANCE),
.DIFF_TERM (FFCLK1_DIFF_TERM), .DIFF_TERM (FFCLK1_DIFF_TERM),
.DQS_BIAS (FFCLK1_DQS_BIAS),
.IBUF_DELAY_VALUE (FFCLK1_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR), .IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (FFCLK1_IFD_DELAY_VALUE),
.IOSTANDARD (FFCLK1_IOSTANDARD) .IOSTANDARD (FFCLK1_IOSTANDARD)
) ibufds_ibufgds10_i ( ) ibufds_ibufgds10_i (
.O (ffclk1), // output .O (ffclk1), // output
......
util_modules/clocks393m.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: clocks393m
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Generating global clocks for x393 (excluding memcntrl and SATA)
*
* Copyright (c) 2015 Elphel, Inc .
* clocks393m.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* clocks393m.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module clocks393m#(
parameter CLK_ADDR = 'h728, // ..'h729
parameter CLK_MASK = 'h7fe, //
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
parameter CLK_RESET = 'h0, // which clocks should stay reset after release of masrter reset {ff1,ff0,mem,sync,xclk,pclk,xclk}
parameter CLK_PWDWN = 'h0, // which clocks should stay powered down after release of masrter reset {sync,xclk,pclk,xclk}
// CLocks derived from external clock source (for sesnors
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter BUF_CLK1X_PCLK = "BUFG",
`ifdef USE_PCLK2X
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK2X = "BUFG",
`endif
/*
Mutltiple clocks derived from PS source (excluding memory controller) using a single PLL
Fvco = 1200Mhz - maximal for spped grade -1
*/
parameter MULTICLK_IN_PERIOD = 20, // 50MHz
parameter MULTICLK_DIVCLK = 1, //
parameter MULTICLK_MULT = 24, //1200MHz
parameter MULTICLK_DIV_DLYREF = 6, // 6 - 200MHz I/O delay reference clock (4 - 300MHz)
parameter MULTICLK_DIV_AXIHP = 8, // 150 MHz for AXI HP
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
`ifdef USE_XCLK2X
parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
`endif
parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
// Additional parameters for multi-clock PLL (phases and buffer types)
parameter MULTICLK_PHASE_FB = 0.0,
parameter MULTICLK_PHASE_DLYREF = 0.0,
parameter MULTICLK_BUF_DLYREF = "BUFG",
parameter MULTICLK_PHASE_AXIHP = 0.0,
parameter MULTICLK_BUF_AXIHP = "BUFG",
parameter MULTICLK_PHASE_XCLK = 0.0,
parameter MULTICLK_BUF_XCLK = "BUFG",
`ifdef USE_XCLK2X
parameter MULTICLK_PHASE_XCLK2X = 0.0,
parameter MULTICLK_BUF_XCLK2X = "BUFG",
`endif
parameter MULTICLK_PHASE_SYNC = 0.0,
parameter MULTICLK_BUF_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IOSTANDARD = "DEFAULT",
parameter FFCLK0_CAPACITANCE = "DONT_CARE",
parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IOSTANDARD = "DEFAULT",
parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IOSTANDARD = "DEFAULT"
)(
input async_rst, // always reset MMCM/PLL
input mclk, // global clock, comes from the memory controller (uses aclk generated here)
input mrst,
// command/status interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
input [3:0] fclk, // 4 clocks coming from the Zynq PS. Currently only [0] is used
input memclk_pad, // connected to external clock generator (VDD=1.5V)
input ffclk0p_pad, // differential clock (P) same power as sensors 0 and 1 (VCC_SENS01)
input ffclk0n_pad, // differential clock (N) same power as sensors 0 and 1 (VCC_SENS01)
input ffclk1p_pad, // differential clock (P) same power as sensors 0 and 1 (VCC_SENS01)
input ffclk1n_pad, // differential clock (N) same power as sensors 0 and 1 (VCC_SENS01)
output aclk, // global clock 50 MHz (used for maxi0)
output hclk, // global clock 150MHz (used for afi*, saxi*)
output pclk, // global clock for sensors (now 96MHz), based on external clock generator
`ifdef USE_PCLK2X
output pclk2x, // global clock for sensors, 2x frequency (now 192MHz)
`endif
output xclk, // global clock for compressor (now 100MHz)
`ifdef USE_XCLK2X
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
`endif
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
output dly_ref_clk, // global clock for I/O delays calibration
input [1:0] extra_status, // just extra two status bits from the top module
output locked_sync_clk,
output locked_xclk,
output locked_pclk,
output locked_hclk
);
wire memclk;
wire ffclk0;
wire ffclk1;
wire [8:0] status_data;
wire [10:0] cmd_data;
wire cmd_we;
wire [0:0] cmd_a;
wire set_ctrl_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_CNTRL);
wire set_status_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_STATUS);
wire [3:0] locked;
reg [6:0] reset_clk = CLK_RESET;
reg [3:0] pwrdwn_clk = CLK_PWDWN;
reg [2:0] test_clk; // FF to test input clocks are running
wire memclk_rst = reset_clk[4];
wire ffclk0_rst = reset_clk[5];
wire ffclk1_rst = reset_clk[6];
assign locked[3:2] = 3; // for compatibility with previous clocks393.v module
assign locked_sync_clk = locked[3];
assign locked_xclk = locked[2];
assign locked_pclk = locked[1];
assign locked_hclk = locked[0];
always @ (posedge mclk) begin
if (mrst) reset_clk <= CLK_RESET;
else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};
if (mrst) pwrdwn_clk <= CLK_PWDWN;
else if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4];
end
assign status_data = {test_clk, locked, extra_status};
always @ (posedge memclk or posedge memclk_rst) if (async_rst || memclk_rst) test_clk[0] <= 0; else test_clk[0] <= ~test_clk[0];
always @ (posedge ffclk0 or posedge ffclk0_rst) if (async_rst || ffclk0_rst) test_clk[1] <= 0; else test_clk[1] <= ~test_clk[1];
always @ (posedge ffclk1 or posedge ffclk1_rst) if (async_rst || ffclk1_rst) test_clk[2] <= 0; else test_clk[2] <= ~test_clk[2];
cmd_deser #(
.ADDR (CLK_ADDR),
.ADDR_MASK (CLK_MASK),
.NUM_CYCLES (4),
.ADDR_WIDTH (1),
.DATA_WIDTH (11)
) cmd_deser_32bit_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (CLK_STATUS_REG_ADDR),
.PAYLOAD_BITS (9),
.REGISTER_STATUS (0)
) status_generate_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[14:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
BUFG bufg_axi_aclk_i (.O(aclk), .I(fclk[0])); // PS clock, 50MHz
// from external clock sourec
dual_clock_source #(
.CLKIN_PERIOD (CLKIN_PERIOD_PCLK),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_PCLK),
.BUF_CLK1X (BUF_CLK1X_PCLK)
`ifdef USE_PCLK2X
,.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_PCLK),
.BUF_CLK2X (BUF_CLK1X_PCLK2X)
`else
,.BUF_CLK2X ("NONE")
`endif
) dual_clock_pclk_i (
.rst (async_rst || reset_clk[1]), // input
.clk_in (ffclk0), // input
.pwrdwn (pwrdwn_clk[1]), // input
.clk1x (pclk), // output
`ifdef USE_PCLK2X
.clk2x (pclk2x), // output
`else
.clk2x (), // output not connected
`endif
.locked (locked[1]) // output
);
wire multi_clkfb;
wire hclk_pre;
wire dly_ref_clk_pre;
wire xclk_pre;
wire sync_clk_pre;
`ifdef USE_PCLK2X
wire xclk2x_pre;
`endif
pll_base #(
.CLKIN_PERIOD (MULTICLK_IN_PERIOD), // 20
.BANDWIDTH ("OPTIMIZED"),
.DIVCLK_DIVIDE (MULTICLK_DIVCLK),
.CLKFBOUT_MULT (MULTICLK_MULT), // 2..64, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKFBOUT_PHASE (MULTICLK_PHASE_FB),
.CLKOUT0_DIVIDE (MULTICLK_DIV_AXIHP),
.CLKOUT0_PHASE (MULTICLK_PHASE_AXIHP),
.CLKOUT1_DIVIDE (MULTICLK_DIV_XCLK),
.CLKOUT1_PHASE (MULTICLK_PHASE_XCLK),
`ifdef USE_XCLK2X
.CLKOUT2_DIVIDE (MULTICLK_DIV_XCLK2X),
.CLKOUT2_PHASE (MULTICLK_PHASE_XCLK2X),
`endif
.CLKOUT3_DIVIDE (MULTICLK_DIV_SYNC),
.CLKOUT3_PHASE (MULTICLK_PHASE_SYNC),
.CLKOUT5_DIVIDE (MULTICLK_DIV_DLYREF),
.CLKOUT5_PHASE (MULTICLK_PHASE_DLYREF),
.REF_JITTER1 (0.010),
.STARTUP_WAIT ("FALSE")
) pll_base_i (
.clkin(aclk), // input
.clkfbin (multi_clkfb), // input
.rst (async_rst || reset_clk[0]), // input TODO: check resets/
.pwrdwn (pwrdwn_clk[0]), // input
.clkout0 (hclk_pre), // output
.clkout1 (xclk_pre), // output
`ifdef USE_PCLK2X
.clkout2 (xclk2x_pre), // output
`else
.clkout2 (), // output
`endif
.clkout3 (sync_clk_pre), // output
.clkout4 (), // output
.clkout5 (dly_ref_clk_pre), // output
.clkfbout (multi_clkfb), // output
.locked (locked[0]) // output
);
// Buffering clocks outputs
select_clk_buf #(.BUFFER_TYPE(MULTICLK_BUF_DLYREF)) dly_ref_clk_i (.o(dly_ref_clk), .i(dly_ref_clk_pre), .clr(async_rst));
select_clk_buf #(.BUFFER_TYPE(MULTICLK_BUF_AXIHP)) hclk_i (.o(hclk), .i(hclk_pre), .clr(async_rst));
select_clk_buf #(.BUFFER_TYPE(MULTICLK_BUF_XCLK)) xclk_i (.o(xclk), .i(xclk_pre), .clr(async_rst)); // locked[2],pwrdwn_clk[2],reset_clk[2]
`ifdef USE_XCLK2X
select_clk_buf #(.BUFFER_TYPE(MULTICLK_BUF_XCLK2X)) xclk2x_i (.o(xclk2x), .i(xclk2x_pre), .clr(async_rst));
`endif
select_clk_buf #(.BUFFER_TYPE(MULTICLK_BUF_SYNC)) sync_clk_i (.o(sync_clk), .i(sync_clk_pre), .clr(async_rst)); // locked[3],pwrdwn_clk[3],reset_clk[3]
ibuf_ibufg #(
.CAPACITANCE (MEMCLK_CAPACITANCE),
.IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR),
.IOSTANDARD (MEMCLK_IOSTANDARD)
) ibuf_ibufg_i (
.O (memclk), // output
.I (memclk_pad) // input
);
ibufds_ibufgds #(
.CAPACITANCE (FFCLK0_CAPACITANCE),
.DIFF_TERM (FFCLK0_DIFF_TERM),
.IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR),
.IOSTANDARD (FFCLK0_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (ffclk0), // output
.I (ffclk0p_pad), // input
.IB (ffclk0n_pad) // input
);
ibufds_ibufgds #(
.CAPACITANCE (FFCLK1_CAPACITANCE),
.DIFF_TERM (FFCLK1_DIFF_TERM),
.IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR),
.IOSTANDARD (FFCLK1_IOSTANDARD)
) ibufds_ibufgds10_i (
.O (ffclk1), // output
.I (ffclk1p_pad), // input
.IB (ffclk1n_pad) // input
);
// RTC reference: integer number of microseconds, less than mclk/2. Not a global clock
// temporary:
reg [2:0] time_ref_r;
always @ (posedge mclk) if (mrst) time_ref_r <= 0; else time_ref_r <= time_ref_r + 1;
assign time_ref = time_ref_r[2];
endmodule
wrap/ibuf_ibufg.v
View file @ 8dd16a59
...@@ -23,6 +23,12 @@ ...@@ -23,6 +23,12 @@
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites. clock input sites.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibuf_ibufg_i/memclk_0 is directly
driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibuf_ibufg_i/IBUF_i/O[VivadoPlace:0000]
*/ */
module ibuf_ibufg #( module ibuf_ibufg #(
parameter CAPACITANCE = "DONT_CARE", parameter CAPACITANCE = "DONT_CARE",
......
wrap/ibufds_ibufgds.v
View file @ 8dd16a59
...@@ -23,6 +23,10 @@ ...@@ -23,6 +23,10 @@
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives": /*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential
input buffer is used as a clock input. input buffer is used as a clock input.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibuf_ibufg_i/memclk_0 is directly driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibuf_ibufg_i/IBUF_i/O[VivadoPlace:0000]
*/ */
module ibufds_ibufgds #( module ibufds_ibufgds #(
parameter CAPACITANCE = "DONT_CARE", parameter CAPACITANCE = "DONT_CARE",
......
wrap/ibufg.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: ibufg
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Wrapper for IBUFG primitive
*
* Copyright (c) 2015 Elphel, Inc .
* ibufg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ibufg.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibufg_i/memclk_0 is directly
driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibufg_i/IBUF_i/O[VivadoPlace:0000]
*/
module ibufg #(
parameter CAPACITANCE = "DONT_CARE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I
);
IBUFG #(
.CAPACITANCE (CAPACITANCE),
// .IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFG_i (
.O (O), // output
.I (I) // input
);
endmodule
wrap/ibufgds.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: ibufgds
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Wrapper for IBUFDS primitive
*
* Copyright (c) 2015 Elphel, Inc .
* ibufgds.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ibufgds.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential
input buffer is used as a clock input.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibufds_ibufgds0_i/ffclk0 is directly driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O[VivadoPlace:0000]
*/
module ibufgds #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
// parameter DQS_BIAS = "FALSE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
IBUFGDS #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
// .DQS_BIAS (DQS_BIAS),
// .IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFGDS_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
wrap/select_clk_buf.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: select_clk_buf
* Date:2015-11-07
* Author: andrey
* Description: Select one of the clock buffers primitives by parameter
*
* Copyright (c) 2015 Elphel, Inc .
* select_clk_buf.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* select_clk_buf.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module select_clk_buf #(
parameter BUFFER_TYPE = "BUFR" // to use clr
)(
output o,
input i,
input clr // for BUFR_only
);
generate
if (BUFFER_TYPE == "BUFG") BUFG clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFH") BUFH clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFR") BUFR clk1x_i (.O(o), .I(i), .CE(1'b1), .CLR(clr));
else if (BUFFER_TYPE == "BUFMR") BUFMR clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFIO") BUFIO clk1x_i (.O(o), .I(i));
else assign o = i;
endgenerate
endmodule
x393.v
View file @ 8dd16a59
...@@ -26,6 +26,51 @@ module x393 #( ...@@ -26,6 +26,51 @@ module x393 #(
`include "includes/x393_parameters.vh" `include "includes/x393_parameters.vh"
)( )(
// Sensors interface: I/O pads, pin names match circuit diagram (each sensor) // Sensors interface: I/O pads, pin names match circuit diagram (each sensor)
`ifdef HISPI
input [3:0] sns1_dp,
input [3:0] sns1_dn,
inout [7:4] sns1_dp74, // other non-diff signals
inout [7:4] sns1_dn74, // other non-diff signals
input sns1_clkp,
input sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
inout sns1_pg,
input [3:0] sns2_dp,
input [3:0] sns2_dn,
inout [7:4] sns2_dp74, // other non-diff signals
inout [7:4] sns2_dn74, // other non-diff signals
input sns2_clkp,
input sns2_clkn,
inout sns2_scl,
inout sns2_sda,
inout sns2_ctl,
inout sns2_pg,
input [3:0] sns3_dp,
input [3:0] sns3_dn,
inout [7:4] sns3_dp74, // other non-diff signals
inout [7:4] sns3_dn74, // other non-diff signals
input sns3_clkp,
input sns3_clkn,
inout sns3_scl,
inout sns3_sda,
inout sns3_ctl,
inout sns3_pg,
input [3:0] sns4_dp,
input [3:0] sns4_dn,
inout [7:4] sns4_dp74, // other non-diff signals
inout [7:4] sns4_dn74, // other non-diff signals
input sns4_clkp,
input sns4_clkn,
inout sns4_scl,
inout sns4_sda,
inout sns4_ctl,
inout sns4_pg,
`else
inout [7:0] sns1_dp, inout [7:0] sns1_dp,
inout [7:0] sns1_dn, inout [7:0] sns1_dn,
inout sns1_clkp, inout sns1_clkp,
...@@ -61,6 +106,7 @@ module x393 #( ...@@ -61,6 +106,7 @@ module x393 #(
inout sns4_sda, inout sns4_sda,
inout sns4_ctl, inout sns4_ctl,
inout sns4_pg, inout sns4_pg,
`endif
// GPIO pins (1.5V): assigned in 10389: [1:0] - i2c, [5:2] - gpio, [GPIO_N-1:6] - sync i/o // GPIO pins (1.5V): assigned in 10389: [1:0] - i2c, [5:2] - gpio, [GPIO_N-1:6] - sync i/o
inout [GPIO_N-1:0] gpio_pins, inout [GPIO_N-1:0] gpio_pins,
// DDR3 interface // DDR3 interface
...@@ -88,14 +134,9 @@ module x393 #( ...@@ -88,14 +134,9 @@ module x393 #(
input ffclk0n, // Y11 input ffclk0n, // Y11
input ffclk1p, // W14 input ffclk1p, // W14
input ffclk1n // W13 input ffclk1n // W13
,output DUMMY_TO_KEEP
); );
`include "fpga_version.vh" `include "fpga_version.vh"
assign DUMMY_TO_KEEP = frst[2] && fclk[1];
// localparam ADDRESS_NUMBER=15;
// localparam COLADDR_NUMBER=10;
// Source for reset and clock // Source for reset and clock
`ifndef IGNORE_ATTR `ifndef IGNORE_ATTR
(* KEEP = "TRUE" *) (* KEEP = "TRUE" *)
...@@ -1023,8 +1064,6 @@ assign axi_grst = axi_rst_pre; ...@@ -1023,8 +1064,6 @@ assign axi_grst = axi_rst_pre;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -1105,7 +1144,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1105,7 +1144,7 @@ assign axi_grst = axi_rst_pre;
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), .mrst (mrst),
.locked (mcntrl_locked), // to generate sync reset .locked (mcntrl_locked), // to generate sync reset
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0] .cmd_ad (cmd_mcontr_ad), // input[7:0]
...@@ -1553,7 +1592,6 @@ assign axi_grst = axi_rst_pre; ...@@ -1553,7 +1592,6 @@ assign axi_grst = axi_rst_pre;
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR), .PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE), .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
...@@ -1570,6 +1608,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1570,6 +1608,7 @@ assign axi_grst = axi_rst_pre;
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE), .IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE), .IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.BUF_IPCLK_SENS0 (BUF_IPCLK_SENS0), .BUF_IPCLK_SENS0 (BUF_IPCLK_SENS0),
.BUF_IPCLK2X_SENS0 (BUF_IPCLK2X_SENS0), .BUF_IPCLK2X_SENS0 (BUF_IPCLK2X_SENS0),
.BUF_IPCLK_SENS1 (BUF_IPCLK_SENS1), .BUF_IPCLK_SENS1 (BUF_IPCLK_SENS1),
...@@ -1587,6 +1626,15 @@ assign axi_grst = axi_rst_pre; ...@@ -1587,6 +1626,15 @@ assign axi_grst = axi_rst_pre;
`ifdef HISPI `ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST), ,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK0 (HISPI_DELAY_CLK0),
.HISPI_DELAY_CLK1 (HISPI_DELAY_CLK1),
.HISPI_DELAY_CLK2 (HISPI_DELAY_CLK2),
.HISPI_DELAY_CLK3 (HISPI_DELAY_CLK3),
.HISPI_MMCM0 (HISPI_MMCM0),
.HISPI_MMCM1 (HISPI_MMCM1),
.HISPI_MMCM2 (HISPI_MMCM2),
.HISPI_MMCM3 (HISPI_MMCM3),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -1616,7 +1664,18 @@ assign axi_grst = axi_rst_pre; ...@@ -1616,7 +1664,18 @@ assign axi_grst = axi_rst_pre;
.status_ad (status_sensor_ad), // output[7:0] .status_ad (status_sensor_ad), // output[7:0]
.status_rq (status_sensor_rq), // output .status_rq (status_sensor_rq), // output
.status_start (status_sensor_start), // input .status_start (status_sensor_start), // input
`ifdef HISPI
.sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // input[3:0]
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0]
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] SuppressThisWarning VEditor vdt-bug
.sns_clkp ({sns4_clkp, sns3_clkp, sns2_clkp, sns1_clkp}), // input
.sns_clkn ({sns4_clkn, sns3_clkn, sns2_clkn, sns1_clkn}), // input
.sns_scl ({sns4_scl, sns3_scl, sns2_scl, sns1_scl}), // inout
.sns_sda ({sns4_sda, sns3_sda, sns2_sda, sns1_sda}), // inout
.sns_ctl ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}), // inout
.sns_pg ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}), // inout
`else
.sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // inout[7:0] .sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // inout[7:0]
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // inout[7:0] .sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // inout[7:0]
.sns_clkp ({sns4_clkp, sns3_clkp, sns2_clkp, sns1_clkp}), // inout .sns_clkp ({sns4_clkp, sns3_clkp, sns2_clkp, sns1_clkp}), // inout
...@@ -1625,7 +1684,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1625,7 +1684,7 @@ assign axi_grst = axi_rst_pre;
.sns_sda ({sns4_sda, sns3_sda, sns2_sda, sns1_sda}), // inout .sns_sda ({sns4_sda, sns3_sda, sns2_sda, sns1_sda}), // inout
.sns_ctl ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}), // inout .sns_ctl ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}), // inout
.sns_pg ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}), // inout .sns_pg ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}), // inout
`endif
.rpage_set (sens_rpage_set), // input .rpage_set (sens_rpage_set), // input
.rpage_next (sens_rpage_next), // input .rpage_next (sens_rpage_next), // input
.buf_rd (sens_buf_rd), // input .buf_rd (sens_buf_rd), // input
...@@ -2156,17 +2215,12 @@ assign axi_grst = axi_rst_pre; ...@@ -2156,17 +2215,12 @@ assign axi_grst = axi_rst_pre;
.saxi_bresp (saxi1_bresp) // input[1:0] .saxi_bresp (saxi1_bresp) // input[1:0]
); );
clocks393 #( clocks393m #(
.CLK_ADDR (CLK_ADDR), .CLK_ADDR (CLK_ADDR),
.CLK_MASK (CLK_MASK), .CLK_MASK (CLK_MASK),
.CLK_STATUS_REG_ADDR (CLK_STATUS_REG_ADDR), .CLK_STATUS_REG_ADDR (CLK_STATUS_REG_ADDR),
.CLK_CNTRL (CLK_CNTRL), .CLK_CNTRL (CLK_CNTRL),
.CLK_STATUS (CLK_STATUS), .CLK_STATUS (CLK_STATUS),
.CLKIN_PERIOD_AXIHP (CLKIN_PERIOD_AXIHP),
.DIVCLK_DIVIDE_AXIHP (DIVCLK_DIVIDE_AXIHP),
.CLKFBOUT_MULT_AXIHP (CLKFBOUT_MULT_AXIHP),
.CLKOUT_DIV_AXIHP (CLKOUT_DIV_AXIHP),
.BUF_CLK1X_AXIHP (BUF_CLK1X_AXIHP),
.CLKIN_PERIOD_PCLK (CLKIN_PERIOD_PCLK), .CLKIN_PERIOD_PCLK (CLKIN_PERIOD_PCLK),
.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK), .DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK), .CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
...@@ -2176,40 +2230,41 @@ assign axi_grst = axi_rst_pre; ...@@ -2176,40 +2230,41 @@ assign axi_grst = axi_rst_pre;
.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X), .CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK), .PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
.BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X), .BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X),
`endif
.MULTICLK_IN_PERIOD (MULTICLK_IN_PERIOD),
.MULTICLK_DIVCLK (MULTICLK_DIVCLK),
.MULTICLK_MULT (MULTICLK_MULT),
.MULTICLK_DIV_DLYREF (MULTICLK_DIV_DLYREF),
.MULTICLK_DIV_AXIHP (MULTICLK_DIV_AXIHP),
.MULTICLK_DIV_XCLK (MULTICLK_DIV_XCLK),
`ifdef USE_XCLK2X
.MULTICLK_DIV_XCLK2X (MULTICLK_DIV_XCLK2X),
`endif `endif
.CLKIN_PERIOD_XCLK (CLKIN_PERIOD_XCLK), .MULTICLK_DIV_SYNC (MULTICLK_DIV_SYNC),
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK), .MULTICLK_PHASE_FB (MULTICLK_PHASE_FB),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK), .MULTICLK_PHASE_DLYREF (MULTICLK_PHASE_DLYREF),
.CLKOUT_DIV_XCLK (CLKOUT_DIV_XCLK), .MULTICLK_BUF_DLYREF (MULTICLK_BUF_DLYREF),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK), .MULTICLK_PHASE_AXIHP (MULTICLK_PHASE_AXIHP),
`ifdef USE_XCLK2X .MULTICLK_BUF_AXIHP (MULTICLK_BUF_AXIHP),
.CLKOUT_DIV_XCLK2X (CLKOUT_DIV_XCLK2X), .MULTICLK_PHASE_XCLK (MULTICLK_PHASE_XCLK),
.PHASE_CLK2X_XCLK (PHASE_CLK2X_XCLK), .MULTICLK_BUF_XCLK (MULTICLK_BUF_XCLK),
.BUF_CLK1X_XCLK2X (BUF_CLK1X_XCLK2X), `ifdef USE_XCLK2X
.MULTICLK_PHASE_XCLK2X (MULTICLK_PHASE_XCLK2X),
.MULTICLK_BUF_XCLK2X (MULTICLK_BUF_XCLK2X),
`endif `endif
.CLKIN_PERIOD_SYNC (CLKIN_PERIOD_SYNC), .MULTICLK_PHASE_SYNC (MULTICLK_PHASE_SYNC),
.DIVCLK_DIVIDE_SYNC (DIVCLK_DIVIDE_SYNC), .MULTICLK_BUF_SYNC (MULTICLK_BUF_SYNC),
.CLKFBOUT_MULT_SYNC (CLKFBOUT_MULT_SYNC),
.CLKOUT_DIV_SYNC (CLKOUT_DIV_SYNC),
.BUF_CLK1X_SYNC (BUF_CLK1X_SYNC),
.MEMCLK_CAPACITANCE (MEMCLK_CAPACITANCE), .MEMCLK_CAPACITANCE (MEMCLK_CAPACITANCE),
.MEMCLK_IBUF_DELAY_VALUE (MEMCLK_IBUF_DELAY_VALUE),
.MEMCLK_IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR), .MEMCLK_IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR),
.MEMCLK_IFD_DELAY_VALUE (MEMCLK_IFD_DELAY_VALUE),
.MEMCLK_IOSTANDARD (MEMCLK_IOSTANDARD), .MEMCLK_IOSTANDARD (MEMCLK_IOSTANDARD),
.FFCLK0_CAPACITANCE (FFCLK0_CAPACITANCE), .FFCLK0_CAPACITANCE (FFCLK0_CAPACITANCE),
.FFCLK0_DIFF_TERM (FFCLK0_DIFF_TERM), .FFCLK0_DIFF_TERM (FFCLK0_DIFF_TERM),
.FFCLK0_DQS_BIAS (FFCLK0_DQS_BIAS),
.FFCLK0_IBUF_DELAY_VALUE (FFCLK0_IBUF_DELAY_VALUE),
.FFCLK0_IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR), .FFCLK0_IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR),
.FFCLK0_IFD_DELAY_VALUE (FFCLK0_IFD_DELAY_VALUE),
.FFCLK0_IOSTANDARD (FFCLK0_IOSTANDARD), .FFCLK0_IOSTANDARD (FFCLK0_IOSTANDARD),
.FFCLK1_CAPACITANCE (FFCLK1_CAPACITANCE), .FFCLK1_CAPACITANCE (FFCLK1_CAPACITANCE),
.FFCLK1_DIFF_TERM (FFCLK1_DIFF_TERM), .FFCLK1_DIFF_TERM (FFCLK1_DIFF_TERM),
.FFCLK1_DQS_BIAS (FFCLK1_DQS_BIAS),
.FFCLK1_IBUF_DELAY_VALUE (FFCLK1_IBUF_DELAY_VALUE),
.FFCLK1_IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR), .FFCLK1_IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR),
.FFCLK1_IFD_DELAY_VALUE (FFCLK1_IFD_DELAY_VALUE),
.FFCLK1_IOSTANDARD (FFCLK1_IOSTANDARD) .FFCLK1_IOSTANDARD (FFCLK1_IOSTANDARD)
) clocks393_i ( ) clocks393_i (
.async_rst (axi_rst_pre), .async_rst (axi_rst_pre),
...@@ -2238,12 +2293,12 @@ assign axi_grst = axi_rst_pre; ...@@ -2238,12 +2293,12 @@ assign axi_grst = axi_rst_pre;
`endif `endif
.sync_clk (camsync_clk), // output .sync_clk (camsync_clk), // output
.time_ref (time_ref), // output .time_ref (time_ref), // output
.dly_ref_clk (ref_clk), // output
.extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0] .extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0]
.locked_sync_clk (locked_sync_clk), // output .locked_sync_clk (locked_sync_clk), // output // always 1
.locked_xclk (locked_xclk), // output .locked_xclk (locked_xclk), // output // always 1
.locked_pclk (locked_pclk), // output .locked_pclk (locked_pclk), // output
.locked_hclk (locked_hclk) // output .locked_hclk (locked_hclk) // output
); );
sync_resets #( sync_resets #(
......
x393.xdc
View file @ 8dd16a59
...@@ -19,6 +19,15 @@ ...@@ -19,6 +19,15 @@
# along with this program. If not, see <http://www.gnu.org/licenses/> . # along with this program. If not, see <http://www.gnu.org/licenses/> .
################################################################################# #################################################################################
# Global constraints
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property DCI_CASCADE 34 [get_iobanks 35]
set_property INTERNAL_VREF 0.750 [get_iobanks 35]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Disabling some of the DRC checks:
#http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622 #http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622
set_property is_enabled false [get_drc_checks REQP-119] set_property is_enabled false [get_drc_checks REQP-119]
#Input Buffer Connections .. has no loads. An input buffer must drive an internal load. #Input Buffer Connections .. has no loads. An input buffer must drive an internal load.
...@@ -30,202 +39,60 @@ set_property is_enabled false [get_drc_checks DPOP-1] ...@@ -30,202 +39,60 @@ set_property is_enabled false [get_drc_checks DPOP-1]
set_property is_enabled false [get_drc_checks REQP-1577] set_property is_enabled false [get_drc_checks REQP-1577]
#Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ... #Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ...
set_property is_enabled false [get_drc_checks REQP-165] set_property is_enabled false [get_drc_checks REQP-165]
#Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS. #Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS.
set_property is_enabled false [get_drc_checks REQP-14] set_property is_enabled false [get_drc_checks REQP-14]
# output SDRST, // output SDRST, active low
set_property IOSTANDARD SSTL15 [get_ports {SDRST}]
set_property PACKAGE_PIN J4 [get_ports {SDRST}] set_property PACKAGE_PIN J4 [get_ports {SDRST}]
# output SDCLK, // DDR3 clock differential output, positive
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
set_property PACKAGE_PIN K3 [get_ports {SDCLK}] set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
# output SDNCLK,// DDR3 clock differential output, negative
set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDNCLK}]
set_property PACKAGE_PIN K2 [get_ports {SDNCLK}] set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
# output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
set_property IOSTANDARD SSTL15 [get_ports {SDA[0]}]
set_property PACKAGE_PIN N3 [get_ports {SDA[0]}] set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[1]}]
set_property PACKAGE_PIN H2 [get_ports {SDA[1]}] set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[2]}]
set_property PACKAGE_PIN M2 [get_ports {SDA[2]}] set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[3]}]
set_property PACKAGE_PIN P5 [get_ports {SDA[3]}] set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[4]}]
set_property PACKAGE_PIN H1 [get_ports {SDA[4]}] set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[5]}]
set_property PACKAGE_PIN M3 [get_ports {SDA[5]}] set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[6]}]
set_property PACKAGE_PIN J1 [get_ports {SDA[6]}] set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[7]}]
set_property PACKAGE_PIN P4 [get_ports {SDA[7]}] set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[8]}]
set_property PACKAGE_PIN K1 [get_ports {SDA[8]}] set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[9]}]
set_property PACKAGE_PIN P3 [get_ports {SDA[9]}] set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[10]}]
set_property PACKAGE_PIN F2 [get_ports {SDA[10]}] set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[11]}]
set_property PACKAGE_PIN H3 [get_ports {SDA[11]}] set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[12]}]
set_property PACKAGE_PIN G3 [get_ports {SDA[12]}] set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[13]}]
set_property PACKAGE_PIN N2 [get_ports {SDA[13]}] set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
set_property IOSTANDARD SSTL15 [get_ports {SDA[14]}]
set_property PACKAGE_PIN J3 [get_ports {SDA[14]}] set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
# output [2:0] SDBA, // output bank address ports
set_property IOSTANDARD SSTL15 [get_ports {SDBA[0]}]
set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}] set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
set_property IOSTANDARD SSTL15 [get_ports {SDBA[1]}]
set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}] set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
set_property IOSTANDARD SSTL15 [get_ports {SDBA[2]}]
set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}] set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
# output SDWE, // output WE port
set_property IOSTANDARD SSTL15 [get_ports {SDWE}]
set_property PACKAGE_PIN G4 [get_ports {SDWE}] set_property PACKAGE_PIN G4 [get_ports {SDWE}]
# output SDRAS, // output RAS port
set_property IOSTANDARD SSTL15 [get_ports {SDRAS}]
set_property PACKAGE_PIN L2 [get_ports {SDRAS}] set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
# output SDCAS, // output CAS port
set_property IOSTANDARD SSTL15 [get_ports {SDCAS}]
set_property PACKAGE_PIN L1 [get_ports {SDCAS}] set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
# output SDCKE, // output Clock Enable port
set_property IOSTANDARD SSTL15 [get_ports {SDCKE}]
set_property PACKAGE_PIN E1 [get_ports {SDCKE}] set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
# output SDODT, // output ODT port
set_property IOSTANDARD SSTL15 [get_ports {SDODT}]
set_property PACKAGE_PIN M7 [get_ports {SDODT}] set_property PACKAGE_PIN M7 [get_ports {SDODT}]
#
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[0]}]
set_property PACKAGE_PIN K6 [get_ports {SDD[0]}] set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[1]}]
set_property PACKAGE_PIN L4 [get_ports {SDD[1]}] set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[2]}]
set_property PACKAGE_PIN K7 [get_ports {SDD[2]}] set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[3]}]
set_property PACKAGE_PIN K4 [get_ports {SDD[3]}] set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[4]}]
set_property PACKAGE_PIN L6 [get_ports {SDD[4]}] set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[5]}]
set_property PACKAGE_PIN M4 [get_ports {SDD[5]}] set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[6]}]
set_property PACKAGE_PIN L7 [get_ports {SDD[6]}] set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[7]}]
set_property PACKAGE_PIN N5 [get_ports {SDD[7]}] set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[8]}]
set_property PACKAGE_PIN H5 [get_ports {SDD[8]}] set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[9]}]
set_property PACKAGE_PIN J6 [get_ports {SDD[9]}] set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[10]}]
set_property PACKAGE_PIN G5 [get_ports {SDD[10]}] set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[11]}]
set_property PACKAGE_PIN H6 [get_ports {SDD[11]}] set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[12]}]
set_property PACKAGE_PIN F5 [get_ports {SDD[12]}] set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[13]}]
set_property PACKAGE_PIN F7 [get_ports {SDD[13]}] set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[14]}]
set_property PACKAGE_PIN F4 [get_ports {SDD[14]}] set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
# inout [15:0] SDD, // DQ I/O pads
set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[15]}]
set_property PACKAGE_PIN F6 [get_ports {SDD[15]}] set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
# inout DQSL, // LDQS I/O pad
set_property PACKAGE_PIN N7 [get_ports {DQSL}] set_property PACKAGE_PIN N7 [get_ports {DQSL}]
#set_property SLEW FAST [get_ports {DQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSL}]
# inout NDQSL, // ~LDQS I/O pad
set_property PACKAGE_PIN N6 [get_ports {NDQSL}] set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
#set_property SLEW FAST [get_ports {NDQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSL}]
# inout DQSU, // UDQS I/O pad
set_property PACKAGE_PIN H7 [get_ports {DQSU}] set_property PACKAGE_PIN H7 [get_ports {DQSU}]
#set_property SLEW FAST [get_ports {DQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSU}]
# inout NDQSU, // ~UDQS I/O pad
set_property PACKAGE_PIN G7 [get_ports {NDQSU}] set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
#set_property SLEW FAST [get_ports {NDQSU}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]
# inout SDDML, // LDM I/O pad (actually only output)
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDML}]
set_property PACKAGE_PIN L5 [get_ports {SDDML}] set_property PACKAGE_PIN L5 [get_ports {SDDML}]
# inout SDDMU, // UDM I/O pad (actually only output)
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
set_property IOSTANDARD LVCMOS25 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN T11 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging #not yet used, just for debugging
# input memclk,
#set_property IOSTANDARD SSTL15 [get_ports {memclk}]
set_property PACKAGE_PIN M5 [get_ports {memclk}] set_property PACKAGE_PIN M5 [get_ports {memclk}]
...@@ -253,182 +120,100 @@ set_property PACKAGE_PIN W14 [get_ports {ffclk1p}] ...@@ -253,182 +120,100 @@ set_property PACKAGE_PIN W14 [get_ports {ffclk1p}]
set_property PACKAGE_PIN W13 [get_ports {ffclk1n}] set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
# Global constraints
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property DCI_CASCADE 34 [get_iobanks 35]
set_property INTERNAL_VREF 0.750 [get_iobanks 35]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# ================= Sensor port 0 ================= # ================= Sensor port 0 =================
# inout [7:0] sns1_dp,
# inout [7:0] sns1_dn,
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}] set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}] set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}] set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}] set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}] set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}] set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}] set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}] set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}] set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}] set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}] set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}] set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}] set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}] set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}] set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}] set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
# inout sns1_clkp,
# inout sns1_clkn,
set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}] set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}] set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
# inout sns1_scl,
# inout sns1_sda,
set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}] set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}] set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
# inout sns1_ctl,
# inout sns1_pg,
set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}] set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
set_property PACKAGE_PIN U8 [get_ports {sns1_pg}] set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 ================= # ================= Sensor port 1 =================
# inout [7:0] sns2_dp,
# inout [7:0] sns2_dn,
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}] set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}] set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}] set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}] set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}] set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}] set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}] set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}] set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}] set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}] set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}] set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}] set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}] set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}] set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}] set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}] set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}]
# inout sns2_clkp,
# inout sns2_clkn,
set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}] set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}] set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
# inout sns2_scl,
# inout sns2_sda,
set_property PACKAGE_PIN T12 [get_ports {sns2_scl}] set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
set_property PACKAGE_PIN U12 [get_ports {sns2_sda}] set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
# inout sns2_ctl,
# inout sns2_pg,
set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}] set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}] set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 ================= # ================= Sensor port 2 =================
# inout [7:0] sns3_dp,
# inout [7:0] sns3_dn,
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}] set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}] set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}] set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}] set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}] set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}] set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}] set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}] set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}] set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}] set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}] set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}] set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}] set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}] set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}] set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}] set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}]
# inout sns3_clkp,
# inout sns3_clkn,
set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}] set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}] set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
# inout sns3_scl,
# inout sns3_sda,
set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}] set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}] set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
# inout sns3_ctl,
# inout sns3_pg,
set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}] set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}] set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 ================= # ================= Sensor port 3 =================
# inout [7:0] sns4_dp,
# inout [7:0] sns4_dn,
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}] set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}] set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}] set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}] set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}] set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}] set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}] set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}] set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}] set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}] set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}] set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}] set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}] set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}] set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}] set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}] set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}]
# inout sns4_clkp,
# inout sns4_clkn,
set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}] set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}] set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
# inout sns4_scl,
# inout sns4_sda,
set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}] set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}] set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
# inout sns4_ctl,
# inout sns4_pg,
set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}] set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}] set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
#ERROR: [Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair.
# The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock
# region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable
# for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.
# However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/clkout1]
\ No newline at end of file
x393_hispi.xdc 0 → 100644
View file @ 8dd16a59
#################################################################################
# Filename: x393.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: Elphel x393 camera constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
# Global constraints
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
set_property DCI_CASCADE 34 [get_iobanks 35]
set_property INTERNAL_VREF 0.750 [get_iobanks 35]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
# Disabling some of the DRC checks:
#http://forums.xilinx.com/t5/7-Series-FPGAs/MMCM-reference-clock-muxing/td-p/550622
set_property is_enabled false [get_drc_checks REQP-119]
#Input Buffer Connections .. has no loads. An input buffer must drive an internal load.
set_property is_enabled false [get_drc_checks BUFC-1]
#DSP Buffering:
set_property is_enabled false [get_drc_checks DPIP-1]
set_property is_enabled false [get_drc_checks DPOP-1]
#MMCME2_ADV connectivity violation
set_property is_enabled false [get_drc_checks REQP-1577]
#Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ...
set_property is_enabled false [get_drc_checks REQP-165]
#Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS.
set_property is_enabled false [get_drc_checks REQP-14]
set_property PACKAGE_PIN J4 [get_ports {SDRST}]
set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
set_property PACKAGE_PIN G4 [get_ports {SDWE}]
set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
set_property PACKAGE_PIN M7 [get_ports {SDODT}]
set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
set_property PACKAGE_PIN N7 [get_ports {DQSL}]
set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
set_property PACKAGE_PIN H7 [get_ports {DQSU}]
set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
set_property PACKAGE_PIN L5 [get_ports {SDDML}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
#not yet used, just for debugging
set_property PACKAGE_PIN M5 [get_ports {memclk}]
# ======== GPIO pins ===============
# inout [GPIO_N-1:0] gpio_pins,
set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}]
set_property PACKAGE_PIN A4 [get_ports {gpio_pins[1]}]
set_property PACKAGE_PIN A2 [get_ports {gpio_pins[2]}]
set_property PACKAGE_PIN A1 [get_ports {gpio_pins[3]}]
set_property PACKAGE_PIN C3 [get_ports {gpio_pins[4]}]
set_property PACKAGE_PIN D3 [get_ports {gpio_pins[5]}]
set_property PACKAGE_PIN D1 [get_ports {gpio_pins[6]}]
set_property PACKAGE_PIN C1 [get_ports {gpio_pins[7]}]
set_property PACKAGE_PIN C2 [get_ports {gpio_pins[8]}]
set_property PACKAGE_PIN B2 [get_ports {gpio_pins[9]}]
# =========Differential clock inputs ==========
# input ffclk0p, // Y12
# input ffclk0n, // Y11
# input ffclk1p, // W14
# input ffclk1n // W13
set_property PACKAGE_PIN Y12 [get_ports {ffclk0p}]
set_property PACKAGE_PIN Y11 [get_ports {ffclk0n}]
set_property PACKAGE_PIN W14 [get_ports {ffclk1p}]
set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
# ================= Sensor port 0 =================
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}]
set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 =================
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}]
set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 =================
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}]
set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 =================
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}]
set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
x393_hispi_timing.xdc 0 → 100644
View file @ 8dd16a59
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
#create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
#create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#clock for inter - camera synchronization and event logger
#create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/mmcm_phase_cntr_i/clkout1]
#Sensor-synchronous clocks
#create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
#create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
#create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
#create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
#set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
#set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
#set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
#set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
x393_nox2_timing.xdc
View file @ 8dd16a59
...@@ -73,14 +73,19 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ] ...@@ -73,14 +73,19 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ] create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ] create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre] create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ] #create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ] create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
#create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ] #create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ] #create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/xclk2x_pre ]
#clock for inter - camera synchronization and event logger #clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ] #create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}] create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated #Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
......
x393_testbench01.tf
View file @ 8dd16a59
...@@ -159,7 +159,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -159,7 +159,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire SDDMU; // inout wire SDDMU; // inout
wire DQSU; // inout wire DQSU; // inout
wire NDQSU; // inout wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
wire memclk; wire memclk;
wire ffclk0p; // input wire ffclk0p; // input
...@@ -828,8 +827,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -828,8 +827,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE), .SDCLK_PHASE (SDCLK_PHASE),
...@@ -974,8 +971,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -974,8 +971,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n), // input .ffclk1n (ffclk1n) // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
......
x393_testbench02.tf
View file @ 8dd16a59
...@@ -317,7 +317,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -317,7 +317,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire SDDMU; // inout wire SDDMU; // inout
wire DQSU; // inout wire DQSU; // inout
wire NDQSU; // inout wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
wire memclk; wire memclk;
wire ffclk0p; // input wire ffclk0p; // input
...@@ -1292,8 +1291,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1292,8 +1291,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
...@@ -1439,8 +1436,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1439,8 +1436,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n), // input .ffclk1n (ffclk1n) // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
......
x393_testbench03.tf
View file @ 8dd16a59
...@@ -439,7 +439,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -439,7 +439,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire SDDMU; // inout wire SDDMU; // inout
wire DQSU; // inout wire DQSU; // inout
wire NDQSU; // inout wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
wire memclk; wire memclk;
wire ffclk0p; // input wire ffclk0p; // input
...@@ -1420,8 +1419,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1420,8 +1419,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -1567,8 +1564,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1567,8 +1564,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n), // input .ffclk1n (ffclk1n) // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
......
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