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Commit 82e11ec7 authored by Andrey Filippov's avatar Andrey Filippov
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multiple changes, synchronizing simulation with hardware

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.gitignore
View file @ 82e11ec7
...@@ -2,6 +2,9 @@ unisims ...@@ -2,6 +2,9 @@ unisims
vivado_* vivado_*
syntax_* syntax_*
simulation/* simulation/*
simulation_data/*
www/*
constraints/*
ise_* ise_*
attic/* attic/*
hardware_tests/* hardware_tests/*
...@@ -31,3 +34,9 @@ x393_testbench01_debug_membridge.sav ...@@ -31,3 +34,9 @@ x393_testbench01_debug_membridge.sav
x393_testbench02-0.sav x393_testbench02-0.sav
py393/generated py393/generated
*.pickle *.pickle
py393/i2c.py
py393/x393_i2c.py.test
py393/x393_init_usb_hub.py
py393/x393_mcntrl_adjust.py.dbg
x393_testbench03_01.sav
.project
View file @ 82e11ec7
...@@ -62,52 +62,52 @@ ...@@ -62,52 +62,52 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160417173535326.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160417175241357.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160417173535326.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160417173535326.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
...@@ -127,7 +127,7 @@ ...@@ -127,7 +127,7 @@
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160417173535326.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
axi/membridge.v
View file @ 82e11ec7
...@@ -291,6 +291,8 @@ module membridge#( ...@@ -291,6 +291,8 @@ module membridge#(
reg [4:0] rd_id; reg [4:0] rd_id;
reg [4:0] wr_id; reg [4:0] wr_id;
reg read_no_more; // after frame_done - no more requests for new pages to read
assign afi_arid={1'b1,rd_id}; assign afi_arid={1'b1,rd_id};
assign afi_awid={1'b1,wr_id}; assign afi_awid={1'b1,wr_id};
assign afi_wid= {1'b1,wr_id}; assign afi_wid= {1'b1,wr_id};
...@@ -324,7 +326,7 @@ module membridge#( ...@@ -324,7 +326,7 @@ module membridge#(
if (hrst) wr_start <= 0; if (hrst) wr_start <= 0;
else wr_start <= rdwr_start[2] && wr_mode; else wr_start <= rdwr_start[2] && wr_mode;
page_ready_rd <= page_ready && !wr_mode; // page_ready_rd <= page_ready && !wr_mode && !read_no_more;
if (hrst) rd_id <= 0; if (hrst) rd_id <= 0;
else if (rd_start) rd_id <= rd_id +1; else if (rd_start) rd_id <= rd_id +1;
...@@ -429,7 +431,7 @@ module membridge#( ...@@ -429,7 +431,7 @@ module membridge#(
afi_len <= (|left64[28:4])?4'hf : (left64[3:0]-1); afi_len <= (|left64[28:4])?4'hf : (left64[3:0]-1);
afi_len_plus1 <= (|left64[28:4]) ? 5'h10 : {1'b0,left64[3:0]}; afi_len_plus1 <= (|left64[28:4]) ? 5'h10 : {1'b0,left64[3:0]};
page_ready_rd <= page_ready && !wr_mode; page_ready_rd <= page_ready && !wr_mode && !read_no_more;
page_ready_wr <= page_ready && wr_mode; page_ready_wr <= page_ready && wr_mode;
if (!rw_in_progress) buf_left64 <= len64; if (!rw_in_progress) buf_left64 <= len64;
...@@ -450,12 +452,13 @@ module membridge#( ...@@ -450,12 +452,13 @@ module membridge#(
//rdwr_en //rdwr_en
reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels
reg [7:0] axi_bursts_requested; // number of bursts requested reg [7:0] axi_bursts_requested; // number of bursts requested
reg [7:0] wresp_conf; // number of 64-bit words confirmed through axi b channel reg [7:0] wresp_conf; // number of 64-bit words confirmed through axi b channel (wrong confirmed only bursts)!
wire [7:0] axi_wr_pending; // Number of words qued to AW but not yet confirmed through B-channel; wire [7:0] axi_wr_pending; // Number of bursts queued to AW but not yet confirmed through B-channel;
reg [7:0] axi_wr_left; // Number of bursts queued through AW but not sent over W;
wire [7:0] axi_rd_pending; wire [7:0] axi_rd_pending;
reg [7:0] axi_rd_received; reg [7:0] axi_rd_received;
assign axi_rd_pending= axi_arw_requested - axi_rd_received; assign axi_rd_pending= axi_arw_requested - axi_rd_received; // WRONG! - use bursts, not words!
// assign axi_wr_pending= axi_arw_requested - wresp_conf; // assign axi_wr_pending= axi_arw_requested - wresp_conf;
assign axi_wr_pending= axi_bursts_requested - wresp_conf; assign axi_wr_pending= axi_bursts_requested - wresp_conf;
...@@ -520,12 +523,12 @@ module membridge#( ...@@ -520,12 +523,12 @@ module membridge#(
if (hrst) read_page <= 0; if (hrst) read_page <= 0;
else if (reset_page_rd) read_page <= 0; else if (reset_page_rd) read_page <= 0;
else if (next_page_rd_w) read_page <= read_page + 1; else if (done_page_rd_w) read_page <= read_page + 1;
if (hrst) read_pages_ready <= 0; if (hrst) read_pages_ready <= 0;
else if (!read_busy) read_pages_ready <= 0; else if (!read_busy) read_pages_ready <= 0;
else if ( page_ready_rd && !next_page_rd_w) read_pages_ready <= read_pages_ready +1; else if ( page_ready_rd && !done_page_rd_w) read_pages_ready <= read_pages_ready +1;
else if (!page_ready_rd && next_page_rd_w) read_pages_ready <= read_pages_ready -1; else if (!page_ready_rd && done_page_rd_w) read_pages_ready <= read_pages_ready -1;
if (hrst) afi_wd_safe_not_full <= 0; if (hrst) afi_wd_safe_not_full <= 0;
else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3])); else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));
...@@ -544,6 +547,12 @@ module membridge#( ...@@ -544,6 +547,12 @@ module membridge#(
else if (pre_done) done <= 1; else if (pre_done) done <= 1;
else if (rdwr_start) done <= 0; else if (rdwr_start) done <= 0;
if (hrst ) read_no_more <= 0;
else if (!read_busy) read_no_more <= 0;
else if (frame_done) read_no_more <= 1;
end end
// handle interaction with the buffer, advance addresses, keep track of partial (last) pages in each line // handle interaction with the buffer, advance addresses, keep track of partial (last) pages in each line
...@@ -557,17 +566,29 @@ module membridge#( ...@@ -557,17 +566,29 @@ module membridge#(
wire is_last_in_page; wire is_last_in_page;
wire next_page_rd_w; wire next_page_rd_w;
wire next_page_wr_w; wire next_page_wr_w;
wire done_page_rd_w;
wire safe_some_left_rd_w;
reg left_was_1; // was <=1 (0 does not matter) valid next after buffer address
reg left_many;
// assign next_page_rd_w = read_started && !busy_next_page && is_last_in_page && bufrd_rd[0]; // assign next_page_rd_w = read_started && !busy_next_page && is_last_in_page && bufrd_rd[0];
assign next_page_rd_w = read_started && is_last_in_page && bufrd_rd[0]; assign done_page_rd_w = read_started && is_last_in_page && bufrd_rd[0];
assign next_page_rd_w = done_page_rd_w && !read_no_more;
assign is_last_in_line = buf_in_line64 == last_in_line64; assign is_last_in_line = buf_in_line64 == last_in_line64;
assign is_last_in_page = is_last_in_line || (&buf_in_line64[6:0]); assign is_last_in_page = is_last_in_line || (&buf_in_line64[6:0]);
// assign safe_some_left_rd_w = (axi_wr_left[7:1]!=0) || (axi_wr_left[0] && !bufrd_rd[0]);
assign safe_some_left_rd_w = left_many || (|buf_left64[1:0] && !(|bufrd_rd)); // Fine tune
`ifdef MEMBRIDGE_DEBUG_READ `ifdef MEMBRIDGE_DEBUG_READ
assign bufrd_rd_w = afi_wd_safe_not_full && (|read_pages_ready[2:1] || (read_pages_ready[0] && !is_last_in_page)) && debug_w_ready; assign bufrd_rd_w = safe_some_left_rd_w && !read_over && afi_wd_safe_not_full &&
(|read_pages_ready[2:1] || (read_pages_ready[0] && (!is_last_in_page || read_no_more))) && debug_w_ready;
`else `else
assign bufrd_rd_w = afi_wd_safe_not_full && (|read_pages_ready[2:1] || (read_pages_ready[0] && !is_last_in_page)); // assign bufrd_rd_w = afi_wd_safe_not_full && (|read_pages_ready[2:1] || (read_pages_ready[0] && !is_last_in_page));
assign bufrd_rd_w = safe_some_left_rd_w && !read_over && afi_wd_safe_not_full &&
(|read_pages_ready[2:1] || (read_pages_ready[0] && (!is_last_in_page || read_no_more)));
`endif `endif
//last_in_line64 - last word number in scan line //last_in_line64 - last word number in scan line
reg left_was_1; // was <=1 (0 does not matter) valid next after buffer address
reg [3:0] src_wcntr; reg [3:0] src_wcntr;
// reg [2:0] wlast_in_burst; // reg [2:0] wlast_in_burst;
reg wlast; // valid 2 after buffer address, same as wvalid reg wlast; // valid 2 after buffer address, same as wvalid
...@@ -581,6 +602,12 @@ module membridge#( ...@@ -581,6 +602,12 @@ module membridge#(
if (!rw_in_progress) left_was_1 <= 0; if (!rw_in_progress) left_was_1 <= 0;
else if (buf_rdwr) left_was_1 <= !(|buf_left64[28:1]); else if (buf_rdwr) left_was_1 <= !(|buf_left64[28:1]);
/* if (!rw_in_progress) left_many <= 0;
else if (buf_rdwr) */
left_many <= |buf_left64[28:2];
if (!read_started) src_wcntr <= 0; if (!read_started) src_wcntr <= 0;
else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1; else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1;
...@@ -643,6 +670,11 @@ module membridge#( ...@@ -643,6 +670,11 @@ module membridge#(
else if (!write_busy) axi_rd_received <= 0; else if (!write_busy) axi_rd_received <= 0;
else if (bufwr_we[0]) axi_rd_received <= axi_rd_received + 1; else if (bufwr_we[0]) axi_rd_received <= axi_rd_received + 1;
if (hrst) axi_wr_left <= 0;
else if (!read_started) axi_wr_left <= 0;
else if ( advance_rel_addr && !(wlast && afi_wvalid)) axi_wr_left <= axi_wr_left + 1;
else if (!advance_rel_addr && (wlast && afi_wvalid)) axi_wr_left <= axi_wr_left - 1;
if (hrst) afi_rd_safe_not_empty <= 0; if (hrst) afi_rd_safe_not_empty <= 0;
// allow 1 cycle latency, no continuous reads when FIFO is low (like in the very end of the transfer) // allow 1 cycle latency, no continuous reads when FIFO is low (like in the very end of the transfer)
......
compressor_jp/cmprs_frame_sync.v
View file @ 82e11ec7
...@@ -78,7 +78,8 @@ module cmprs_frame_sync#( ...@@ -78,7 +78,8 @@ module cmprs_frame_sync#(
output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk
// stuffer will re-clock and extract 0->1 transition // stuffer will re-clock and extract 0->1 transition
output stuffer_running_mclk, output stuffer_running_mclk,
output reading_frame output reading_frame,
output frame_started_mclk // use to store frame number
); );
/* /*
Abort frame (force flush) if: Abort frame (force flush) if:
...@@ -87,7 +88,7 @@ module cmprs_frame_sync#( ...@@ -87,7 +88,7 @@ module cmprs_frame_sync#(
Abort frame lasts until flush end or timeout expire Abort frame lasts until flush end or timeout expire
*/ */
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late // wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
wire frame_started_mclk; // wire frame_started_mclk;
reg bonded_mode; reg bonded_mode;
reg frame_start_dst_r; reg frame_start_dst_r;
reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_* reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_*
......
compressor_jp/cmprs_status.v
View file @ 82e11ec7
...@@ -33,15 +33,18 @@ ...@@ -33,15 +33,18 @@
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
module cmprs_status( module cmprs_status #(
parameter NUM_FRAME_BITS = 4
) (
input mrst, input mrst,
input mclk, // system clock input mclk, // system clock
input eof_written, input eof_written,
input stuffer_running, input stuffer_running,
input reading_frame, input reading_frame,
input [NUM_FRAME_BITS - 1:0] frame_num_compressed,
input set_interrupts, input set_interrupts,
input [1:0] data_in, input [1:0] data_in,
output [4:0] status, output [NUM_FRAME_BITS+7:0] status,
output irq output irq
); );
...@@ -49,9 +52,11 @@ module cmprs_status( ...@@ -49,9 +52,11 @@ module cmprs_status(
reg flushing_fifo; reg flushing_fifo;
reg is_r; // interrupt status (not masked) reg is_r; // interrupt status (not masked)
reg im_r; // interrupt mask reg im_r; // interrupt mask
reg [NUM_FRAME_BITS - 1:0] frame_irq;
assign status = {frame_irq,
assign status = {flushing_fifo, 3'b0,
flushing_fifo,
stuffer_running_r, stuffer_running_r,
reading_frame, reading_frame,
im_r, is_r}; im_r, is_r};
...@@ -65,6 +70,8 @@ module cmprs_status( ...@@ -65,6 +70,8 @@ module cmprs_status(
else if (eof_written) is_r <= 1; else if (eof_written) is_r <= 1;
else if (set_interrupts && (data_in == 1)) is_r <= 0; else if (set_interrupts && (data_in == 1)) is_r <= 0;
if (eof_written) frame_irq <= frame_num_compressed;
stuffer_running_r <= stuffer_running; stuffer_running_r <= stuffer_running;
if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1; if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1;
......
compressor_jp/compressor393.v
View file @ 82e11ec7
...@@ -127,7 +127,9 @@ module compressor393 # ( ...@@ -127,7 +127,9 @@ module compressor393 # (
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26) parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3, parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used parameter AFI_MUX_BUF_LATENCY = 4'd2, // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
`ifdef DEBUG_RING `ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 ,parameter DEBUG_CMD_LATENCY = 2
`endif `endif
...@@ -173,6 +175,7 @@ module compressor393 # ( ...@@ -173,6 +175,7 @@ module compressor393 # (
// use as 'eot_real' in 353 // use as 'eot_real' in 353
output [3:0]suspend, // suspend reading data for this channel - waiting for the source data output [3:0]suspend, // suspend reading data for this channel - waiting for the source data
output [4*LAST_FRAME_BITS-1:0] frame_number_finished, // frame numbers compressed
// statistics data was not used in late nc353 // statistics data was not used in late nc353
// input dccout, //enable output of DC and HF components for brightness/color/focus adjustments // input dccout, //enable output of DC and HF components for brightness/color/focus adjustments
...@@ -187,11 +190,12 @@ module compressor393 # ( ...@@ -187,11 +190,12 @@ module compressor393 # (
// Outputs for interrupts generation // Outputs for interrupts generation
output [3:0] eof_written_mclk, output [3:0] eof_written_mclk,
output [3:0] stuffer_done_mclk, output [3:0] stuffer_done_mclk,
// frame input synchronization // frame input synchronization
input [3:0] vsync_late, // delayed start of frame, @mclk. In 353 it was 16 lines after VACT active input [3:0] vsync_late, // delayed start of frame, @mclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands // source channel should already start, some delay give time for sequencer commands
// that should arrive before it // that should arrive before it
// Frame numbers to determine number of compressed frame (for interrupts)
input [4 * NUM_FRAME_BITS-1:0] frame_num_compressed,
// AXI_HP inteface (single/dual). afi indices - relative (0,1) may actually be connected to 1,2 (or only to 1) // AXI_HP inteface (single/dual). afi indices - relative (0,1) may actually be connected to 1,2 (or only to 1)
input hclk, input hclk,
...@@ -398,7 +402,8 @@ module compressor393 # ( ...@@ -398,7 +402,8 @@ module compressor393 # (
.CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS), .CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS),
.CMPRS_CORING_BITS (CMPRS_CORING_BITS), .CMPRS_CORING_BITS (CMPRS_CORING_BITS),
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS), .CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT) .CMPRS_TIMEOUT (CMPRS_TIMEOUT),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY) ,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif `endif
...@@ -433,7 +438,7 @@ module compressor393 # ( ...@@ -433,7 +438,7 @@ module compressor393 # (
.frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0] .frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_dst (frame_done_dst[i]), // input .frame_done_dst (frame_done_dst[i]), // input
.suspend (suspend[i]), // output .suspend (suspend[i]), // output
.frame_number_finished (frame_number_finished[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // output reg[15:0]
.dccout (1'b0), // input .dccout (1'b0), // input
.hfc_sel (3'b0), // input[2:0] .hfc_sel (3'b0), // input[2:0]
.statistics_dv (), // output .statistics_dv (), // output
...@@ -443,6 +448,7 @@ module compressor393 # ( ...@@ -443,6 +448,7 @@ module compressor393 # (
.eof_written_mclk (eof_written_mclk[i]), // output .eof_written_mclk (eof_written_mclk[i]), // output
.stuffer_done_mclk (stuffer_done_mclk[i]), // output .stuffer_done_mclk (stuffer_done_mclk[i]), // output
.vsync_late (vsync_late[i]), // input .vsync_late (vsync_late[i]), // input
.frame_num_compressed (frame_num_compressed[i * NUM_FRAME_BITS +: NUM_FRAME_BITS]), // input[3:0]
.hclk (hclk), // input .hclk (hclk), // input
.fifo_rst (fifo_rst[i]), // input .fifo_rst (fifo_rst[i]), // input
......
compressor_jp/jp_channel.v
View file @ 82e11ec7
...@@ -111,7 +111,9 @@ module jp_channel#( ...@@ -111,7 +111,9 @@ module jp_channel#(
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_TIMEOUT_BITS= 12, parameter CMPRS_TIMEOUT_BITS= 12,
parameter CMPRS_TIMEOUT= 1000 // mclk cycles parameter CMPRS_TIMEOUT= 1000, // mclk cycles
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
`ifdef DEBUG_RING `ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 //SuppressThisWarning VEditor - not used ,parameter DEBUG_CMD_LATENCY = 2 //SuppressThisWarning VEditor - not used
`endif `endif
...@@ -159,6 +161,8 @@ module jp_channel#( ...@@ -159,6 +161,8 @@ module jp_channel#(
input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353 // use as 'eot_real' in 353
output suspend, // suspend reading data for this channel - waiting for the source data output suspend, // suspend reading data for this channel - waiting for the source data
output reg [LAST_FRAME_BITS-1:0] frame_number_finished, // valid after stuffer done
// statistics data was not used in late nc353 // statistics data was not used in late nc353
input dccout, //enable output of DC and HF components for brightness/color/focus adjustments input dccout, //enable output of DC and HF components for brightness/color/focus adjustments
...@@ -177,6 +181,7 @@ module jp_channel#( ...@@ -177,6 +181,7 @@ module jp_channel#(
input vsync_late, // delayed start of frame, @mclk. In 353 it was 16 lines after VACT active input vsync_late, // delayed start of frame, @mclk. In 353 it was 16 lines after VACT active
// source channel should already start, some delay give time for sequencer commands // source channel should already start, some delay give time for sequencer commands
// that should arrive before it // that should arrive before it
input [NUM_FRAME_BITS-1:0] frame_num_compressed,
// Output interface to the AFI mux // Output interface to the AFI mux
input hclk, input hclk,
...@@ -312,6 +317,17 @@ module jp_channel#( ...@@ -312,6 +317,17 @@ module jp_channel#(
//TODO: use next signals for status //TODO: use next signals for status
wire stuffer_running_mclk; wire stuffer_running_mclk;
wire reading_frame; wire reading_frame;
wire frame_started_mclk;// store frame number ? Wrong, frame number should come from the sensor channel
reg stuffer_running_mclk_d;
reg [LAST_FRAME_BITS-1:0] frame_number_started; // valid when stuffer started
// output reg [LAST_FRAME_BITS-1:0] frame_number_finished, // valid after stuffer done
always @ (posedge mclk) begin
stuffer_running_mclk_d <=stuffer_running_mclk;
if ( stuffer_running_mclk && !stuffer_running_mclk_d) frame_number_started <= frame_number_dst;
if (!stuffer_running_mclk && stuffer_running_mclk_d) frame_number_finished <= frame_number_started;
end
`ifdef USE_XCLK2X `ifdef USE_XCLK2X
wire [15:0] huff_do; // output[15:0] reg wire [15:0] huff_do; // output[15:0] reg
...@@ -581,22 +597,25 @@ module jp_channel#( ...@@ -581,22 +597,25 @@ module jp_channel#(
.we (cmd_we) // output .we (cmd_we) // output
); );
wire [4:0] status_data; wire [11:0] status_data;
cmprs_status cmprs_status_i ( cmprs_status #(
.NUM_FRAME_BITS(4)
) cmprs_status_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
.eof_written (eof_written_mclk), // input .eof_written (eof_written_mclk), // input
.stuffer_running (stuffer_running_mclk), // input .stuffer_running (stuffer_running_mclk), // input
.reading_frame (reading_frame), // input .reading_frame (reading_frame), // input
.frame_num_compressed (frame_num_compressed), // input[3:0]
.set_interrupts (set_interrupts_w), // input .set_interrupts (set_interrupts_w), // input
.data_in (cmd_data[1:0]), // input[1:0] .data_in (cmd_data[1:0]), // input[1:0]
.status (status_data), // output[2:0] .status (status_data), // output[9:0]
.irq (irq) // output .irq (irq) // output
); );
status_generate #( status_generate #(
.STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR), .STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR),
.PAYLOAD_BITS (7), .PAYLOAD_BITS (14),
.EXTRA_WORDS (1), .EXTRA_WORDS (1),
.EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR) .EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR)
...@@ -779,8 +798,8 @@ module jp_channel#( ...@@ -779,8 +798,8 @@ module jp_channel#(
.stuffer_running (stuffer_running), // input .stuffer_running (stuffer_running), // input
.force_flush_long (force_flush_long), // output reg - @ mclk tried to start frame compression before the previous one was finished .force_flush_long (force_flush_long), // output reg - @ mclk tried to start frame compression before the previous one was finished
.stuffer_running_mclk(stuffer_running_mclk), // output .stuffer_running_mclk(stuffer_running_mclk), // output
.reading_frame (reading_frame) // output .reading_frame (reading_frame), // output
.frame_started_mclk (frame_started_mclk)
); );
cmprs_macroblock_buf_iface cmprs_macroblock_buf_iface_i ( cmprs_macroblock_buf_iface cmprs_macroblock_buf_iface_i (
...@@ -1239,6 +1258,9 @@ module jp_channel#( ...@@ -1239,6 +1258,9 @@ module jp_channel#(
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO .fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
); );
pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy()); pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
// pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
`ifdef DISPLAY_COMPRESSED_DATA `ifdef DISPLAY_COMPRESSED_DATA
integer dbg_stuffer_word_number; integer dbg_stuffer_word_number;
reg dbg_odd_stuffer_dv; reg dbg_odd_stuffer_dv;
......
fpga_version.vh
View file @ 82e11ec7
...@@ -32,7 +32,8 @@ ...@@ -32,7 +32,8 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer
// parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load
// parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched // parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched
// parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met // parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met
// parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF // parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF
......
includes/tasks_tests_memory.vh
View file @ 82e11ec7
...@@ -139,6 +139,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused ...@@ -139,6 +139,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
input continue; // 0 start from start64, 1 - continue from where it was input continue; // 0 start from start64, 1 - continue from where it was
input disable_need; input disable_need;
input [4:0] cache_mode; // 'h3 - normal, 'h13 - debug input [4:0] cache_mode; // 'h3 - normal, 'h13 - debug
input rpt;
// ----------------------------------------- // -----------------------------------------
...@@ -154,8 +155,8 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused ...@@ -154,8 +155,8 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
begin begin
skip_too_late = 1'b0; skip_too_late = 1'b0;
disable_need = 1'b0; disable_need = 1'b0;
repetitive = 1'b1; repetitive = rpt; //1'b1;
single = 1'b0; single = !rpt; // 1'b0;
reset_frame = 1'b0; reset_frame = 1'b0;
$display("====== test_afi_rw: write=%d, extra_pages=%d, frame_start= %x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d,@%t", $display("====== test_afi_rw: write=%d, extra_pages=%d, frame_start= %x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d,@%t",
write_ddr3, extra_pages, frame_start_addr, window_full_width, window_width, window_height, window_left, window_top, $time); write_ddr3, extra_pages, frame_start_addr, window_full_width, window_width, window_height, window_left, window_top, $time);
......
includes/x393_simulation_parameters.vh
View file @ 82e11ec7
...@@ -55,15 +55,17 @@ ...@@ -55,15 +55,17 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact // parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd) // parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length // parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR_IMAGE_TYPE0 = "NORM", // "RUN1", parameter SENSOR_IMAGE_TYPE0 = "RUN1", //"NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE1 = "RUN1", parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1", parameter SENSOR_IMAGE_TYPE2 = "RUN1", // "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1", parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18, parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18, parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4, parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4, parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JPEG18,
// parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JPEG18,
// CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode: // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0 // parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
// parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks) // parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
......
memctrl/mcntrl393.v
View file @ 82e11ec7
...@@ -311,6 +311,7 @@ module mcntrl393 #( ...@@ -311,6 +311,7 @@ module mcntrl393 #(
input [255:0] sens_buf_dout, // (), // output[63:0] input [255:0] sens_buf_dout, // (), // output[63:0]
input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer
output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block. output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block.
output reg [3:0] sens_first_wr_in_frame, // single mclk pulse on first write block in each frame
// compressor subsystem interface // compressor subsystem interface
// Buffer interfaces, combined for 4 channels // Buffer interfaces, combined for 4 channels
output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw ( output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw (
...@@ -319,6 +320,7 @@ module mcntrl393 #( ...@@ -319,6 +320,7 @@ module mcntrl393 #(
output [255:0] cmprs_buf_din, // data out output [255:0] cmprs_buf_din, // data out
output [3:0] cmprs_page_ready, // single mclk (posedge) output [3:0] cmprs_page_ready, // single mclk (posedge)
input [3:0] cmprs_next_page, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data input [3:0] cmprs_next_page, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
output reg [3:0] cmprs_first_rd_in_frame, // single mclk pulse on first read block in each frame
// master (sensor) with slave (compressor) synchronization I/Os // master (sensor) with slave (compressor) synchronization I/Os
input [3:0] cmprs_frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive input [3:0] cmprs_frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
...@@ -734,7 +736,9 @@ module mcntrl393 #( ...@@ -734,7 +736,9 @@ module mcntrl393 #(
wire tiled_rw_start_wr16; // start cmd_encod_tiled_32_rw generating command sequence in write mode wire tiled_rw_start_wr16; // start cmd_encod_tiled_32_rw generating command sequence in write mode
wire tiled_rw_start_rd32; // start cmd_encod_tiled_32_rw generating command sequence in read mode wire tiled_rw_start_rd32; // start cmd_encod_tiled_32_rw generating command sequence in read mode
wire tiled_rw_start_wr32; // start cmd_encod_tiled_32_rw generating command sequence in write mode wire tiled_rw_start_wr32; // start cmd_encod_tiled_32_rw generating command sequence in write mode
// for propagating absolute frame number:
reg [3:0] sens_first_wr_pending_r;
reg [3:0] cmprs_first_rd_pending_r;
// Command tree - insert register layer(s) if needed, now just direct assignments // Command tree - insert register layer(s) if needed, now just direct assignments
...@@ -756,8 +760,6 @@ module mcntrl393 #( ...@@ -756,8 +760,6 @@ module mcntrl393 #(
assign cmd_cmprs_ad= cmd_ad; assign cmd_cmprs_ad= cmd_ad;
assign cmd_cmprs_stb= cmd_stb; assign cmd_cmprs_stb= cmd_stb;
// For now - combinatorial, maybe add registers (modify axibram_read) // For now - combinatorial, maybe add registers (modify axibram_read)
assign buf_raddr=axird_raddr; assign buf_raddr=axird_raddr;
assign axird_rdata = (select_buf0rd ? buf0_data : 32'b0) | assign axird_rdata = (select_buf0rd ? buf0_data : 32'b0) |
...@@ -788,6 +790,19 @@ module mcntrl393 #( ...@@ -788,6 +790,19 @@ module mcntrl393 #(
assign select_buf4rd_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0; assign select_buf4rd_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf4wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF4_WR_ADDR) & MCONTR_WR_MASK)==0; assign select_buf4wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF4_WR_ADDR) & MCONTR_WR_MASK)==0;
always @ (posedge mclk) begin
if (mrst) sens_first_wr_pending_r <= 0;
else sens_first_wr_pending_r <= sens_sof | (sens_first_wr_pending_r & ~sens_start_wr);
//cmprs_first_rd_pending_r
sens_first_wr_in_frame <= sens_first_wr_pending_r & sens_start_wr;
if (mrst) cmprs_first_rd_pending_r <= 0;
else cmprs_first_rd_pending_r <= cmprs_frame_start_dst | (cmprs_first_rd_pending_r & ~cmprs_channel_pgm_en);
cmprs_first_rd_in_frame <= cmprs_first_rd_pending_r & cmprs_channel_pgm_en;
end
always @ (posedge axi_clk) begin always @ (posedge axi_clk) begin
if (mrst) select_cmd0 <= 0; if (mrst) select_cmd0 <= 0;
else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w; else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
......
memctrl/mcntrl_linear_rw.v
View file @ 82e11ec7
...@@ -182,6 +182,7 @@ module mcntrl_linear_rw #( ...@@ -182,6 +182,7 @@ module mcntrl_linear_rw #(
reg frame_finished_r; reg frame_finished_r;
wire last_in_row_w; wire last_in_row_w;
wire last_row_w; wire last_row_w;
wire last_block_w;
reg last_block; reg last_block;
reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers
reg [NUM_RC_BURST_BITS-1:0] row_col_r; reg [NUM_RC_BURST_BITS-1:0] row_col_r;
...@@ -340,7 +341,9 @@ module mcntrl_linear_rw #( ...@@ -340,7 +341,9 @@ module mcntrl_linear_rw #(
// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r); // assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
// accelerating pre_want: // accelerating pre_want:
assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ; // assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ;
// last_block was too late to inclusde in pre_want_r1, moving it here
assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend && !last_block;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r}); assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
assign last_row_w= next_y==window_height; assign last_row_w= next_y==window_height;
...@@ -485,8 +488,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -485,8 +488,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page // calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge mclk) begin always @(posedge mclk) begin
// acceletaring pre_want // acceletaring pre_want
pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
// pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
//last_block is too late for pre_want_r1, moving upsteram
pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
if (mrst) par_mod_r<=0; if (mrst) par_mod_r<=0;
else if (pgm_param_w || else if (pgm_param_w ||
xfer_start_r[0] || xfer_start_r[0] ||
......
py393/test_mcntrl.py
View file @ 82e11ec7
...@@ -47,6 +47,7 @@ import time ...@@ -47,6 +47,7 @@ import time
#import shutil #import shutil
import socket import socket
import select import select
import traceback
from import_verilog_parameters import ImportVerilogParameters from import_verilog_parameters import ImportVerilogParameters
#from import_verilog_parameters import VerilogParameters #from import_verilog_parameters import VerilogParameters
...@@ -152,6 +153,7 @@ def execTask(commandLine): ...@@ -152,6 +153,7 @@ def execTask(commandLine):
sFuncArgs+=' <'+str(a)+'>' sFuncArgs+=' <'+str(a)+'>'
print ("Usage:\n%s %s"%(funcName,sFuncArgs)) print ("Usage:\n%s %s"%(funcName,sFuncArgs))
print ("exception message:"+str(e)) print ("exception message:"+str(e))
print (traceback.format_exc())
else: else:
result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs) result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
return result return result
...@@ -480,7 +482,7 @@ USAGE ...@@ -480,7 +482,7 @@ USAGE
print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET)) print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult])) print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult]))
print ("Use 'socket_port [PORT]' to (re-)open socket on PORT (0 or no PORT - disable socket)") print ("Use 'socket_port [PORT]' to (re-)open socket on PORT (0 or no PORT - disable socket)")
# print ("Use 'copy <SRC> <DST> to copy files in file the system") # print ("Use 'copy <SRC> <DST> to copy files in file the system")
print ("Use 'pydev_predefines' to generate a parameter list to paste to vrlg.py, so Pydev will be happy") print ("Use 'pydev_predefines' to generate a parameter list to paste to vrlg.py, so Pydev will be happy")
elif lineList[0].upper() == 'R': elif lineList[0].upper() == 'R':
if len(lineList)>1: if len(lineList)>1:
......
py393/x393_cmprs_afi.py
View file @ 82e11ec7
...@@ -106,15 +106,51 @@ class X393CmprsAfi(object): ...@@ -106,15 +106,51 @@ class X393CmprsAfi(object):
num_lines_print = 20): num_lines_print = 20):
""" """
Returns image metadata (start, length,timestamp) or null Returns image metadata (start, length,timestamp) or null
@param port_afi - AFI port (0/1), currently only 0 @param port_afi - AFI port (0/1), currently only 0, or file path template for simulated mode
@param channel - AFI input channel (0..3) - with 2 AFIs - 0..1 only @param channel - AFI input channel (0..3) - with 2 AFIs - 0..1 only
@return - memory segments (1 or two) with image data, timestamp in numeric and string format @return - memory segments (1 or two) with image data, timestamp in numeric and string format
""" """
if verbose >0: def read_mem(addr):
if ba_data:
return ba_data[addr + 0] + (ba_data[addr + 1] << 8) + (ba_data[addr + 2] << 16) + (ba_data[addr + 3] << 24)
else:
return self.x393_mem.read_mem(addr)
if isinstance(port_afi, (unicode,str)):
data_file = port_afi%channel # for simulated mode
ba_data=bytearray()
try:
with open(data_file) as f:
for l in f:
line = l.strip()
if line:
dl = []
for item in line.split():
dl.append(int(item,16))
ba_data += bytearray(dl)
if verbose > 0:
print ("Read simulated sensor JPEG data from %s data file"%(data_file))
except:
print("Failed to read data from ", data_file)
return
cirbuf_start = 0
circbuf_len = len(ba_data)
print ("len(ba) = %d"%(len(ba_data)))
if verbose > 1:
for i in range(len(ba_data)):
if not (i%16):
print("\n%04x:"%(i),end="")
print ("%02x "%(ba_data[i]),end="")
else:
ba_data = None
if verbose > 0:
print ("\n------------ channel %d --------------"%(channel)) print ("\n------------ channel %d --------------"%(channel))
print ("x393_sens_cmprs.GLBL_WINDOW = ", x393_sens_cmprs.GLBL_WINDOW) print ("x393_sens_cmprs.GLBL_WINDOW = ", x393_sens_cmprs.GLBL_WINDOW)
if (self.DRY_MODE): # if (self.DRY_MODE):
return None # return None
CCAM_MMAP_META = 12 # extra bytes included at the end of each frame (last aligned to 32 bytes) CCAM_MMAP_META = 12 # extra bytes included at the end of each frame (last aligned to 32 bytes)
CCAM_MMAP_META_LENGTH = 4 # displacement to length frame length data from the end of the 32-byte aligned frame slot CCAM_MMAP_META_LENGTH = 4 # displacement to length frame length data from the end of the 32-byte aligned frame slot
CCAM_MMAP_META_USEC = 8 # // (negative) displacement to USEC data - 20 bits (frame timestamp) CCAM_MMAP_META_USEC = 8 # // (negative) displacement to USEC data - 20 bits (frame timestamp)
...@@ -122,20 +158,25 @@ class X393CmprsAfi(object): ...@@ -122,20 +158,25 @@ class X393CmprsAfi(object):
# offs_len32 = 0x20 - CCAM_MMAP_META_LENGTH # 0x1c #from last image 32-byte chunk to lower of 3-byte image length (MSB == 0xff) # offs_len32 = 0x20 - CCAM_MMAP_META_LENGTH # 0x1c #from last image 32-byte chunk to lower of 3-byte image length (MSB == 0xff)
if ba_data:
next_image = len(ba_data)
else:
next_image = self.afi_mux_get_image_pointer(port_afi = port_afi, next_image = self.afi_mux_get_image_pointer(port_afi = port_afi,
channel = channel) channel = channel)
# Bug - got 0x20 more than start of the new image # Bug - got 0x20 more than start of the new image
last_image_chunk = next_image - 0x40 last_image_chunk = next_image - 0x40
if last_image_chunk < 0: if last_image_chunk < 0:
last_image_chunk += circbuf_len last_image_chunk += circbuf_len
len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH)) ## len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
len32 = read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
markerFF = len32 >> 24 markerFF = len32 >> 24
if (markerFF != 0xff): if (markerFF != 0xff):
print ("Failed to get 0xff marker at offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"% print ("Failed to get 0xff marker at offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"%
(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32,next_image)) (cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH) + 3,len32,next_image))
if verbose >0: if verbose >0:
for a in range ( next_image - (0x10 * num_lines_print), next_image + (0x10 * num_lines_print), 4): for a in range ( next_image - (0x10 * num_lines_print), next_image + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a) ## d = self.x393_mem.read_mem(cirbuf_start + a)
d = read_mem(cirbuf_start + a)
if (a % 16) == 0: if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" ) print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "") print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
...@@ -146,7 +187,8 @@ class X393CmprsAfi(object): ...@@ -146,7 +187,8 @@ class X393CmprsAfi(object):
last_image_chunk = next_image - 0x40 last_image_chunk = next_image - 0x40
if last_image_chunk < 0: if last_image_chunk < 0:
last_image_chunk += circbuf_len last_image_chunk += circbuf_len
len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH)) ## len32 = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
len32 = read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_LENGTH))
markerFF = len32 >> 24 markerFF = len32 >> 24
if (markerFF != 0xff): if (markerFF != 0xff):
print ("**** Failed to get 0xff marker at CORRECTED offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"% print ("**** Failed to get 0xff marker at CORRECTED offset 0x%08x - length word = 0x%08x, next_image = 0x%08x)"%
...@@ -166,7 +208,8 @@ class X393CmprsAfi(object): ...@@ -166,7 +208,8 @@ class X393CmprsAfi(object):
img_start += circbuf_len img_start += circbuf_len
if verbose >0: if verbose >0:
for a in range ( img_start, img_start + (0x10 * num_lines_print), 4): for a in range ( img_start, img_start + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a) ## d = self.x393_mem.read_mem(cirbuf_start + a)
d = read_mem(cirbuf_start + a)
if (a % 16) == 0: if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" ) print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "") print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
...@@ -175,14 +218,17 @@ class X393CmprsAfi(object): ...@@ -175,14 +218,17 @@ class X393CmprsAfi(object):
a = a0 a = a0
if (a < 0): if (a < 0):
a -=circbuf_len a -=circbuf_len
d = self.x393_mem.read_mem(cirbuf_start + a) ## d = self.x393_mem.read_mem(cirbuf_start + a)
d = read_mem(cirbuf_start + a)
if (a % 16) == 0: if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" ) print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "") print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
print() print()
sec = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_SEC)) ## sec = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_SEC))
usec = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_USEC)) sec = read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_SEC))
## usec = self.x393_mem.read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_USEC))
usec = read_mem(cirbuf_start + last_image_chunk + (0x20 - CCAM_MMAP_META_USEC))
fsec=sec + usec/1000000.0 fsec=sec + usec/1000000.0
try: try:
tstr = time.strftime("%b %d %Y %H:%M:%S", time.gmtime(fsec)) tstr = time.strftime("%b %d %Y %H:%M:%S", time.gmtime(fsec))
...@@ -196,6 +242,8 @@ class X393CmprsAfi(object): ...@@ -196,6 +242,8 @@ class X393CmprsAfi(object):
result = {"timestamp": fsec, result = {"timestamp": fsec,
"timestring": tstr, "timestring": tstr,
"segments":segments} "segments":segments}
if ba_data:
result["bindata"] = ba_data
if verbose >0 : if verbose >0 :
print ("Inserted bytes after image before meta = 0x%x"%(inserted_bytes)) print ("Inserted bytes after image before meta = 0x%x"%(inserted_bytes))
print ("Image start (relative to cirbuf) = 0x%x, image length = 0x%x"%(img_start, len32 )) print ("Image start (relative to cirbuf) = 0x%x, image length = 0x%x"%(img_start, len32 ))
......
py393/x393_jpeg.py
View file @ 82e11ec7
...@@ -156,6 +156,7 @@ HUFFVAL = "huffval" ...@@ -156,6 +156,7 @@ HUFFVAL = "huffval"
LENGTH = "length" LENGTH = "length"
VALUE = "value" VALUE = "value"
FPGA_HUFFMAN_TABLE = "fpga_huffman_table" FPGA_HUFFMAN_TABLE = "fpga_huffman_table"
SIMULATION_JPEG_DATA = "../simulation_data/compressor_out_%d.dat"
class X393Jpeg(object): class X393Jpeg(object):
DRY_MODE= True # True DRY_MODE= True # True
...@@ -271,8 +272,8 @@ class X393Jpeg(object): ...@@ -271,8 +272,8 @@ class X393Jpeg(object):
for i,t in enumerate(STD_QUANT_TBLS[t_name]): for i,t in enumerate(STD_QUANT_TBLS[t_name]):
d = max(1,min((t * q + 50) // 100, 255)) d = max(1,min((t * q + 50) // 100, 255))
tbl[ZIG_ZAG[i]] = d tbl[ZIG_ZAG[i]] = d
# fpga_tbl[i] = min(((0x20000 // d) + 1) >> 1, 0xffff) fpga_tbl[i] = min(((0x20000 // d) + 1) >> 1, 0xffff)
fpga_tbl[ZIG_ZAG[i]] = min(((0x20000 // d) + 1) >> 1, 0xffff) ## fpga_tbl[ZIG_ZAG[i]] = min(((0x20000 // d) + 1) >> 1, 0xffff)
rslt.append(tbl) rslt.append(tbl)
fpga.append(fpga_tbl) fpga.append(fpga_tbl)
if verbose > 0: if verbose > 0:
...@@ -770,7 +771,7 @@ class X393Jpeg(object): ...@@ -770,7 +771,7 @@ class X393Jpeg(object):
portrait = False, portrait = False,
# color_mode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved # color_mode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved
byrshift = 0, byrshift = 0,
server_root = "/www/pages/", server_root = None, # "/www/pages/",
verbose = 1): verbose = 1):
""" """
Create JPEG image from the latest acquired in the camera Create JPEG image from the latest acquired in the camera
...@@ -783,6 +784,11 @@ class X393Jpeg(object): ...@@ -783,6 +784,11 @@ class X393Jpeg(object):
@param server_root - files ystem path to the web server root directory @param server_root - files ystem path to the web server root directory
@param verbose - verbose level @param verbose - verbose level
""" """
if server_root is None:
if (self.DRY_MODE):
server_root = "../www/"
else:
server_root = "/www/pages/"
allFiles = False allFiles = False
if file_path[0] == "/": if file_path[0] == "/":
server_root = "" # just do not add anything server_root = "" # just do not add anything
...@@ -849,6 +855,9 @@ class X393Jpeg(object): ...@@ -849,6 +855,9 @@ class X393Jpeg(object):
print ("window[width]",window["width"]) print ("window[width]",window["width"])
print ("window[cmode]",window["cmode"]) print ("window[cmode]",window["cmode"])
print ("window=",window) print ("window=",window)
jpeg_data = self.jpegheader_create ( jpeg_data = self.jpegheader_create (
y_quality = y_quality, y_quality = y_quality,
c_quality = c_quality, c_quality = c_quality,
...@@ -858,13 +867,23 @@ class X393Jpeg(object): ...@@ -858,13 +867,23 @@ class X393Jpeg(object):
color_mode = window["cmode"], #color_mode, color_mode = window["cmode"], #color_mode,
byrshift = byrshift, byrshift = byrshift,
verbose = verbose - 1) verbose = verbose - 1)
if self.DRY_MODE:
meta = self.x393_cmprs_afi.afi_mux_get_image_meta(
port_afi = SIMULATION_JPEG_DATA, # 0,
channel = channel,
cirbuf_start = 0, #x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
circbuf_len = 0, #x393_sens_cmprs.GLBL_CIRCBUF_ENDS[channel] - x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
verbose = verbose)
else:
meta = self.x393_cmprs_afi.afi_mux_get_image_meta( meta = self.x393_cmprs_afi.afi_mux_get_image_meta(
port_afi = 0, port_afi = 0,
channel = channel, channel = channel,
cirbuf_start = x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel], cirbuf_start = x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
circbuf_len = x393_sens_cmprs.GLBL_CIRCBUF_CHN_SIZE, # circbuf_len = x393_sens_cmprs.GLBL_CIRCBUF_CHN_SIZE,
circbuf_len = x393_sens_cmprs.GLBL_CIRCBUF_ENDS[channel] - x393_sens_cmprs.GLBL_CIRCBUF_STARTS[channel],
verbose = verbose) verbose = verbose)
if verbose > 0 : if verbose > 2 :
print ("meta = ",meta) print ("meta = ",meta)
if verbose > 1 : if verbose > 1 :
for s in meta["segments"]: for s in meta["segments"]:
...@@ -874,6 +893,9 @@ class X393Jpeg(object): ...@@ -874,6 +893,9 @@ class X393Jpeg(object):
for s in meta["segments"]: for s in meta["segments"]:
if verbose > 1 : if verbose > 1 :
print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1])) print ("start_address = 0x%x, length = 0x%x"%(s[0],s[1]))
if 'bindata' in meta:
bf.write(meta['bindata'][s[0] : s[0] + s[1]])
else:
self.x393_mem._mem_write_to_file (bf = bf, self.x393_mem._mem_write_to_file (bf = bf,
start_addr = s[0], start_addr = s[0],
length = s[1]) length = s[1])
...@@ -976,6 +998,7 @@ setup_all_sensors True None 0x4 ...@@ -976,6 +998,7 @@ setup_all_sensors True None 0x4
################## Parallel ################## ################## Parallel ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
#fpga_shutdown
setupSensorsPower "PAR12" setupSensorsPower "PAR12"
measure_all "*DI" measure_all "*DI"
setup_all_sensors True None 0xf setup_all_sensors True None 0xf
...@@ -997,6 +1020,11 @@ axi_write_single_w 0x686 0x079800a3 ...@@ -997,6 +1020,11 @@ axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3 axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3 axi_write_single_w 0x6b6 0x079800a3
#Gamma 0.57 #Gamma 0.57
program_gamma all 0 0.57 0.04 program_gamma all 0 0.57 0.04
......
py393/x393_mcntrl_membridge.py
View file @ 82e11ec7
...@@ -206,7 +206,7 @@ class X393McntrlMembridge(object): ...@@ -206,7 +206,7 @@ class X393McntrlMembridge(object):
size64 = BUFFER_LEN//8 # input [28:0] size64; # size of the system memory range in 64-bit words size64 = BUFFER_LEN//8 # input [28:0] size64; # size of the system memory range in 64-bit words
if quiet <2: if quiet <2:
print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet)) print("membridge_setup(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet))
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_SIZE64, size64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_SIZE64, size64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64);
......
py393/x393_sens_cmprs.py
View file @ 82e11ec7
...@@ -64,15 +64,58 @@ BUFFER_ADDRESS_NAME = 'buffer_address' ...@@ -64,15 +64,58 @@ BUFFER_ADDRESS_NAME = 'buffer_address'
BUFFER_PAGES_NAME = 'buffer_pages' BUFFER_PAGES_NAME = 'buffer_pages'
BUFFER_ADDRESS = None # in bytes BUFFER_ADDRESS = None # in bytes
BUFFER_LEN = None # in bytes BUFFER_LEN = None # in bytes
BUFFER_ADDRESS_NAME = 'buffer_address'
BUFFER_PAGES_NAME = 'buffer_pages'
BUFFER_H2D_ADDRESS_NAME = 'buffer_address_h2d'
BUFFER_H2D_PAGES_NAME = 'buffer_pages_h2d'
BUFFER_D2H_ADDRESS_NAME = 'buffer_address_d2h'
BUFFER_D2H_PAGES_NAME = 'buffer_pages_d2h'
BUFFER_BIDIR_ADDRESS_NAME = 'buffer_address_bidir'
BUFFER_BIDIR_PAGES_NAME = 'buffer_pages_bidir'
BUFFER_FOR_CPU = 'sync_for_cpu' # add suffix
BUFFER_FOR_DEVICE = 'sync_for_device' # add suffix
BUFFER_FOR_CPU_H2D = 'sync_for_cpu_h2d'
BUFFER_FOR_DEVICE_H2D = 'sync_for_device_h2d'
BUFFER_FOR_CPU_D2H = 'sync_for_cpu_d2h'
BUFFER_FOR_DEVICE_D2H = 'sync_for_device_d2h'
BUFFER_FOR_CPU_BIDIR = 'sync_for_cpu_bidir'
BUFFER_FOR_DEVICE_BIDIR = 'sync_for_device_bidir'
GLBL_CIRCBUF_CHN_SIZE = None GLBL_CIRCBUF_CHN_SIZE = None
GLBL_CIRCBUF_STARTS = None GLBL_CIRCBUF_STARTS = None
GLBL_CIRCBUF_ENDS = None
GLBL_CIRCBUF_END = None GLBL_CIRCBUF_END = None
GLBL_MEMBRIDGE_START = None GLBL_MEMBRIDGE_START = None
GLBL_MEMBRIDGE_END = None GLBL_MEMBRIDGE_END = None
GLBL_MEMBRIDGE_H2D_START = None
GLBL_MEMBRIDGE_H2D_END = None
GLBL_MEMBRIDGE_D2H_START = None
GLBL_MEMBRIDGE_D2H_END = None
GLBL_BUFFER_END = None GLBL_BUFFER_END = None
GLBL_WINDOW = None GLBL_WINDOW = None
BUFFER_ADDRESS = None # in bytes
BUFFER_LEN = None # in bytes
BUFFER_ADDRESS_H2D = None # in bytes
BUFFER_LEN_H2D = None # in bytes
BUFFER_ADDRESS_D2H = None # in bytes
BUFFER_LEN_D2H = None # in bytes
BUFFER_ADDRESS_BIDIR = None # in bytes
BUFFER_LEN_BIDIR = None # in bytes
#SENSOR_INTERFACE_PARALLEL = "PAR12" #SENSOR_INTERFACE_PARALLEL = "PAR12"
#SENSOR_INTERFACE_HISPI = "HISPI" #SENSOR_INTERFACE_HISPI = "HISPI"
# for now - single sensor type per interface # for now - single sensor type per interface
...@@ -102,7 +145,10 @@ class X393SensCmprs(object): ...@@ -102,7 +145,10 @@ class X393SensCmprs(object):
x393Membridge = None x393Membridge = None
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None): def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
global BUFFER_ADDRESS, BUFFER_LEN # global BUFFER_ADDRESS, BUFFER_LEN
global BUFFER_ADDRESS, BUFFER_LEN, COMMAND_ADDRESS, DATAIN_ADDRESS, DATAOUT_ADDRESS
global BUFFER_ADDRESS_H2D, BUFFER_LEN_H2D, BUFFER_ADDRESS_D2H, BUFFER_LEN_D2H, BUFFER_ADDRESS_BIDIR, BUFFER_LEN_BIDIR
self.DEBUG_MODE= debug_mode self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode) self.x393_mem= X393Mem(debug_mode,dry_mode)
...@@ -122,8 +168,16 @@ class X393SensCmprs(object): ...@@ -122,8 +168,16 @@ class X393SensCmprs(object):
except: except:
pass pass
if dry_mode: if dry_mode:
BUFFER_ADDRESS=0x27900000 BUFFER_ADDRESS = 0x38100000
BUFFER_LEN= 0x6400000 BUFFER_LEN = 0x06400000
BUFFER_ADDRESS_H2D = 0x38100000
BUFFER_LEN_H2D = 0x06400000
BUFFER_ADDRESS_D2H = 0x38100000
BUFFER_LEN_D2H = 0x06400000
BUFFER_ADDRESS_BIDIR = 0x38100000
BUFFER_LEN_BIDIR = 0x06400000
print ("Running in simulated mode, using hard-coded addresses:")
print ("Running in simulated mode, using hard-coded addresses:") print ("Running in simulated mode, using hard-coded addresses:")
else: else:
try: try:
...@@ -136,6 +190,41 @@ class X393SensCmprs(object): ...@@ -136,6 +190,41 @@ class X393SensCmprs(object):
print('BUFFER_ADDRESS=', BUFFER_ADDRESS) print('BUFFER_ADDRESS=', BUFFER_ADDRESS)
print('BUFFER_LEN=', BUFFER_LEN) print('BUFFER_LEN=', BUFFER_LEN)
return return
try:
with open(MEM_PATH + BUFFER_H2D_ADDRESS_NAME) as sysfile:
BUFFER_ADDRESS_H2D=int(sysfile.read(),0)
with open(MEM_PATH+BUFFER_H2D_PAGES_NAME) as sysfile:
BUFFER_LEN_H2D=PAGE_SIZE*int(sysfile.read(),0)
except:
print("Failed to get reserved physical memory range")
print('BUFFER_ADDRESS_H2D=',BUFFER_ADDRESS_H2D)
print('BUFFER_LEN_H2D=',BUFFER_LEN_H2D)
return
try:
with open(MEM_PATH + BUFFER_D2H_ADDRESS_NAME) as sysfile:
BUFFER_ADDRESS_D2H=int(sysfile.read(),0)
with open(MEM_PATH+BUFFER_D2H_PAGES_NAME) as sysfile:
BUFFER_LEN_D2H=PAGE_SIZE*int(sysfile.read(),0)
except:
print("Failed to get reserved physical memory range")
print('BUFFER_ADDRESS_D2H=',BUFFER_ADDRESS_D2H)
print('BUFFER_LEN_D2H=',BUFFER_LEN_D2H)
return
try:
with open(MEM_PATH + BUFFER_BIDIR_ADDRESS_NAME) as sysfile:
BUFFER_ADDRESS_BIDIR=int(sysfile.read(),0)
with open(MEM_PATH+BUFFER_BIDIR_PAGES_NAME) as sysfile:
BUFFER_LEN_BIDIR=PAGE_SIZE*int(sysfile.read(),0)
except:
print("Failed to get reserved physical memory range")
print('BUFFER_ADDRESS_BIDIR=',BUFFER_ADDRESS_BIDIR)
print('BUFFER_LEN_BIDIR=',BUFFER_LEN_BIDIR)
return
print('X393SensCmprs: BUFFER_ADDRESS=0x%x'%(BUFFER_ADDRESS)) print('X393SensCmprs: BUFFER_ADDRESS=0x%x'%(BUFFER_ADDRESS))
print('X393SensCmprs: BUFFER_LEN=0x%x'%(BUFFER_LEN)) print('X393SensCmprs: BUFFER_LEN=0x%x'%(BUFFER_LEN))
def get_histogram_byte_start(self): # should be 4KB page aligned def get_histogram_byte_start(self): # should be 4KB page aligned
...@@ -217,12 +306,12 @@ class X393SensCmprs(object): ...@@ -217,12 +306,12 @@ class X393SensCmprs(object):
return return
if quiet == 0: if quiet == 0:
print ("Turning on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair])) print ("Turning on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
time.sleep(0.2) time.sleep(0.3)
with open (POWER393_PATH + "/channels_en","w") as f: with open (POWER393_PATH + "/channels_en","w") as f:
print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f) print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f)
if quiet == 0: if quiet == 0:
print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair])) print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
time.sleep(0.2) time.sleep(0.3)
with open (POWER393_PATH + "/channels_en","w") as f: with open (POWER393_PATH + "/channels_en","w") as f:
print(("vp33sens01", "vp33sens23")[sub_pair], file = f) print(("vp33sens01", "vp33sens23")[sub_pair], file = f)
if quiet == 0: if quiet == 0:
...@@ -268,7 +357,7 @@ class X393SensCmprs(object): ...@@ -268,7 +357,7 @@ class X393SensCmprs(object):
# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr? # frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?
# frame_start_address_inc, # frame_start_address_inc,
last_buf_frame = 1, # - just 2-frame buffer last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = 0x180, # 0x90 fo 1x colorsat_blue = 0x120, # 0x90 fo 1x
colorsat_red = 0x16c, # 0xb6 for x1 colorsat_red = 0x16c, # 0xb6 for x1
clk_sel = 1, # 1 clk_sel = 1, # 1
histogram_left = None, # 0, histogram_left = None, # 0,
...@@ -636,7 +725,7 @@ class X393SensCmprs(object): ...@@ -636,7 +725,7 @@ class X393SensCmprs(object):
portrait = None, portrait = None,
gamma = None, gamma = None,
black = None, # 0.04 black = None, # 0.04
colorsat_blue = None, # colorsat_blue, #0x180 # 0x90 for 1x colorsat_blue = None, # colorsat_blue, #0x120 # 0x90 for 1x
colorsat_red = None, # colorsat_red, #0x16c, # 0xb6 for x1 colorsat_red = None, # colorsat_red, #0x16c, # 0xb6 for x1
verbose = 1 verbose = 1
): ):
...@@ -750,17 +839,28 @@ class X393SensCmprs(object): ...@@ -750,17 +839,28 @@ class X393SensCmprs(object):
""" """
@param circbuf_chn_size - circular buffer size for each channel, in bytes @param circbuf_chn_size - circular buffer size for each channel, in bytes
""" """
global GLBL_CIRCBUF_CHN_SIZE, GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_END, GLBL_MEMBRIDGE_START, GLBL_MEMBRIDGE_END, GLBL_BUFFER_END global GLBL_CIRCBUF_CHN_SIZE, GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_ENDS, GLBL_CIRCBUF_END, GLBL_MEMBRIDGE_START, GLBL_MEMBRIDGE_END, GLBL_BUFFER_END
global GLBL_MEMBRIDGE_H2D_START, GLBL_MEMBRIDGE_H2D_END, GLBL_MEMBRIDGE_D2H_START, GLBL_MEMBRIDGE_D2H_END
global BUFFER_ADDRESS_H2D, BUFFER_LEN_H2D, BUFFER_ADDRESS_D2H, BUFFER_LEN_D2H
circbuf_start = self.get_circbuf_byte_start() circbuf_start = self.get_circbuf_byte_start()
GLBL_BUFFER_END= self.get_circbuf_byte_end() GLBL_BUFFER_END= self.get_circbuf_byte_end()
GLBL_CIRCBUF_CHN_SIZE = circbuf_chn_size GLBL_CIRCBUF_CHN_SIZE = circbuf_chn_size
GLBL_CIRCBUF_STARTS=[] GLBL_CIRCBUF_STARTS=[]
GLBL_CIRCBUF_ENDS=[]
for i in range(16): for i in range(16):
GLBL_CIRCBUF_STARTS.append(circbuf_start + i*circbuf_chn_size) GLBL_CIRCBUF_STARTS.append(circbuf_start + i*circbuf_chn_size)
GLBL_CIRCBUF_ENDS.append(circbuf_start + (i+1)*circbuf_chn_size)
GLBL_CIRCBUF_END = circbuf_start + 4*GLBL_CIRCBUF_CHN_SIZE GLBL_CIRCBUF_END = circbuf_start + 4*GLBL_CIRCBUF_CHN_SIZE
GLBL_MEMBRIDGE_START = GLBL_CIRCBUF_END GLBL_MEMBRIDGE_START = GLBL_CIRCBUF_END
GLBL_MEMBRIDGE_END = GLBL_BUFFER_END GLBL_MEMBRIDGE_END = GLBL_BUFFER_END
GLBL_MEMBRIDGE_H2D_START = BUFFER_ADDRESS_H2D
GLBL_MEMBRIDGE_H2D_END = BUFFER_ADDRESS_H2D + BUFFER_LEN_H2D
GLBL_MEMBRIDGE_D2H_START = BUFFER_ADDRESS_D2H
GLBL_MEMBRIDGE_D2H_END = BUFFER_ADDRESS_D2H + BUFFER_LEN_D2H
if verbose >0 : if verbose >0 :
print ("compressor system memory buffers:") print ("compressor system memory buffers:")
print ("circbuf start 0 = 0x%x"%(GLBL_CIRCBUF_STARTS[0])) print ("circbuf start 0 = 0x%x"%(GLBL_CIRCBUF_STARTS[0]))
...@@ -771,6 +871,12 @@ class X393SensCmprs(object): ...@@ -771,6 +871,12 @@ class X393SensCmprs(object):
print ("membridge start = 0x%x"%(GLBL_MEMBRIDGE_START)) print ("membridge start = 0x%x"%(GLBL_MEMBRIDGE_START))
print ("membridge end = 0x%x"%(GLBL_MEMBRIDGE_END)) print ("membridge end = 0x%x"%(GLBL_MEMBRIDGE_END))
print ("membridge size = %d bytes"%(GLBL_MEMBRIDGE_END - GLBL_MEMBRIDGE_START)) print ("membridge size = %d bytes"%(GLBL_MEMBRIDGE_END - GLBL_MEMBRIDGE_START))
print ("membridge h2d_start = 0x%x"%(GLBL_MEMBRIDGE_H2D_START))
print ("membridge h2d end = 0x%x"%(GLBL_MEMBRIDGE_H2D_END))
print ("membridge h2d size = %d bytes"%(GLBL_MEMBRIDGE_H2D_END - GLBL_MEMBRIDGE_H2D_START))
print ("membridge h2d start = 0x%x"%(GLBL_MEMBRIDGE_D2H_START))
print ("membridge h2d end = 0x%x"%(GLBL_MEMBRIDGE_D2H_END))
print ("membridge h2d size = %d bytes"%(GLBL_MEMBRIDGE_D2H_END - GLBL_MEMBRIDGE_D2H_START))
print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END)) print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END))
def setup_cmdmux (self): def setup_cmdmux (self):
#Will report frame number for each channel #Will report frame number for each channel
...@@ -866,7 +972,7 @@ class X393SensCmprs(object): ...@@ -866,7 +972,7 @@ class X393SensCmprs(object):
window_left = None, # 0, # 0 window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1? window_top = None, # 0, # 0? 1?
last_buf_frame = 1, # - just 2-frame buffer last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = 0x180, # 0x90 for 1x colorsat_blue = 0x120, # 0x90 for 1x
colorsat_red = 0x16c, # 0xb6 for x1 colorsat_red = 0x16c, # 0xb6 for x1
verbose = 1): verbose = 1):
""" """
...@@ -903,7 +1009,7 @@ class X393SensCmprs(object): ...@@ -903,7 +1009,7 @@ class X393SensCmprs(object):
try: try:
if (chn == all) or (chn[0].upper() == "A"): #all is a built-in function if (chn == all) or (chn[0].upper() == "A"): #all is a built-in function
for chn in range(4): for chn in range(4):
self. setup_compressor(self, self. setup_compressor( #self,
chn = chn, chn = chn,
cmode = cmode, cmode = cmode,
qbank = qbank, qbank = qbank,
...@@ -917,7 +1023,7 @@ class X393SensCmprs(object): ...@@ -917,7 +1023,7 @@ class X393SensCmprs(object):
window_left = None, # 0, # 0 window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1? window_top = None, # 0, # 0? 1?
last_buf_frame = last_buf_frame, # - just 2-frame buffer last_buf_frame = last_buf_frame, # - just 2-frame buffer
colorsat_blue = colorsat_blue, #0x180 # 0x90 for 1x colorsat_blue = colorsat_blue, #0x120 # 0x90 for 1x
colorsat_red = colorsat_red, #0x16c, # 0xb6 for x1 colorsat_red = colorsat_red, #0x16c, # 0xb6 for x1
verbose = verbose) verbose = verbose)
return return
...@@ -996,7 +1102,7 @@ class X393SensCmprs(object): ...@@ -996,7 +1102,7 @@ class X393SensCmprs(object):
print ("frame_sa_inc = 0x%x"%(frame_start_address_inc)) print ("frame_sa_inc = 0x%x"%(frame_start_address_inc))
print ("last_frame_num = 0x%x"%(last_buf_frame)) print ("last_frame_num = 0x%x"%(last_buf_frame))
print ("frame_full_width = 0x%x"%(frame_full_width)) print ("frame_full_width = 0x%x"%(frame_full_width))
print ("window_width = 0x%x"%(width32 * 2 )) # window_width >> 4)) # width in 16 - bursts, made evem print ("window_width = 0x%x (in 16 - bursts, made even)"%(width32 * 2 )) # window_width >> 4)) # width in 16 - bursts, made even
print ("window_height = 0x%x"%(window_height & 0xfffffff0)) print ("window_height = 0x%x"%(window_height & 0xfffffff0))
print ("window_left = 0x%x"%(left_tiles32 * 2)) # window_left >> 4)) # left in 16-byte bursts, made even print ("window_left = 0x%x"%(left_tiles32 * 2)) # window_left >> 4)) # left in 16-byte bursts, made even
print ("window_top = 0x%x"%(window_top)) print ("window_top = 0x%x"%(window_top))
...@@ -1035,7 +1141,7 @@ class X393SensCmprs(object): ...@@ -1035,7 +1141,7 @@ class X393SensCmprs(object):
window_top = None, # 0, # 0? 1? window_top = None, # 0, # 0? 1?
compressor_left_margin = 0, #0?`1? compressor_left_margin = 0, #0?`1?
last_buf_frame = 1, # - just 2-frame buffer last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = 0x180, # 0x90 fo 1x colorsat_blue = 0x120, # 0x90 fo 1x
colorsat_red = 0x16c, # 0xb6 for x1 colorsat_red = 0x16c, # 0xb6 for x1
clk_sel = 1, # 1 clk_sel = 1, # 1
histogram_left = None, histogram_left = None,
...@@ -1082,7 +1188,8 @@ class X393SensCmprs(object): ...@@ -1082,7 +1188,8 @@ class X393SensCmprs(object):
@param verbose - verbose level @param verbose - verbose level
@return True if all done, False if exited prematurely by exit_step @return True if all done, False if exited prematurely by exit_step
""" """
global GLBL_CIRCBUF_CHN_SIZE, GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_END, GLBL_MEMBRIDGE_START, GLBL_MEMBRIDGE_END, GLBL_BUFFER_END, GLBL_WINDOW global GLBL_CIRCBUF_CHN_SIZE, GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_ENDS, GLBL_CIRCBUF_END, GLBL_MEMBRIDGE_START, GLBL_MEMBRIDGE_END, GLBL_BUFFER_END, GLBL_WINDOW
global GLBL_MEMBRIDGE_H2D_START, GLBL_MEMBRIDGE_H2D_END, GLBL_MEMBRIDGE_D2H_START, GLBL_MEMBRIDGE_D2H_END
sensorType = self.x393Sensor.getSensorInterfaceType() sensorType = self.x393Sensor.getSensorInterfaceType()
if verbose > 0 : if verbose > 0 :
...@@ -1135,17 +1242,32 @@ class X393SensCmprs(object): ...@@ -1135,17 +1242,32 @@ class X393SensCmprs(object):
afi_cmprs1_sa = GLBL_CIRCBUF_STARTS[1] // 32 afi_cmprs1_sa = GLBL_CIRCBUF_STARTS[1] // 32
afi_cmprs2_sa = GLBL_CIRCBUF_STARTS[2] // 32 afi_cmprs2_sa = GLBL_CIRCBUF_STARTS[2] // 32
afi_cmprs3_sa = GLBL_CIRCBUF_STARTS[3] // 32 afi_cmprs3_sa = GLBL_CIRCBUF_STARTS[3] // 32
afi_cmprs_len = GLBL_CIRCBUF_CHN_SIZE // 32 afi_cmprs0_len = (GLBL_CIRCBUF_ENDS[0] - GLBL_CIRCBUF_STARTS[0]) // 32
afi_cmprs1_len = (GLBL_CIRCBUF_ENDS[1] - GLBL_CIRCBUF_STARTS[1]) // 32
afi_cmprs2_len = (GLBL_CIRCBUF_ENDS[2] - GLBL_CIRCBUF_STARTS[2]) // 32
afi_cmprs3_len = (GLBL_CIRCBUF_ENDS[3] - GLBL_CIRCBUF_STARTS[3]) // 32
# afi_cmprs_len = GLBL_CIRCBUF_CHN_SIZE // 32
if verbose >0 : if verbose >0 :
print ("compressor system memory buffers:") print ("compressor system memory buffers:")
print ("circbuf start 0 = 0x%x"%(GLBL_CIRCBUF_STARTS[0])) print ("circbuf start 0 = 0x%x"%(GLBL_CIRCBUF_STARTS[0]))
print ("circbuf start 1 = 0x%x"%(GLBL_CIRCBUF_STARTS[1])) print ("circbuf start 1 = 0x%x"%(GLBL_CIRCBUF_STARTS[1]))
print ("circbuf start 2 = 0x%x"%(GLBL_CIRCBUF_STARTS[2])) print ("circbuf start 2 = 0x%x"%(GLBL_CIRCBUF_STARTS[2]))
print ("circbuf start 3 = 0x%x"%(GLBL_CIRCBUF_STARTS[3])) print ("circbuf start 3 = 0x%x"%(GLBL_CIRCBUF_STARTS[3]))
print ("circbuf end 0 = 0x%x"%(GLBL_CIRCBUF_ENDS[0]))
print ("circbuf end 1 = 0x%x"%(GLBL_CIRCBUF_ENDS[1]))
print ("circbuf end 2 = 0x%x"%(GLBL_CIRCBUF_ENDS[2]))
print ("circbuf end 3 = 0x%x"%(GLBL_CIRCBUF_ENDS[3]))
print ("circbuf end = 0x%x"%(GLBL_BUFFER_END)) print ("circbuf end = 0x%x"%(GLBL_BUFFER_END))
print ("membridge start = 0x%x"%(GLBL_MEMBRIDGE_START)) print ("membridge start = 0x%x"%(GLBL_MEMBRIDGE_START))
print ("membridge end = 0x%x"%(GLBL_MEMBRIDGE_END)) print ("membridge end = 0x%x"%(GLBL_MEMBRIDGE_END))
print ("membridge size = %d bytes"%(GLBL_MEMBRIDGE_END - GLBL_MEMBRIDGE_START)) print ("membridge size = %d bytes"%(GLBL_MEMBRIDGE_END - GLBL_MEMBRIDGE_START))
print ("membridge h2d_start = 0x%x"%(GLBL_MEMBRIDGE_H2D_START))
print ("membridge h2d end = 0x%x"%(GLBL_MEMBRIDGE_H2D_END))
print ("membridge h2d size = %d bytes"%(GLBL_MEMBRIDGE_H2D_END - GLBL_MEMBRIDGE_H2D_START))
print ("membridge h2d start = 0x%x"%(GLBL_MEMBRIDGE_D2H_START))
print ("membridge h2d end = 0x%x"%(GLBL_MEMBRIDGE_D2H_END))
print ("membridge h2d size = %d bytes"%(GLBL_MEMBRIDGE_D2H_END - GLBL_MEMBRIDGE_D2H_START))
print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END)) print ("memory buffer end = 0x%x"%(GLBL_BUFFER_END))
self.program_status_debug (3,0) self.program_status_debug (3,0)
...@@ -1158,9 +1280,14 @@ class X393SensCmprs(object): ...@@ -1158,9 +1280,14 @@ class X393SensCmprs(object):
window_left = window_left, window_left = window_left,
window_top = window_top, window_top = window_top,
last_buf_frame = last_buf_frame, last_buf_frame = last_buf_frame,
membridge_start = GLBL_MEMBRIDGE_START, # membridge_start = GLBL_MEMBRIDGE_START,
membridge_end = GLBL_MEMBRIDGE_END, # membridge_end = GLBL_MEMBRIDGE_END,
#Setting up to read raw sensor data
membridge_start = GLBL_MEMBRIDGE_D2H_START,
membridge_end = GLBL_MEMBRIDGE_D2H_END,
verbose = verbose) verbose = verbose)
self.sync_for_device('D2H', GLBL_MEMBRIDGE_D2H_START, GLBL_MEMBRIDGE_D2H_END - GLBL_MEMBRIDGE_D2H_START) # command and PRD table
# if verbose >0 : # if verbose >0 :
# print ("===================== Sensor power setup: sensor ports 0 and 1 =========================") # print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
...@@ -1219,13 +1346,13 @@ class X393SensCmprs(object): ...@@ -1219,13 +1346,13 @@ class X393SensCmprs(object):
# mode == 3 - show current pointer, confirmed written to the system memory # mode == 3 - show current pointer, confirmed written to the system memory
report_mode = 0, # = 0, report_mode = 0, # = 0,
afi_cmprs0_sa = afi_cmprs0_sa, afi_cmprs0_sa = afi_cmprs0_sa,
afi_cmprs0_len = afi_cmprs_len, afi_cmprs0_len = afi_cmprs0_len,
afi_cmprs1_sa = afi_cmprs1_sa, afi_cmprs1_sa = afi_cmprs1_sa,
afi_cmprs1_len = afi_cmprs_len, afi_cmprs1_len = afi_cmprs1_len,
afi_cmprs2_sa = afi_cmprs2_sa, afi_cmprs2_sa = afi_cmprs2_sa,
afi_cmprs2_len = afi_cmprs_len, afi_cmprs2_len = afi_cmprs2_len,
afi_cmprs3_sa = afi_cmprs3_sa, afi_cmprs3_sa = afi_cmprs3_sa,
afi_cmprs3_len = afi_cmprs_len) afi_cmprs3_len = afi_cmprs3_len)
for num_sensor in range(4): for num_sensor in range(4):
if sensor_mask & (1 << num_sensor): if sensor_mask & (1 << num_sensor):
...@@ -1469,8 +1596,8 @@ class X393SensCmprs(object): ...@@ -1469,8 +1596,8 @@ class X393SensCmprs(object):
window_left = 0, window_left = 0,
window_top = 0, window_top = 0,
last_buf_frame = 1, # - just 2-frame buffer last_buf_frame = 1, # - just 2-frame buffer
membridge_start = 0x2ba00000, membridge_start = None,
membridge_end = 0x2dd00000, membridge_end = None,
verbose = 1): verbose = 1):
""" """
Configure membridge to read/write to the sensor 0 area in the video memory Configure membridge to read/write to the sensor 0 area in the video memory
...@@ -1486,6 +1613,14 @@ class X393SensCmprs(object): ...@@ -1486,6 +1613,14 @@ class X393SensCmprs(object):
@param membridge_end system memory buffer length (bytes)= 0x2dd00000, @param membridge_end system memory buffer length (bytes)= 0x2dd00000,
@param verbose verbose level): @param verbose verbose level):
""" """
global GLBL_MEMBRIDGE_H2D_START, GLBL_MEMBRIDGE_H2D_END, GLBL_MEMBRIDGE_D2H_START, GLBL_MEMBRIDGE_D2H_END
if (membridge_start is None) or (membridge_end is None):
if write_mem:
membridge_start = GLBL_MEMBRIDGE_H2D_START
membridge_end = GLBL_MEMBRIDGE_H2D_END
else:
membridge_start = GLBL_MEMBRIDGE_D2H_START
membridge_end = GLBL_MEMBRIDGE_D2H_END
#copied from setup_sensor_channel() #copied from setup_sensor_channel()
align_to_bursts = 64 # align full width to multiple of align_to_bursts. 64 is the size of memory access align_to_bursts = 64 # align full width to multiple of align_to_bursts. 64 is the size of memory access
width_in_bursts = window_width >> 4 width_in_bursts = window_width >> 4
...@@ -1551,7 +1686,9 @@ class X393SensCmprs(object): ...@@ -1551,7 +1686,9 @@ class X393SensCmprs(object):
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_address) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_address) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, frame_full_width) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, frame_full_width)
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | (window_width >> 4)) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16)); # self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | (window_width >> 4)) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
# width should include partial bursts to matych membridge
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | num_burst_in_line) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | (window_left >> 4)) # WINDOW_X0+ (WINDOW_Y0<<16)); self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | (window_left >> 4)) # WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
...@@ -1586,7 +1723,14 @@ class X393SensCmprs(object): ...@@ -1586,7 +1723,14 @@ class X393SensCmprs(object):
if verbose >0 : if verbose >0 :
print ("Run 'membridge_start' to initiate data transfer") print ("Run 'membridge_start' to initiate data transfer")
print ("Use 'mem_dump 0x%x <length>' to view data"%(membridge_start)) print ("Use 'mem_dump 0x%x <length>' to view data"%(membridge_start))
if (write_mem):
print ("Synchronize to device after preparing data with:")
print ('sync_for_device "H2D" 0x%x 0x%x'%(membridge_start, membridge_end - membridge_start))
else:
print ("Synchronize to CPU with:")
print ('sync_for_cpu "D2H" 0x%x 0x%x'%(membridge_start, membridge_end - membridge_start))
print ("Use 'mem_save \"/usr/local/verilog/memdumpXX\" 0x%x 0x%x' to save data"%(membridge_start,(membridge_end - membridge_start))) print ("Use 'mem_save \"/usr/local/verilog/memdumpXX\" 0x%x 0x%x' to save data"%(membridge_start,(membridge_end - membridge_start)))
return {"start_addr":membridge_start,"width_padded":num_burst_in_line*16}
def print_debug( self, def print_debug( self,
first = None, first = None,
...@@ -1941,5 +2085,282 @@ class X393SensCmprs(object): ...@@ -1941,5 +2085,282 @@ class X393SensCmprs(object):
for d in data32: for d in data32:
self.x393_axi_tasks.write_control_register(reg_addr, d) self.x393_axi_tasks.write_control_register(reg_addr, d)
#copied from x393_sata
def get_mem_buf_args(self, saddr=None, leng=None):
#Is it really needed? Or use cache line size (32B), not PAGE_SIZE?
# args=""
if (saddr is None) or (leng is None):
return ""
else:
eaddr = PAGE_SIZE * ((saddr+leng) // PAGE_SIZE)
if ((saddr+leng) % PAGE_SIZE):
eaddr += PAGE_SIZE
saddr = PAGE_SIZE * (saddr // PAGE_SIZE)
return "%d %d"%(saddr, eaddr-saddr )
def _get_dma_dir_suffix(self, direction):
if direction.upper()[0] in "HT":
return "_h2d"
elif direction.upper()[0] in "DF":
return "_d2h"
elif direction.upper()[0] in "B":
return "_bidir"
def sync_for_cpu(self, direction, saddr=None, leng=None):
with open (MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, leng),file=f)
def sync_for_device(self, direction, saddr=None, leng=None):
with open (MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, leng),file=f)
"""
cd /usr/local/verilog/; test_mcntrl.py @hargs
#fpga_shutdown
setupSensorsPower "PAR12"
measure_all "*DI"
#program_status_sensor_io all 1 0
#setup_all_sensors True None 0xf
setup_simulated_mode "sensor_to_memory_1.dat"
#compressor_control all None None None None None 3
sync_for_device "D2H" 0x2d800000 0x400000
compressor_control 0 2
sync_for_cpu "D2H" 0x2d800000 0x400000
jpeg_write "img.jpeg" 0
specify_window 66 36 0 0 0 3 1
jpeg_write "img.jpeg" 1
membridge h2d_start = 0x2dc00000
membridge h2d end = 0x2e000000
membridge h2d size = 4194304 bytes
membridge h2d start = 0x2d800000
membridge h2d end = 0x2dc00000
membridge h2d size = 4194304 bytes
setup_membridge_sensor 0 False 3 66 36 0 0 0 0x2d800000 0x2dc00000 2
jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3
00000000: fe 08 3c 33 ff 00 21 5b 3f fa f8 8f ff 00 42 1f
00000010: e7 b7 d4 75 1f 66 fe db 72 ef b6 fd 9b 63 f3 77
00000020: f9 5f 04 2d 07 97 f6 8f 37 c9 dd e2 df 11 b6 df
00000030: 27 fb 5e fb ec db be f6 cf ec dd 17 7f df f2 2e
00000040: bf e3 e0 fc 6b e1 e8 a5 87 55 b0 f3 a3 92 2f 32
00000050: 68 de 3f 31 19 37 a0 98 c4 5d 37 01 b9 44 b1 bc
00000060: 65 87 02 44 74 dc 19 4e 3e e6 fd af 7c 3d af f8
00000070: ae cb f6 7e 7f 0e e9 d7 da ec 3a 1f c0 68 ef 35
00000080: 43 a7 33 5f 47 a4 da 41 e2 8d 7a e2 e2 6b b4 8f
00000090: 57 bf 5d 3e 28 e1 9e 29 e4 f3 34 ed 0c 34 52 2c
000000a0: e6 0b a4 3f 6a 3f 97 71 c6 27 0f 85 e3 3f 09 aa
000000b0: e2 ab d1 c3 52 7c 55 9d 53 f6 98 8a b0 a3 4f da
000000c0: 55 e0 1e 31 a7 4a 9f 3d 49 46 3c f5 6a 4a 34 e9
000000d0: c6 fc d3 9c a3 18 a7 26 91 f7 fe 1e 65 f8 fe 21
000000e0: cb bc 43 c2 e4 18 1c 5e 79 89 c6 70 6e 5d 80 c2
000000f0: 61 f2 7c 35 6c ce be 2b 1d 5f c5 8f 0d f2 ea 18
00000100: 2c 3d 1c 14 2b d4 af 8b ad 98 4a 38 1a 58 6a 51
00000110: 95 6a 98 c9 47 0b 08 3a ed 40 f8 5b c3 3f f2 15
00000120: b3 ff 00 af 88 ff 00 f4 21 fe 7b 7d 47 51 f6 67
"""
# Setup for compression of teh simulated data
def setup_simulated_mode(self,
data_file = None,
chn = 0,
qbank = 0,
y_quality = None,
c_quality = None, # use "same" to save None
cmode = 0, # vrlg.CMPRS_CBIT_CMODE_JPEG18,
bayer = 3, #0, as in simulator
window_width = 66,
window_height = 36,
window_left = 0,
window_top = 0,
colorsat_blue = 0x120, # 0x90 for 1x
colorsat_red = 0x16c, # 0xb6 for x1
verbose = verbose):
"""
@brief Stop sensor, configure membridge channel and write simulated data from teh text file (same as for simulation)
@param data_file - data_file - hex simulation data as used in simulation ('None' will use sensor_to_memory_%d.dat)
@param chn - compressor channel (0..3)
@param qbank - quantization table page (0..15)
@param y_quality - for JPEG header only
@param c_quality = for JPEG header only,use "same" to save None
@param cmode - color mode:
CMPRS_CBIT_CMODE_JPEG18 = 0 - color 4:2:0
CMPRS_CBIT_CMODE_MONO6 = 1 - mono 4:2:0 (6 blocks)
CMPRS_CBIT_CMODE_JP46 = 2 - jp4, 6 blocks, original
CMPRS_CBIT_CMODE_JP46DC = 3 - jp4, 6 blocks, dc -improved
CMPRS_CBIT_CMODE_JPEG20 = 4 - mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
CMPRS_CBIT_CMODE_JP4 = 5 - jp4, 4 blocks, dc-improved
CMPRS_CBIT_CMODE_JP4DC = 6 - jp4, 4 blocks, dc-improved
CMPRS_CBIT_CMODE_JP4DIFF = 7 - jp4, 4 blocks, differential
CMPRS_CBIT_CMODE_JP4DIFFHDR = 8 - jp4, 4 blocks, differential, hdr
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 9 - jp4, 4 blocks, differential, divide by 2
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 10 - jp4, 4 blocks, differential, hdr,divide by 2
CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented)
CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks
@param bayer - Bayer shift (0..3)
@param window_width - window width in pixels (bytes) (TODO: add 16-bit mode)
@param window_height - window height in lines
@param window_left - window left margin
@param window_top - window top margin
@param colorsat_blue - color saturation for blue (10 bits), 0x90 for 100%
@param colorsat_red - color saturation for red (10 bits), 0xb6 for 100%
@param verbose verbose level
"""
global GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_ENDS
global GLBL_MEMBRIDGE_H2D_START, GLBL_MEMBRIDGE_H2D_END, GLBL_MEMBRIDGE_D2H_START, GLBL_MEMBRIDGE_D2H_END
if data_file is None:
data_file = "sensor_to_memory_%d.dat"%chn
# Read data file
sensor_data = []
try:
with open(data_file) as f:
for l in f:
line = l.strip()
if line:
dl = []
for item in line.split():
dl.append(int(item,16))
sensor_data.append(dl)
num_cols = max([len(l) for l in sensor_data])
num_rows = len(sensor_data)
if verbose > 0:
print ("Read simulated sensor data of %d rows by %d columns from %s data file"%(num_rows, num_cols,data_file))
except:
print("Failed to read data from ", data_file)
return
# Above did not work, try disabling memory channel
self.x393_axi_tasks.enable_memcntrl_en_dis(8 + chn, False);
#Will restore defaulrt circbuf parameters
self.specify_phys_memory() # setup physical memory
#Overwrite CIRCBUF parameters for selected channel with D2H stream DMA buffer (shared with membridge)
GLBL_CIRCBUF_STARTS[chn] = GLBL_MEMBRIDGE_D2H_START
GLBL_CIRCBUF_ENDS[chn] = GLBL_MEMBRIDGE_D2H_END
membridge_format = self.setup_membridge_sensor(
num_sensor = chn,
write_mem = True,
window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top,
last_buf_frame = 0, # single frame
# membridge_start = GLBL_MEMBRIDGE_START,
# membridge_end = GLBL_MEMBRIDGE_END,
membridge_start = GLBL_MEMBRIDGE_H2D_START,
membridge_end = GLBL_MEMBRIDGE_H2D_END,
verbose = verbose)
#Fill membridge buffer with the data read from the file, rolling over if insufficient columns/rows
if verbose > 1:
print("membridge_format: start_addr=0x%08x, width_padded=0x%08x"%(membridge_format["start_addr"],membridge_format["width_padded"]))
self.sync_for_cpu('H2D',GLBL_MEMBRIDGE_H2D_START, GLBL_MEMBRIDGE_H2D_END - GLBL_MEMBRIDGE_H2D_START) # command and PRD table
for sline in range(window_height):
line_start = membridge_format["start_addr"] + sline * membridge_format["width_padded"]
if verbose > 1:
print("0x%08x: "%(line_start), end = "")
for scol4 in range(0,window_width,4):
data = 0
for b in range(4):
try:
data |= sensor_data[sline % num_rows][(scol4 + b) % num_cols] << (8*b)
except:
pass # should happen only for short (<num_cols) lines
if verbose > 1:
print("%08x "%(data), end = "")
self.x393_mem.write_mem(line_start + scol4,data)
if verbose > 1:
print()
# Hand buffer to FPGA
self.sync_for_device('H2D',GLBL_MEMBRIDGE_H2D_START, GLBL_MEMBRIDGE_H2D_END - GLBL_MEMBRIDGE_H2D_START) # command and PRD table
#run membridge write to video memory
self.x393Membridge.membridge_start ()
# just wait done (default timeout = 10 sec)
self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
vrlg.MEMBRIDGE_STATUS_REG, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
vrlg.MEMBRIDGE_ADDR +vrlg.MEMBRIDGE_STATUS_CNTRL, # MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
vrlg.DEFAULT_STATUS_MODE,
2 << vrlg.STATUS_2LSB_SHFT, # bit 24 - busy, bit 25 - frame done
2 << vrlg.STATUS_2LSB_SHFT, # mask for the 4-bit page number
0, # equal to
1); # synchronize sequence number
# setup compressor memory and mode
self. setup_compressor(chn = chn,
cmode = cmode,
qbank = qbank,
dc_sub = True,
multi_frame = False,
bayer = bayer,
focus_mode = 0,
coring = 0,
window_width = window_width, # 2592, # 2592
window_height = window_height, # 1944, # 1944
window_left = window_left, # 0, # 0
window_top = window_top, # 0, # 0? 1?
last_buf_frame = 0, # - just 2-frame buffer
colorsat_blue = colorsat_blue, #0x120 # 0x90 for 1x
colorsat_red = colorsat_red, #0x16c, # 0xb6 for x1
verbose = verbose)
self.specify_window (window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top,
cmode = cmode,
bayer = bayer,
# colorsat_blue = colorsat_blue, # colorsat_blue, #0x120 # 0x90 for 1x
# colorsat_red = colorsat_red, # colorsat_red, #0x16c, # 0xb6 for x1
verbose = verbose)
#Setup afi_mux for only one (this) channel, others will be disabled
afi_cmprs0_sa = GLBL_CIRCBUF_STARTS[0] // 32
afi_cmprs1_sa = GLBL_CIRCBUF_STARTS[1] // 32
afi_cmprs2_sa = GLBL_CIRCBUF_STARTS[2] // 32
afi_cmprs3_sa = GLBL_CIRCBUF_STARTS[3] // 32
afi_cmprs0_len = (GLBL_CIRCBUF_ENDS[0] - GLBL_CIRCBUF_STARTS[0]) // 32
afi_cmprs1_len = (GLBL_CIRCBUF_ENDS[1] - GLBL_CIRCBUF_STARTS[1]) // 32
afi_cmprs2_len = (GLBL_CIRCBUF_ENDS[2] - GLBL_CIRCBUF_STARTS[2]) // 32
afi_cmprs3_len = (GLBL_CIRCBUF_ENDS[3] - GLBL_CIRCBUF_STARTS[3]) // 32
self.x393CmprsAfi.afi_mux_setup (
port_afi = 0,
chn_mask = 1 << chn,
status_mode = 3, # = 3,
# mode == 0 - show EOF pointer, internal
# mode == 1 - show EOF pointer, confirmed written to the system memory
# mode == 2 - show current pointer, internal
# mode == 3 - show current pointer, confirmed written to the system memory
report_mode = 0, # = 0,
afi_cmprs0_sa = afi_cmprs0_sa,
afi_cmprs0_len = afi_cmprs0_len,
afi_cmprs1_sa = afi_cmprs1_sa,
afi_cmprs1_len = afi_cmprs1_len,
afi_cmprs2_sa = afi_cmprs2_sa,
afi_cmprs2_len = afi_cmprs2_len,
afi_cmprs3_sa = afi_cmprs3_sa,
afi_cmprs3_len = afi_cmprs3_len)
# Hand CIRCBUF to FPGA
self.sync_for_device('D2H',GLBL_CIRCBUF_STARTS[chn], GLBL_CIRCBUF_ENDS[chn] - GLBL_CIRCBUF_STARTS[chn])
# self.x393Cmprs.compressor_control(chn = chn,
# run_mode = 2) # 2: run single from memory
print ('Use the next commands')
print ('compressor_control %d 2'%(chn))
print ('sync_for_cpu "D2H" 0x%x 0x%x'%(GLBL_CIRCBUF_STARTS[chn], GLBL_CIRCBUF_ENDS[chn] - GLBL_CIRCBUF_STARTS[chn]))
print ('jpeg_write "img.jpeg" %d\n to make jpeg from simulated data'%(chn))
py393/x393_sensor.py
View file @ 82e11ec7
...@@ -70,6 +70,8 @@ class X393Sensor(object): ...@@ -70,6 +70,8 @@ class X393Sensor(object):
Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
@return "PAR12" or "HISPI" @return "PAR12" or "HISPI"
""" """
if self.DRY_MODE:
return SENSOR_INTERFACE_PARALLEL
return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI" return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def program_status_sensor_i2c( self, def program_status_sensor_i2c( self,
...@@ -502,6 +504,18 @@ class X393Sensor(object): ...@@ -502,6 +504,18 @@ class X393Sensor(object):
@param bits16) - True - 16 bpp mode, false - 8 bpp mode (bypass gamma). Gamma-processed data @param bits16) - True - 16 bpp mode, false - 8 bpp mode (bypass gamma). Gamma-processed data
is still used for histograms is still used for histograms
""" """
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_mode (num_sensor = num_sensor,
hist_en = hist_en,
hist_nrst = hist_nrst,
chn_en = chn_en,
bits16 = bits16)
return
except:
pass
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSOR_CTRL_RADDR, self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSOR_CTRL_RADDR,
self.func_sensor_mode( self.func_sensor_mode(
hist_en = hist_en, hist_en = hist_en,
......
sensor/sens_parallel12.v
View file @ 82e11ec7
...@@ -432,7 +432,8 @@ module sens_parallel12 #( ...@@ -432,7 +432,8 @@ module sens_parallel12 #(
status_generate #( status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG), .STATUS_REG_ADDR(SENSIO_STATUS_REG),
// .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS) // .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH+1) // STATUS_PAYLOAD_BITS) // .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH+1) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(26) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i ( ) status_generate_sens_io_i (
.rst (1'b0), // rst), // input .rst (1'b0), // rst), // input
.clk (mclk), // input .clk (mclk), // input
......
simulation_modules/simul_axi_hp_wr.v
View file @ 82e11ec7
...@@ -150,12 +150,14 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored ...@@ -150,12 +150,14 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
reg start_write_burst_r; // next after start_write_burst_w reg start_write_burst_r; // next after start_write_burst_w
wire write_in_progress_w; // should go inactive last confirmed upstream cycle wire write_in_progress_w; // should go inactive last confirmed upstream cycle
reg write_in_progress; reg write_in_progress;
reg [ 7:0] num_full_data = 0; // Number of full data bursts in FIFO
wire [5:0] wresp_num_in_fifo; wire [5:0] wresp_num_in_fifo;
reg was_wresp_re=0; reg was_wresp_re=0;
wire wresp_re; wire wresp_re;
reg [ 7:0] num_full_data = 0; // Number of full data bursts in FIFO
wire inc_num_full_data = wvalid && wready && wlast;
// documentation sais : "When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher // documentation sais : "When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher
// priority transactions are backed up behind it." Whqt about demotion? Assuming it is not demoted // priority transactions are backed up behind it." Whqt about demotion? Assuming it is not demoted
assign sim_wr_qos = (wrQosHeadOfCmdQEn && (wr_qos_in > wr_qos_out))? wr_qos_in : wr_qos_out; assign sim_wr_qos = (wrQosHeadOfCmdQEn && (wr_qos_in > wr_qos_out))? wr_qos_in : wr_qos_out;
...@@ -218,8 +220,8 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored ...@@ -218,8 +220,8 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
// Count full data bursts ready in FIFO // Count full data bursts ready in FIFO
always @ (posedge rst or posedge aclk) begin always @ (posedge rst or posedge aclk) begin
if (rst) num_full_data <=0; if (rst) num_full_data <=0;
else if (wvalid && wready && wlast && !start_write_burst_w) num_full_data <= num_full_data + 1; else if ( inc_num_full_data && !start_write_burst_w) num_full_data <= num_full_data + 1;
else if (!(wvalid && wready && wlast) && start_write_burst_w) num_full_data <= num_full_data - 1; else if (!inc_num_full_data && start_write_burst_w) num_full_data <= num_full_data - 1;
end end
......
util_modules/frame_num_sync.v 0 → 100644
View file @ 82e11ec7
/*******************************************************************************
* Module: frame_num_sync
* Date:2016-04-28
* Author: andrey
* Description: Propagating frame number from acquisition to compressor output
*
* Copyright (c) 2016 Elphel, Inc .
* frame_num_sync.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* frame_num_sync.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module frame_num_sync #(
parameter NUM_FRAME_BITS = 4,
parameter LAST_FRAME_BITS = 16,
parameter FRAME_BITS_KEEP = 4 // number of bits from mcntrl frame number used to index absolute sensor frame number
)(
input mrst,
input mclk, // for command/status
input [NUM_FRAME_BITS*4-1:0] absolute_frames, // per-channel current sensor frame number
input [3:0] first_wr_in_frame, // sensor writes first block in a frame
// input [3:0] first_rd_in_frame, // compressor gets first block in a frame
input [4*LAST_FRAME_BITS-1:0] memory_frames_sensor, // 4 channels of frame numbers as defined for memory allocation
input [4*LAST_FRAME_BITS-1:0] memory_frames_compressor, // 4 channels of frame numbers as defined for memory allocation, valid after compression (before done)
output reg [NUM_FRAME_BITS*4-1:0] compressed_frames // frame numbers valid at compressor done (TODO: keep until IRQ cleared? pointers will change anyway)
);
reg [NUM_FRAME_BITS-1:0] frames_ram0[0: (1<<FRAME_BITS_KEEP) -1];
reg [NUM_FRAME_BITS-1:0] frames_ram1[0: (1<<FRAME_BITS_KEEP) -1];
reg [NUM_FRAME_BITS-1:0] frames_ram2[0: (1<<FRAME_BITS_KEEP) -1];
reg [NUM_FRAME_BITS-1:0] frames_ram3[0: (1<<FRAME_BITS_KEEP) -1];
always @ (posedge mclk) begin
if (first_wr_in_frame[0]) frames_ram0[memory_frames_sensor[0*LAST_FRAME_BITS+:FRAME_BITS_KEEP]] <= absolute_frames[0*NUM_FRAME_BITS +: NUM_FRAME_BITS];
if (first_wr_in_frame[1]) frames_ram1[memory_frames_sensor[1*LAST_FRAME_BITS+:FRAME_BITS_KEEP]] <= absolute_frames[1*NUM_FRAME_BITS +: NUM_FRAME_BITS];
if (first_wr_in_frame[2]) frames_ram2[memory_frames_sensor[2*LAST_FRAME_BITS+:FRAME_BITS_KEEP]] <= absolute_frames[2*NUM_FRAME_BITS +: NUM_FRAME_BITS];
if (first_wr_in_frame[3]) frames_ram3[memory_frames_sensor[3*LAST_FRAME_BITS+:FRAME_BITS_KEEP]] <= absolute_frames[3*NUM_FRAME_BITS +: NUM_FRAME_BITS];
compressed_frames[0*NUM_FRAME_BITS +: NUM_FRAME_BITS] <= frames_ram0[memory_frames_compressor[0*LAST_FRAME_BITS+:FRAME_BITS_KEEP]];
compressed_frames[1*NUM_FRAME_BITS +: NUM_FRAME_BITS] <= frames_ram1[memory_frames_compressor[1*LAST_FRAME_BITS+:FRAME_BITS_KEEP]];
compressed_frames[2*NUM_FRAME_BITS +: NUM_FRAME_BITS] <= frames_ram2[memory_frames_compressor[2*LAST_FRAME_BITS+:FRAME_BITS_KEEP]];
compressed_frames[3*NUM_FRAME_BITS +: NUM_FRAME_BITS] <= frames_ram3[memory_frames_compressor[3*LAST_FRAME_BITS+:FRAME_BITS_KEEP]];
end
endmodule
// wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src;// input[15:0] current frame number (for multi-frame ranges) in the source (sensor) channel
x393.v
View file @ 82e11ec7
...@@ -482,6 +482,8 @@ module x393 #( ...@@ -482,6 +482,8 @@ module x393 #(
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
// TODO: Add counter(s) to count sens_xfer_skipped pulses // TODO: Add counter(s) to count sens_xfer_skipped pulses
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
wire [3:0] sens_first_wr_in_frame; // single mclk pulse on first write block in each frame
wire trigger_mode; // (), // input wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0] wire [3:0] trig_in; // input[3:0]
...@@ -494,7 +496,7 @@ module x393 #( ...@@ -494,7 +496,7 @@ module x393 #(
wire [3:0] sof_late_mclk; // (), // output[3:0] wire [3:0] sof_late_mclk; // (), // output[3:0]
wire [4 * NUM_FRAME_BITS - 1:0] frame_num; // (), // input[15:0] wire [4 * NUM_FRAME_BITS - 1:0] frame_num; // (), // input[15:0]
wire [4 * NUM_FRAME_BITS - 1:0] frame_num_compressed; // (), // input[15:0]
// signals for compressor393 (in/outs as seen for the sensor393) // signals for compressor393 (in/outs as seen for the sensor393)
// per-channel memory buffers interface // per-channel memory buffers interface
...@@ -520,6 +522,8 @@ module x393 #( ...@@ -520,6 +522,8 @@ module x393 #(
wire [3:0] cmprs_frame_done_dst; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory wire [3:0] cmprs_frame_done_dst; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353 // use as 'eot_real' in 353
wire [3:0] cmprs_suspend; // output suspend reading data for this channel - waiting for the source data wire [3:0] cmprs_suspend; // output suspend reading data for this channel - waiting for the source data
wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_finished; // frame numbers compressed
// Timestamp messages (@mclk) - combine to a single ts_data? // Timestamp messages (@mclk) - combine to a single ts_data?
wire [3:0] ts_pre_stb; // input[ 3:0] 4 compressor channels wire [3:0] ts_pre_stb; // input[ 3:0] 4 compressor channels
...@@ -929,6 +933,22 @@ assign axi_grst = axi_rst_pre; ...@@ -929,6 +933,22 @@ assign axi_grst = axi_rst_pre;
end end
endgenerate endgenerate
frame_num_sync #(
.NUM_FRAME_BITS(NUM_FRAME_BITS),
.LAST_FRAME_BITS(LAST_FRAME_BITS),
.FRAME_BITS_KEEP(NUM_FRAME_BITS)
) frame_num_sync_i (
.mrst (mrst), // input
.mclk (mclk), // input
.absolute_frames (frame_num), // input[15:0]
.first_wr_in_frame (sens_first_wr_in_frame), // input[3:0]
// .first_rd_in_frame (), // input[3:0]
.memory_frames_sensor (cmprs_frame_number_src), // input[63:0]
.memory_frames_compressor (cmprs_frame_number_finished), // input[63:0]
.compressed_frames (frame_num_compressed) // output[15:0]
);
cmd_seq_mux #( cmd_seq_mux #(
.CMDSEQMUX_ADDR (CMDSEQMUX_ADDR), .CMDSEQMUX_ADDR (CMDSEQMUX_ADDR),
.CMDSEQMUX_MASK (CMDSEQMUX_MASK), .CMDSEQMUX_MASK (CMDSEQMUX_MASK),
...@@ -1298,6 +1318,8 @@ assign axi_grst = axi_rst_pre; ...@@ -1298,6 +1318,8 @@ assign axi_grst = axi_rst_pre;
.sens_buf_dout (sens_buf_dout), // input[255:0] .sens_buf_dout (sens_buf_dout), // input[255:0]
.sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer .sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer
.sens_xfer_skipped (sens_xfer_skipped), // output reg .sens_xfer_skipped (sens_xfer_skipped), // output reg
.sens_first_wr_in_frame (sens_first_wr_in_frame), // single mclk pulse on first write block in each frame
// compressor interface // compressor interface
.cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0] .cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0]
.cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0] .cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0]
...@@ -1996,7 +2018,9 @@ assign axi_grst = axi_rst_pre; ...@@ -1996,7 +2018,9 @@ assign axi_grst = axi_rst_pre;
.CMPRS_AFIMUX_SA_LEN (CMPRS_AFIMUX_SA_LEN), .CMPRS_AFIMUX_SA_LEN (CMPRS_AFIMUX_SA_LEN),
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH), .CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS), .CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY) .AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY) ,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif `endif
...@@ -2034,13 +2058,15 @@ assign axi_grst = axi_rst_pre; ...@@ -2034,13 +2058,15 @@ assign axi_grst = axi_rst_pre;
.frame_done_dst (cmprs_frame_done_dst), // input[3:0] .frame_done_dst (cmprs_frame_done_dst), // input[3:0]
.suspend (cmprs_suspend), // output[3:0] .suspend (cmprs_suspend), // output[3:0]
.frame_number_finished (cmprs_frame_number_finished),// output[63:0] frame numbers compressed
.ts_pre_stb (ts_pre_stb), // input[3:0] .ts_pre_stb (ts_pre_stb), // input[3:0]
.ts_data (ts_data), // input[31:0] .ts_data (ts_data), // input[31:0]
.eof_written_mclk (eof_written_mclk), // output[3:0] .eof_written_mclk (eof_written_mclk), // output[3:0]
.stuffer_done_mclk (stuffer_done_mclk), // output[3:0] .stuffer_done_mclk (stuffer_done_mclk), // output[3:0]
.vsync_late (sof_late_mclk), // input[3:0] .vsync_late (sof_late_mclk), // input[3:0]
.frame_num_compressed (frame_num_compressed[4 * NUM_FRAME_BITS -1 : 0]), // input[3:0]
.hclk (hclk), // input .hclk (hclk), // input
.afi0_awaddr (afi1_awaddr), // output[31:0] .afi0_awaddr (afi1_awaddr), // output[31:0]
......
x393_testbench03.sav
View file @ 82e11ec7
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Nov 18 00:58:20 2015 [*] Sat Apr 30 19:42:21 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151115142219571.fst" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160429201645793.fst"
[dumpfile_mtime] "Sun Nov 15 22:02:48 2015" [dumpfile_mtime] "Sat Apr 30 02:59:43 2016"
[dumpfile_size] 287600988 [dumpfile_size] 259025431
[savefile] "/home/andrey/git/x393/x393_testbench03.sav" [savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0 [timestart] 0
[size] 1823 1180 [size] 1823 1180
[pos] 0 0 [pos] 1917 0
*-25.097748 69667459 107947388 109212388 108561548 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-25.657038 71773130 107947388 109212388 101070300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03. [treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[1].
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[2].
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[3].
[treeopen] x393_testbench03.simul_sensor12bits_2_i. [treeopen] x393_testbench03.simul_sensor12bits_2_i.
[treeopen] x393_testbench03.x393_i. [treeopen] x393_testbench03.x393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i. [treeopen] x393_testbench03.x393_i.compressor393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0]. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2]. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_macroblock_buf_iface_i.
...@@ -36,15 +32,16 @@ ...@@ -36,15 +32,16 @@
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.csconvert_i.i_csconvert_jp4.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i. [treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_testbench03.x393_i.frame_sequencer_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i. [treeopen] x393_testbench03.x393_i.mcntrl393_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i. [treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i. [treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0]. [treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i. [treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i. [treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i. [treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_testbench03.x393_i.sensors393_i. [treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0]. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
...@@ -52,33 +49,21 @@ ...@@ -52,33 +49,21 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 340 [sst_width] 402
[signals_width] 321 [signals_width] 428
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 514 [sst_vpaned_height] 518
@820 @820
x393_testbench03.TEST_TITLE[639:0] x393_testbench03.TEST_TITLE[639:0]
@800200 @800200
...@@ -92,296 +77,82 @@ x393_testbench03.x393_i.pclk ...@@ -92,296 +77,82 @@ x393_testbench03.x393_i.pclk
-x393_top -x393_top
@c00200 @c00200
-sens_10398 -sens_10398
@28 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pclk -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_ext_clk_p
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.rst_mmcm
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@1001200 @1001200
-group_end -group_end
@200 @200
- -
@800200 @800200
-sens_hispi12l4 -sens_hispi12l4
@28 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk2x
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.irst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.prst
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.irst_r[4:0]
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0]
@1401200 @1401200
-group_end -group_end
@c00022 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0]
@1401200 @1401200
-group_end -group_end
@22 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
@1401200 @1401200
-group_end -group_end
@28 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_out -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp
@c00022 @1401200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0] -group_end
@28 @c00200
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
@1401200 @1401200
-group_end -group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dn[3:0]
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(10)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(11)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(12)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(13)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(14)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(15)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_clkp
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_aligned[47:0]
@200 @200
-lanes -lanes
@c00022 @c00200
[color] 3 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@1401200 @1401200
-group_end -group_end
@22 @c00200
[color] 2 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
[color] 3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout[11:0]
[color] 3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dv
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.din[3:0]
@1401200 @1401200
-group_end -group_end
@22 @c00200
[color] 2 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.shift_val[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.dout[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[1].sens_hispi_lane_i.dv
@c00022
[color] 3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din[3:0]
@1401200 @1401200
-group_end -group_end
@22 @c00200
[color] 2 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.shift_val[1:0]
[color] 3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.dout[11:0]
[color] 3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.dv
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.din[3:0]
@1401200 @1401200
-group_end -group_end
@22
[color] 2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.shift_val[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.dout[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_lane_i.dv
@200 @200
- -
@c00022 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sof[3:0]
@1401200 @1401200
-group_end -group_end
@22 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eof[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_sol[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_eol[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ignore_embedded
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_embed[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out_pre[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk_strt[1:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sof_pclk
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@1001200 @1001200
-group_end -group_end
@28 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_pclk -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.good_lanes[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_on
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@1001200 @1001200
-group_end -group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_off
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.eof
@200 @200
-hact_off -hact_off
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_hact_off_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_hact_off_i.dout
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_hact_off_i.dly[3:0]
@200
-hact_on -hact_on
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_hact_on_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_hact_on_i.dout
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_hact_on_i.dly[3:0]
@200
-pxd -pxd
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_pxd_out_i.din[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_pxd_out_i.dout[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.dly_16_pxd_out_i.dly[3:0]
@800200 @800200
-sens_hispi_fifo -sens_hispi_fifo
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.eol
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.din[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.we
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.wa[4:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_start_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.re
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.ra[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.dout[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.run
@1000200 @1000200
-sens_hispi_fifo -sens_hispi_fifo
@800200 @800200
-sens_hispi_fifo_3 -sens_hispi_fifo_3
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.eol
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.din[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.we
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.wa[4:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.line_run_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.line_start_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.line_run_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.re
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.ra[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.dout[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.run
@1000200 @1000200
-sens_hispi_fifo_3 -sens_hispi_fifo_3
@200 @200
- -
@c00200 @c00200
-sens_hispi_clock -sens_hispi_clock
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i.clk_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i.ipclk_pre
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i.ipclk2x_pre
@200 @200
- -
@1401200 @1401200
...@@ -390,272 +161,64 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -390,272 +161,64 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-sens_hispi_din -sens_hispi_din
@200 @200
- -
@800022 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din[3:0]
@1001200 @1001200
-group_end -group_end
@22 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_dly[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_p
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_n[3:0]
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_p[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_p[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_p[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_p[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_p[3:0]
@1401200 @1401200
-group_end -group_end
@c00022 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(10)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(11)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(12)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(13)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(14)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(15)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(16)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(17)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(18)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(19)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(20)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(21)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(22)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(23)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(24)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(25)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(26)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(27)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(28)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(29)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(30)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
(31)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dly_data[31:0]
@1401200 @1401200
-group_end -group_end
@c00022 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(10)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(11)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(12)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(13)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(14)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
(15)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.dout[15:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.ipclk2x
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.irst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.ld_idelay
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.mrst
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.set_idelay[3:0]
@1401200 @1401200
-group_end
-sens_hispi_din -sens_hispi_din
@800200 @800200
-sens_hispi_lane0_sel -sens_hispi_lane0_sel
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.ipclk2x
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].ibufds_ibufgds0_i.O
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].pxd_dly_i.data_in
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].pxd_dly_i.data_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].iserdes_pxd_i.iclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].iserdes_pxd_i.oclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].iserdes_pxd_i.oclk_div
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].iserdes_pxd_i.ddly
@200 @200
- -
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.ipclk
@800200 @800200
-lane_0 -lane_0
@c00022 @c00200
[color] 3 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@1401200 @1401200
-group_end -group_end
@22 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.d_r[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_lead_0_w[2:0]
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w[2:0]
@1401200 @1401200
-group_end -group_end
@22 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_lead_1_w[2:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_1_w[2:0]
@28
[color] 2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.zero_after_ones_w
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_running_ones[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.prev4ones
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_running_zeros_w[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_running_zeros[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_first_zeros[1:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sync_w
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.barrel[3:0]
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
@1401200 @1401200
-group_end -group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eof
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dv
@1000200 @1000200
-lane_0 -lane_0
@800200 @800200
-lane_2 -lane_2
@200 @200
-lane_2 -lane_2
@22 @800200
[color] 3 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.din[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.d_r[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_lead_0_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_trail_0_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_lead_1_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_trail_1_w[2:0]
[color] 2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.zero_after_ones_w
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_ones[3:0]
@1001200 @1001200
-group_end -group_end
@28 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.prev4ones -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_zeros_w[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_running_zeros[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.num_first_zeros[1:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.got_sync_w
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.shift_val[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.barrel[3:0]
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sync_decode[3:0]
@1401200 @1401200
-group_end -group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.eol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.dout[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].sens_hispi_lane_i.dv
@1000200 @1000200
-lane_2 -lane_2
-sens_hispi_lane0_sel -sens_hispi_lane0_sel
@800200 @800200
-sens_hispi_lane0 -sens_hispi_lane0
@22 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.barrel[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.d_r[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout_w[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.embed
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_embed
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sync
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sync_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.irst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_first_zeros[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_lead_0_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_lead_1_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_running_ones[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_running_zeros[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_running_zeros_w[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_0_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.num_trail_1_w[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.pre_dv[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.prev4ones
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.start_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.start_line_d
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
@1401200 @1401200
-group_end -group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.zero_after_ones_w
@1000200 @1000200
-sens_hispi_lane0 -sens_hispi_lane0
-sens_hispi12l4 -sens_hispi12l4
...@@ -752,6 +315,26 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hi ...@@ -752,6 +315,26 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@200 @200
-hist_debug -hist_debug
@c00022
x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sof_out_pclk[3:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
(1)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
(2)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
(3)x393_testbench03.x393_i.sensors393_i.px_valid[3:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.eof_out_pclk[3:0]
@800200 @800200
-channels_1_3 -channels_1_3
@28 @28
...@@ -760,26 +343,6 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.ge ...@@ -760,26 +343,6 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.ge
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@1000200 @1000200
-channels_1_3 -channels_1_3
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.prst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.irst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_ipclk
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk_strt[1:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk_strt[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk_strt[1:0]
@1001200
-group_end
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk[1:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.vact_pclk[1:0]
@1001200
-group_end
@800200 @800200
-sens_sync_chn0 -sens_sync_chn0
@28 @28
...@@ -1003,27 +566,15 @@ x393_testbench03.PX1_MCLK ...@@ -1003,27 +566,15 @@ x393_testbench03.PX1_MCLK
x393_testbench03.PX1_DCLK x393_testbench03.PX1_DCLK
x393_testbench03.PX1_ARO x393_testbench03.PX1_ARO
x393_testbench03.PX1_ARST x393_testbench03.PX1_ARST
x393_testbench03.PX1_CLK_N
x393_testbench03.PX1_CLK_P
@22 @22
x393_testbench03.PX1_D[11:0] x393_testbench03.PX1_D[11:0]
@28 @28
x393_testbench03.PX1_FLASH x393_testbench03.PX1_FLASH
@22
x393_testbench03.PX1_GP[3:0]
@28
x393_testbench03.PX1_HACT x393_testbench03.PX1_HACT
@c00022 @c00200
x393_testbench03.PX1_LANE_N[3:0] -x393_testbench03.PX1_LANE_N
@28
(0)x393_testbench03.PX1_LANE_N[3:0]
(1)x393_testbench03.PX1_LANE_N[3:0]
(2)x393_testbench03.PX1_LANE_N[3:0]
(3)x393_testbench03.PX1_LANE_N[3:0]
@1401200 @1401200
-group_end -group_end
@22
x393_testbench03.PX1_LANE_P[3:0]
@28 @28
x393_testbench03.PX1_MRST x393_testbench03.PX1_MRST
x393_testbench03.PX1_OFST x393_testbench03.PX1_OFST
...@@ -1055,202 +606,52 @@ x393_testbench03.simul_sensor12bits_i.cntrd[15:0] ...@@ -1055,202 +606,52 @@ x393_testbench03.simul_sensor12bits_i.cntrd[15:0]
-SENSOR0 -SENSOR0
@c00200 @c00200
-par_hispi_sel -par_hispi_sel
@28
x393_testbench03.par12_hispi_psp4l0_i.pclk
x393_testbench03.par12_hispi_psp4l0_i.oclk
x393_testbench03.par12_hispi_psp4l0_i.hact
x393_testbench03.par12_hispi_psp4l0_i.hact_d
@22
x393_testbench03.par12_hispi_psp4l0_i.pxd[11:0]
x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.next_line_pclk
x393_testbench03.par12_hispi_psp4l0_i.next_frame_pclk
@22
x393_testbench03.par12_hispi_psp4l0_i.fifo_di[48:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_w
x393_testbench03.par12_hispi_psp4l0_i.fifo_we
@22
x393_testbench03.par12_hispi_psp4l0_i.fifo_wa[11:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.oclk
@22
x393_testbench03.par12_hispi_psp4l0_i.fifo_ra[11:0]
x393_testbench03.par12_hispi_psp4l0_i.fifo_out[48:0]
x393_testbench03.par12_hispi_psp4l0_i.lines_available[1:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.next_line_oclk
x393_testbench03.par12_hispi_psp4l0_i.sof_sol_sent
x393_testbench03.par12_hispi_psp4l0_i.next_sof
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_data_w
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_sof_sol_w
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_eof_w
@22
x393_testbench03.par12_hispi_psp4l0_i.lines_left
@c00200
-par12_hspi_lane0_sel -par12_hspi_lane0_sel
@22
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.din[12:0]
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.din_filt[11:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.dav
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].par12_hispi_psp4l_lane_i.dav_rdy
@200 @200
-other_lanes -other_lanes
@22
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[1].par12_hispi_psp4l_lane_i.din_filt[11:0]
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[2].par12_hispi_psp4l_lane_i.din_filt[11:0]
x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[3].par12_hispi_psp4l_lane_i.din_filt[11:0]
@1401200 @1401200
-par12_hspi_lane0_sel -par12_hspi_lane0_sel
@c00200 @c00200
-clk_mult_div -clk_mult_div
@28
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_in
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_int
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_out
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.en
@1401200 @1401200
-clk_mult_div -clk_mult_div
-par_hispi_sel -par_hispi_sel
@c00200 @c00200
-sens_hispi_12l4 -sens_hispi_12l4
-lane0 -lane0
@28 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk2x
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_dp[3:0]
@1001200 @1001200
-group_end -group_end
@28 @c00200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_clkp -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(10)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(11)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(12)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(13)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(14)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
(15)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sns_d[15:0]
@1401200 @1401200
-group_end -group_end
@800022 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.din[3:0]
@1001200 @1001200
-group_end -group_end
@22 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dout[11:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sol
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.eol
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.sync_decode[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.got_sync
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.barrel[3:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
@1001200 @1001200
-group_end -group_end
@1401200 @1401200
-lane0 -lane0
@800200 @800200
-fifo0 -fifo0
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.out_dly[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.we
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.wa[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.din[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.start_out_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.start_sent
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk_d
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.re
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.run
@200 @200
- -
@1000200 @1000200
-fifo0 -fifo0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.set_lanes_map
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.set_fifo_dly
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.lanes_map[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_out_dly_mclk[3:0]
@200 @200
-other -other
@28 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pclk -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_all_dly
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@1001200 @1001200
-group_end -group_end
@22 @800200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.good_lanes[3:0] -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re
@28 -x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_pclk
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out_pre[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_out
@1001200 @1001200
-group_end -group_end
-group_end -group_end
...@@ -1260,113 +661,9 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -1260,113 +661,9 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-sens_hispi_12l4 -sens_hispi_12l4
@c00200 @c00200
-par_hspi_0 -par_hspi_0
@28 -x393_testbench03.par12_hispi_psp4l0_i.pxd_d
x393_testbench03.par12_hispi_psp4l0_i.clk_n
x393_testbench03.par12_hispi_psp4l0_i.clk_p
x393_testbench03.par12_hispi_psp4l0_i.clk_pn
x393_testbench03.par12_hispi_psp4l0_i.clk_pn_dly
x393_testbench03.par12_hispi_psp4l0_i.eof_sent
x393_testbench03.par12_hispi_psp4l0_i.fifo_dav
@22
x393_testbench03.par12_hispi_psp4l0_i.fifo_di[48:0]
x393_testbench03.par12_hispi_psp4l0_i.fifo_out[48:0]
x393_testbench03.par12_hispi_psp4l0_i.fifo_ra[11:0]
x393_testbench03.par12_hispi_psp4l0_i.fifo_wa[11:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.fifo_we
x393_testbench03.par12_hispi_psp4l0_i.frames_open[1:0]
x393_testbench03.par12_hispi_psp4l0_i.hact
x393_testbench03.par12_hispi_psp4l0_i.hact_d
x393_testbench03.par12_hispi_psp4l0_i.hact_in
x393_testbench03.par12_hispi_psp4l0_i.image_lines
@22
x393_testbench03.par12_hispi_psp4l0_i.lane_n[3:0]
x393_testbench03.par12_hispi_psp4l0_i.lane_p[3:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.lane_pcntr[1:0]
x393_testbench03.par12_hispi_psp4l0_i.line_available
x393_testbench03.par12_hispi_psp4l0_i.lines_available[1:0]
x393_testbench03.par12_hispi_psp4l0_i.next_frame_oclk
x393_testbench03.par12_hispi_psp4l0_i.next_frame_pclk
x393_testbench03.par12_hispi_psp4l0_i.next_line_oclk
x393_testbench03.par12_hispi_psp4l0_i.next_line_pclk
x393_testbench03.par12_hispi_psp4l0_i.next_sof
x393_testbench03.par12_hispi_psp4l0_i.oclk
x393_testbench03.par12_hispi_psp4l0_i.orst
x393_testbench03.par12_hispi_psp4l0_i.orst_r
x393_testbench03.par12_hispi_psp4l0_i.pclk
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_data_w
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_eof_w
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_sof_sol_w
x393_testbench03.par12_hispi_psp4l0_i.pre_fifo_we_w
@22
x393_testbench03.par12_hispi_psp4l0_i.pre_lines
x393_testbench03.par12_hispi_psp4l0_i.pxd[11:0]
@c00022
x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
@28
(0)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(1)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(2)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(3)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(4)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(5)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(6)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(7)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(8)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(9)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(10)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(11)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(12)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(13)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(14)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(15)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(16)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(17)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(18)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(19)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(20)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(21)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(22)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(23)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(24)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(25)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(26)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(27)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(28)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(29)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(30)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(31)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(32)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(33)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(34)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(35)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(36)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(37)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(38)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(39)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(40)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(41)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(42)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(43)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(44)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(45)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(46)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
(47)x393_testbench03.par12_hispi_psp4l0_i.pxd_d[47:0]
@1401200
-group_end
@22
x393_testbench03.par12_hispi_psp4l0_i.rdy[3:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.rst
@22
x393_testbench03.par12_hispi_psp4l0_i.sdata[3:0]
x393_testbench03.par12_hispi_psp4l0_i.sdata_dly[3:0]
@28
x393_testbench03.par12_hispi_psp4l0_i.sof_sol_sent
x393_testbench03.par12_hispi_psp4l0_i.vact
x393_testbench03.par12_hispi_psp4l0_i.vact_d
@1401200 @1401200
-group_end
-par_hspi_0 -par_hspi_0
@c00200 @c00200
-scheduler16 -scheduler16
...@@ -2719,9 +2016,212 @@ x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rst0 ...@@ -2719,9 +2016,212 @@ x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rst0
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0 x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0
@200 @200
- -
@29 @28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written0 x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written0
@800200
-frame_seq0
@28
x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_sync
@22
x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_no[3:0]
@1000200
-frame_seq0
@800200
-i2c_seq_0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_sync
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_num[3:0]
@1000200
-i2c_seq_0
@c00200
-compressor0_frame
@22
x393_testbench03.compressor_run.num_sensor[1:0]
x393_testbench03.compressor_run.run_mode[31:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_src[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_dst[15:0]
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_go
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_start_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.frame_start_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.frame_start_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.frame_start_dst
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_started
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.frame_started
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_frame_sync_i.frame_started
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.frame_started
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.vsync_late
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.vsync_late
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_frame_sync_i.vsync_late
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.vsync_late
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done_mclk
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.reading_frame
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.reading_frame
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.reading_frame
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.reading_frame
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written_mclk
@22
x393_testbench03.x393_i.compressor393_i.cmprs_irq[3:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.vsync_late
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.broken_frame
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_done
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_dst[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_src[15:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_started_mclk
@800200
-memcntrl
@200
-
@800022
x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_dst[3:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_dst[3:0]
(1)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_dst[3:0]
(2)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_dst[3:0]
(3)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_dst[3:0]
@1001200
-group_end
@800022
x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_src[3:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_src[3:0]
(1)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_src[3:0]
(2)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_src[3:0]
(3)x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_done_src[3:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_number_dst[63:0]
x393_testbench03.x393_i.mcntrl393_i.cmprs_frame_number_src[63:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_number_cntr[15:0]
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_number_current[15:0]
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_channel_pgm_en[3:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_channel_pgm_en[3:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_channel_pgm_en[3:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_channel_pgm_en[3:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_channel_pgm_en[3:0]
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_in_frame[3:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_in_frame[3:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_in_frame[3:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_in_frame[3:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_in_frame[3:0]
@1001200
-group_end
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_pending_r[3:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_pending_r[3:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_pending_r[3:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_pending_r[3:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_first_wr_pending_r[3:0]
@1001200
-group_end
-group_end
@800022
x393_testbench03.x393_i.mcntrl393_i.sens_start_wr[3:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_start_wr[3:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_start_wr[3:0]
(2)x393_testbench03.x393_i.mcntrl393_i.sens_start_wr[3:0]
(3)x393_testbench03.x393_i.mcntrl393_i.sens_start_wr[3:0]
@1001200
-group_end
@1000200
-memcntrl
@1401200
-compressor0_frame
@200
-
@28
x393_testbench03.x393_i.mcntrl393_i.mclk
@c00201
-frame_num_sync
@c00022
x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
@28
(0)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(1)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(2)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(3)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(4)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(5)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(6)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(7)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(8)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(9)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(10)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(11)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(12)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(13)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(14)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
(15)x393_testbench03.x393_i.frame_num_sync_i.absolute_frames[15:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
@28
(0)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(1)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(2)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(3)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(4)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(5)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(6)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(7)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(8)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(9)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(10)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(11)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(12)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(13)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(14)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
(15)x393_testbench03.x393_i.frame_num_sync_i.compressed_frames[15:0]
@1401200
-group_end
@800022
x393_testbench03.x393_i.frame_num_sync_i.first_wr_in_frame[3:0]
@28
(0)x393_testbench03.x393_i.frame_num_sync_i.first_wr_in_frame[3:0]
(1)x393_testbench03.x393_i.frame_num_sync_i.first_wr_in_frame[3:0]
(2)x393_testbench03.x393_i.frame_num_sync_i.first_wr_in_frame[3:0]
(3)x393_testbench03.x393_i.frame_num_sync_i.first_wr_in_frame[3:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.frame_num_sync_i.memory_frames_compressor[63:0]
x393_testbench03.x393_i.frame_num_sync_i.memory_frames_sensor[63:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_finished[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.frame_number_finished[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.frame_number_finished[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.frame_number_finished[15:0]
@1401201
-frame_num_sync
@200 @200
- -
@800200
-quantizer0
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.block_mem_o[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.tdo[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.quantizer393_i.tdo[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.quantizer393_i.tdo[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.quantizer393_i.tdo[15:0]
@1000200
-quantizer0
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
x393_testbench03.tf
View file @ 82e11ec7
...@@ -34,13 +34,17 @@ ...@@ -34,13 +34,17 @@
`timescale 1ns/1ps `timescale 1ns/1ps
`include "system_defines.vh" `include "system_defines.vh"
`define SAME_SENSOR_DATA 1 `define SAME_SENSOR_DATA 1
//`undef SAME_SENSOR_DATA
`define COMPRESS_SINGLE `define COMPRESS_SINGLE
//`define use200Mhz 1 //`define use200Mhz 1
//`define DEBUG_FIFO 1 //`define DEBUG_FIFO 1
`undef WAIT_MRS `undef WAIT_MRS
`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays) `define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
`define READBACK_DELAYS 1 `define READBACK_DELAYS 1
//`define TEST_MEMBRIDGE 1
//`define TEST_MEMBRIDGE 1 // was not set
`undef TEST_MEMBRIDGE // was not set
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one `define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation // Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1 //`define TEST_WRITE_LEVELLING 1
...@@ -58,8 +62,8 @@ ...@@ -58,8 +62,8 @@
//`define TEST_TILED_WRITE32 1 //`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1 //`define TEST_TILED_READ32 1
`define TEST_AFI_WRITE 1 //`define TEST_AFI_WRITE 1
`define TEST_AFI_READ 1 //`define TEST_AFI_READ 1
`define TEST_SENSOR 0 `define TEST_SENSOR 0
...@@ -132,9 +136,10 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -132,9 +136,10 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
parameter BLANK_ROWS_AFTER= 1; //8; parameter BLANK_ROWS_AFTER= 1; //8;
`else `else
parameter HBLANK= 12; // 52; // 12; /// 52; //********************* // parameter HBLANK= 12; // 52; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 1; //8; ///2+2 - a little faster than compressor parameter HBLANK= 52; // 12; // 52; // 12; /// 52; //*********************
parameter BLANK_ROWS_AFTER= 1; //8; parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 8; // 1; //8;
`endif `endif
parameter WOI_HEIGHT= 32; parameter WOI_HEIGHT= 32;
parameter TRIG_LINES= 8; parameter TRIG_LINES= 8;
...@@ -617,6 +622,7 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -617,6 +622,7 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire CLK; wire CLK;
reg RST; reg RST;
reg RST_CLEAN = 1;
reg AR_SET_CMD_r; reg AR_SET_CMD_r;
wire AR_READY; wire AR_READY;
...@@ -738,6 +744,7 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -738,6 +744,7 @@ assign #10 gpio_pins[9] = gpio_pins[8];
// SuppressWarnings VEditor : assigned in $readmem() system task // SuppressWarnings VEditor : assigned in $readmem() system task
$dumpvars(0,x393_testbench03); $dumpvars(0,x393_testbench03);
// CLK =1'b0; // CLK =1'b0;
RST_CLEAN = 1;
RST = 1'bx; RST = 1'bx;
AR_SET_CMD_r = 1'b0; AR_SET_CMD_r = 1'b0;
AW_SET_CMD_r = 1'b0; AW_SET_CMD_r = 1'b0;
...@@ -751,6 +758,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -751,6 +758,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
#9000; // same as glbl #9000; // same as glbl
repeat (20) @(posedge CLK) ; repeat (20) @(posedge CLK) ;
RST =1'b0; RST =1'b0;
@(posedge CLK) ;
RST_CLEAN = 0;
while (x393_i.mrst) @(posedge CLK) ; while (x393_i.mrst) @(posedge CLK) ;
// repeat (4) @(posedge CLK) ; // repeat (4) @(posedge CLK) ;
//set simulation-only parameters //set simulation-only parameters
...@@ -836,7 +845,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -836,7 +845,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
1, //WINDOW_WIDTH, 1, //WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
test_scanline_read ( test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel; 1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages; SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
...@@ -844,7 +854,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -844,7 +854,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
1, // WINDOW_WIDTH, 1, // WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
test_scanline_write( test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel; 1, // valid: 1 or 3 input [3:0] channel;
...@@ -853,7 +864,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -853,7 +864,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
2, //WINDOW_WIDTH, 2, //WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
test_scanline_read ( test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel; 1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages; SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
...@@ -861,7 +873,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -861,7 +873,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
2, // WINDOW_WIDTH, 2, // WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
test_scanline_write( test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel; 1, // valid: 1 or 3 input [3:0] channel;
...@@ -870,7 +883,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -870,7 +883,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
3, //WINDOW_WIDTH, 3, //WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
test_scanline_read ( test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel; 1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages; SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
...@@ -878,7 +892,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -878,7 +892,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
3, // WINDOW_WIDTH, 3, // WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
...@@ -894,7 +909,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -894,7 +909,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
WINDOW_WIDTH, WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
`endif `endif
`ifdef TEST_SCANLINE_READ `ifdef TEST_SCANLINE_READ
...@@ -907,7 +923,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -907,7 +923,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
WINDOW_WIDTH, WINDOW_WIDTH,
WINDOW_HEIGHT, WINDOW_HEIGHT,
WINDOW_X0, WINDOW_X0,
WINDOW_Y0); WINDOW_Y0,
1); // repetitive mode
`endif `endif
...@@ -1001,7 +1018,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -1001,7 +1018,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0, // input continue; // 0 start from start64, 1 - continue from where it was 0, // input continue; // 0 start from start64, 1 - continue from where it was
0, // disable_need 0, // disable_need
'h13); //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug 'h13, //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug
1) // repetitive mode
`endif `endif
...@@ -1025,7 +1043,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -1025,7 +1043,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0, // input continue; // 0 start from start64, 1 - continue from where it was 0, // input continue; // 0 start from start64, 1 - continue from where it was
0, // disable_need 0, // disable_need
'h13); //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug 'h13, //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug
1) // repetitive mode
$display("===================== #2 TEST_%s =========================",TEST_TITLE); $display("===================== #2 TEST_%s =========================",TEST_TITLE);
test_afi_rw ( test_afi_rw (
...@@ -1043,7 +1062,8 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -1043,7 +1062,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0, // input continue; // 0 start from start64, 1 - continue from where it was 0, // input continue; // 0 start from start64, 1 - continue from where it was
0, // disable_need 0, // disable_need
'h13); //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug 'h13, //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug
1) // repetitive mode
`endif `endif
...@@ -1246,10 +1266,14 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -1246,10 +1266,14 @@ assign #10 gpio_pins[9] = gpio_pins[8];
`ifdef COMPRESS_SINGLE `ifdef COMPRESS_SINGLE
TEST_TITLE = "COMPRESS_FRAME"; TEST_TITLE = "COMPRESS_FRAME";
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
compressor_run (0, 2); // run single // compressor_run (0, 2); // run single
compressor_run (1, 2); // run single // compressor_run (1, 2); // run single
compressor_run (2, 2); // run single // compressor_run (2, 2); // run single
compressor_run (3, 2); // run single // compressor_run (3, 2); // run single
compressor_run (0, 3); // run repetitive
compressor_run (1, 3); // run repetitive
compressor_run (2, 3); // run repetitive
compressor_run (3, 3); // run repetitive
`endif `endif
`ifdef READBACK_DELAYS `ifdef READBACK_DELAYS
...@@ -1265,13 +1289,33 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -1265,13 +1289,33 @@ assign #10 gpio_pins[9] = gpio_pins[8];
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_membridge (0, // for sensor 0 setup_sensor_membridge (0, // for sensor 0
1) ; // disable_need 1, // disable_need
0, // read from ddr3
1); // repetitive mode
TEST_TITLE = "MEMBRIDGE READ #2"; TEST_TITLE = "MEMBRIDGE READ #2";
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_membridge (0, // for sensor 0 setup_sensor_membridge (0, // for sensor 0
1) ; // disable_need 1, // disable_need
0, // read from ddr3
0); // single mode
TEST_TITLE = "MEMBRIDGE_WRITE # 1";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_membridge (0, // for sensor 0
1, // disable_need
1, // read from ddr3
1); // repetitive mode
TEST_TITLE = "MEMBRIDGE_WRITE # 2";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_membridge (0, // for sensor 0
1, // disable_need
1, // read from ddr3
0); // single mode
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
...@@ -1298,8 +1342,10 @@ end ...@@ -1298,8 +1342,10 @@ end
// protect from never end // protect from never end
initial begin initial begin
// #30000; // #30000;
#200000; // #200000;
// #250000; // #250000;
// #160000;
#175000;
// #60000; // #60000;
$display("finish testbench 2"); $display("finish testbench 2");
$finish; $finish;
...@@ -1541,8 +1587,10 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1541,8 +1587,10 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.sns2_dp74 (sns2_dp[7:4]), // inout[3:0] .sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
.sns2_dn74 (sns2_dn[7:4]), // inout[3:0] .sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
`else `else
.sns2_dp (sns1_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK} // .sns2_dp (sns1_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
.sns2_dn (sns1_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF} // .sns2_dn (sns1_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
.sns2_dp (sns2_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
.sns2_dn (sns2_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
`endif `endif
.sns2_clkp (sns2_clkp), // inout CNVCLK/TDO .sns2_clkp (sns2_clkp), // inout CNVCLK/TDO
.sns2_clkn (sns2_clkn), // inout CNVSYNC/TDI .sns2_clkn (sns2_clkn), // inout CNVSYNC/TDI
...@@ -2708,12 +2756,13 @@ task setup_sensor_channel; ...@@ -2708,12 +2756,13 @@ task setup_sensor_channel;
compressor_run (num_sensor, 0); // reset compressor compressor_run (num_sensor, 0); // reset compressor
simulation_datasimulation_dataspecify_window 66 36 0 0 0 3 1
if (cmode == CMPRS_CBIT_CMODE_JPEG18) begin if (cmode == CMPRS_CBIT_CMODE_JPEG18) begin
setup_compressor_channel( setup_compressor_channel(
num_sensor, // sensor channel number (0..3) num_sensor, // sensor channel number (0..3)
0, // qbank; // [6:3] quantization table page - 100% quality ((num_sensor == 1) || (num_sensor == 3))? 1 : 0, // 0, // qbank; // [6:3] quantization table page - 100% quality
// (num_sensor[1] ^ num_sensor[0]) ? 1 : 0, // 0, // qbank; // [6:3] quantization table page - 100% quality
// 1, // qbank; // [6:3] quantization table page - 85%? quality // 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC 1, // dc_sub; // [8:7] subtract DC
cmode, // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode: cmode, // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
...@@ -2735,7 +2784,8 @@ task setup_sensor_channel; ...@@ -2735,7 +2784,8 @@ task setup_sensor_channel;
0, // input [31:0] focus_mode; // [23:21] Set focus mode 0, // input [31:0] focus_mode; // [23:21] Set focus mode
3, // num_macro_cols_m1; // number of macroblock colums minus 1 3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1 1, // num_macro_rows_m1; // number of macroblock rows minus 1
1, // input [31:0] left_margin; // left margin of the first pixel (0..31) for 32-pixel wide colums in memory access // No shift may break same result as x353?
0, // make same as JP4, no shift 1, // input [31:0] left_margin; // left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
'h120, // input [31:0] colorsat_blue; //color saturation for blue (10 bits) //'h90 for 100% 'h120, // input [31:0] colorsat_blue; //color saturation for blue (10 bits) //'h90 for 100%
'h16c, // colorsat_red; //color saturation for red (10 bits) // 'b6 for 100% 'h16c, // colorsat_red; //color saturation for red (10 bits) // 'b6 for 100%
0); // input [31:0] coring; // coring value 0); // input [31:0] coring; // coring value
...@@ -2749,7 +2799,9 @@ task setup_sensor_channel; ...@@ -2749,7 +2799,9 @@ task setup_sensor_channel;
window_width, // & ~3, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts window_width, // & ~3, // input [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
window_height & ~15, // input [31:0] window_height; // 16 bit window_height & ~15, // input [31:0] window_height; // 16 bit
window_left, // input [31:0] window_left; window_left, // input [31:0] window_left;
window_top+1, // input [31:0] window_top; (to match 20x20 tiles in 353) // window_top+1, // input [31:0] window_top; (to match 20x20 tiles in 353)
window_top, // make same as JP4, no shift 1, // input [31:0] window_top; (to match 20x20 tiles in 353)
1, // input byte32; // == 1? 1, // input byte32; // == 1?
2, //input [31:0] tile_width; // == 2 2, //input [31:0] tile_width; // == 2
1, // input [31:0] extra_pages; // 1 1, // input [31:0] extra_pages; // 1
...@@ -2948,6 +3000,8 @@ endtask // setup_sensor_channel ...@@ -2948,6 +3000,8 @@ endtask // setup_sensor_channel
task setup_sensor_membridge; task setup_sensor_membridge;
input [1:0] num_sensor; input [1:0] num_sensor;
input disable_need; input disable_need;
input write_video_memory;
input rpt;
reg [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes) reg [31:0] frame_full_width; // 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
reg [31:0] window_width; // 13 bit - in 8*16=128 bit bursts reg [31:0] window_width; // 13 bit - in 8*16=128 bit bursts
...@@ -2965,7 +3019,7 @@ task setup_sensor_membridge; ...@@ -2965,7 +3019,7 @@ task setup_sensor_membridge;
frame_start_address = FRAME_START_ADDRESS + num_sensor * FRAME_START_ADDRESS_INC * (LAST_BUF_FRAME + 1); frame_start_address = FRAME_START_ADDRESS + num_sensor * FRAME_START_ADDRESS_INC * (LAST_BUF_FRAME + 1);
// frame_start_address_inc = FRAME_START_ADDRESS_INC; // frame_start_address_inc = FRAME_START_ADDRESS_INC;
test_afi_rw ( test_afi_rw (
0, // write_ddr3; write_video_memory, // write_ddr3;
SCANLINE_EXTRA_PAGES, // extra_pages; SCANLINE_EXTRA_PAGES, // extra_pages;
frame_start_address[21:0], // input [21:0] frame_start_addr; frame_start_address[21:0], // input [21:0] frame_start_addr;
frame_full_width[15:0], // input [15:0] window_full_width; // 13 bit - in 8*16=128 bit bursts frame_full_width[15:0], // input [15:0] window_full_width; // 13 bit - in 8*16=128 bit bursts
...@@ -2978,7 +3032,8 @@ task setup_sensor_membridge; ...@@ -2978,7 +3032,8 @@ task setup_sensor_membridge;
AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words AFI_SIZE64, // input [28:0] size64; // size of the system memory range in 64-bit words
0, // input continue; // 0 start from start64, 1 - continue from where it was 0, // input continue; // 0 start from start64, 1 - continue from where it was
disable_need, disable_need,
'h13); // cache_mode; // 'h3 - normal, 'h13 - debug 'h13, //'h3); // cache_mode; // 'h3 - normal, 'h13 - debug
rpt); // repetitive mode
end end
...@@ -4590,6 +4645,426 @@ endtask ...@@ -4590,6 +4645,426 @@ endtask
`include "includes/x393_tasks01.vh" `include "includes/x393_tasks01.vh"
`include "includes/x393_mcontr_encode_cmd.vh" `include "includes/x393_mcontr_encode_cmd.vh"
// Save sensor data written to memory
reg [3:0] CAPTURE_SENSORS = 0;
reg [3:0] CAPTURED_SENSORS = 0;
//reg [3:0] CAPTURE_SENSORS_D = 0;
//x393_i.pclk
//always @ (posedge x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.pclk);
always @ (posedge x393_i.pclk or posedge RST_CLEAN) begin
if (RST_CLEAN) CAPTURE_SENSORS <= 0;
else CAPTURE_SENSORS <= (~CAPTURED_SENSORS & x393_i.sensors393_i.sof_out_pclk) | (CAPTURE_SENSORS & ~x393_i.sensors393_i.eof_out_pclk) ;
if (RST_CLEAN) CAPTURED_SENSORS <= 0;
else CAPTURED_SENSORS <= CAPTURED_SENSORS | (CAPTURE_SENSORS & x393_i.sensors393_i.eof_out_pclk);
// if (RST_CLEAN) CAPTURE_SENSORS_D <= 0;
// else CAPTURE_SENSORS_D <= CAPTURE_SENSORS;
end
localparam WRITE_SENSOR_CHN0 = 0;
localparam WRITE_SENSOR_CHN1 = 1;
localparam WRITE_SENSOR_CHN2 = 2;
localparam WRITE_SENSOR_CHN3 = 3;
localparam CAPTURE_FOREVER = 0; // 1;
integer file_chn0,file_chn1,file_chn2,file_chn3;
initial begin
@(posedge CAPTURE_SENSORS[WRITE_SENSOR_CHN0]);
file_chn0 = $fopen("simulation_data/sensor_to_memory_0.dat","w");
$display("capture chn0 file opened, CAPTURE_SENSORS[WRITE_SENSOR_CHN0]= %x @%t",CAPTURE_SENSORS[WRITE_SENSOR_CHN0], $time);
while (CAPTURE_SENSORS[WRITE_SENSOR_CHN0]) begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN0]) begin
// $display("file_chn0 <= %x",x393_i.sensors393_i.px_data[WRITE_SENSOR_CHN0]);
$fwrite(file_chn0," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN0 +: 8]);
$fwrite(file_chn0," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN0+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN0])
$fwrite(file_chn0,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_chn0,"\n");
$display("capture chn0 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN0]) begin
$fwrite(file_chn0," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN0 +: 8]);
$fwrite(file_chn0," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN0+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN0])
$fwrite(file_chn0,"\n");
end
end
end
$fclose(file_chn0);
$display("capture chn0 ended @%t",$time);
end
initial begin
@(posedge CAPTURE_SENSORS[WRITE_SENSOR_CHN1]);
file_chn1 = $fopen("simulation_data/sensor_to_memory_1.dat","w");
$display("capture chn1 file opened, CAPTURE_SENSORS[WRITE_SENSOR_CHN1]= %x @%t",CAPTURE_SENSORS[WRITE_SENSOR_CHN1], $time);
while (CAPTURE_SENSORS[WRITE_SENSOR_CHN1]) begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN1]) begin
$fwrite(file_chn1," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN1 +: 8]);
$fwrite(file_chn1," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN1+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN1])
$fwrite(file_chn1,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_chn1,"\n");
$display("capture chn1 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN1]) begin
$fwrite(file_chn1," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN1 +: 8]);
$fwrite(file_chn1," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN1+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN1])
$fwrite(file_chn1,"\n");
end
end
end
$fclose(file_chn1);
$display("capture chn1 ended @%t",$time);
end
initial begin
@(posedge CAPTURE_SENSORS[WRITE_SENSOR_CHN2]);
file_chn2 = $fopen("simulation_data/sensor_to_memory_2.dat","w");
$display("capture chn2 file opened, CAPTURE_SENSORS[WRITE_SENSOR_CHN2]= %x @%t",CAPTURE_SENSORS[WRITE_SENSOR_CHN2], $time);
while (CAPTURE_SENSORS[WRITE_SENSOR_CHN2]) begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN2]) begin
$fwrite(file_chn2," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN2 +: 8]);
$fwrite(file_chn2," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN2+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN2])
$fwrite(file_chn2,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_chn2,"\n");
$display("capture chn2 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN2]) begin
$fwrite(file_chn2," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN2 +: 8]);
$fwrite(file_chn2," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN2+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN2])
$fwrite(file_chn2,"\n");
end
end
end
$fclose(file_chn2);
$display("capture chn2 ended @%t",$time);
end
initial begin
@(posedge CAPTURE_SENSORS[WRITE_SENSOR_CHN3]);
file_chn3 = $fopen("simulation_data/sensor_to_memory_3.dat","w");
$display("capture chn3 file opened, CAPTURE_SENSORS[WRITE_SENSOR_CHN3]= %x @%t",CAPTURE_SENSORS[WRITE_SENSOR_CHN3], $time);
while (CAPTURE_SENSORS[WRITE_SENSOR_CHN3]) begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN3]) begin
$fwrite(file_chn3," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN3 +: 8]);
$fwrite(file_chn3," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN3+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN3])
$fwrite(file_chn3,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_chn3,"\n");
$display("capture chn3 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN3]) begin
$fwrite(file_chn3," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN3 +: 8]);
$fwrite(file_chn3," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN3+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN3])
$fwrite(file_chn3,"\n");
end
end
end
$fclose(file_chn3);
$display("capture chn3 ended @%t",$time);
end
/*
initial begin
@(posedge CAPTURE_SENSORS[WRITE_SENSOR_CHN]);
file_chn = $fopen("sensor_to_memory.dat","w");
$display("capture chn file opened, CAPTURE_SENSORS[WRITE_SENSOR_CHN]= %x @%t",CAPTURE_SENSORS[WRITE_SENSOR_CHN], $time);
while (CAPTURE_SENSORS[WRITE_SENSOR_CHN]) begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN]) begin
$fwrite(file_chn," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN +: 8]);
$fwrite(file_chn," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN])
$fwrite(file_chn,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_chn,"\n");
$display("capture chn first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.pclk);
if (x393_i.sensors393_i.px_valid[WRITE_SENSOR_CHN]) begin
$fwrite(file_chn," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN +: 8]);
$fwrite(file_chn," %02x",x393_i.sensors393_i.px_data[16*WRITE_SENSOR_CHN+8 +: 8]);
if (x393_i.sensors393_i.last_in_line[WRITE_SENSOR_CHN])
$fwrite(file_chn,"\n");
end
end
end
$fclose(file_chn);
$display("capture chn ended @%t",$time);
end
*/
integer file_cmprs_chn0, file_cmprs_chn1, file_cmprs_chn2, file_cmprs_chn3;
localparam WRITE_COMPRESSOR_CHN0 = 0;
localparam WRITE_COMPRESSOR_CHN1 = 1;
localparam WRITE_COMPRESSOR_CHN2 = 2;
localparam WRITE_COMPRESSOR_CHN3 = 3;
reg [3:0] CAPTURE_COMPRESSORS = 0;
reg [3:0] CAPTURED_COMPRESSORS = 0;
reg [3:0] CAPTURE_COMPRESSORS_REN_D;
reg [3:0] CAPTURE_COMPRESSORS_REN_D2;
wire [3:0] CAPTURE_COMPRESSOR_START;
pulse_cross_clock capture_compressor_start_0_i (.rst(RST_CLEAN), .src_clk(x393_i.mclk), .dst_clk(x393_i.hclk),
.in_pulse(x393_i.compressor393_i.frame_start_dst[0]), .out_pulse(CAPTURE_COMPRESSOR_START[0]),.busy());
pulse_cross_clock capture_compressor_start_1_i (.rst(RST_CLEAN), .src_clk(x393_i.mclk), .dst_clk(x393_i.hclk),
.in_pulse(x393_i.compressor393_i.frame_start_dst[1]), .out_pulse(CAPTURE_COMPRESSOR_START[1]),.busy());
pulse_cross_clock capture_compressor_start_2_i (.rst(RST_CLEAN), .src_clk(x393_i.mclk), .dst_clk(x393_i.hclk),
.in_pulse(x393_i.compressor393_i.frame_start_dst[2]), .out_pulse(CAPTURE_COMPRESSOR_START[2]),.busy());
pulse_cross_clock capture_compressor_start_3_i (.rst(RST_CLEAN), .src_clk(x393_i.mclk), .dst_clk(x393_i.hclk),
.in_pulse(x393_i.compressor393_i.frame_start_dst[3]), .out_pulse(CAPTURE_COMPRESSOR_START[3]),.busy());
always @ (posedge x393_i.hclk or posedge RST_CLEAN) begin
if (RST_CLEAN) CAPTURE_COMPRESSORS <= 0;
else CAPTURE_COMPRESSORS <= (~CAPTURED_COMPRESSORS & CAPTURE_COMPRESSOR_START) | (CAPTURE_COMPRESSORS & ~x393_i.compressor393_i.eof_written) ;
if (RST_CLEAN) CAPTURED_COMPRESSORS <= 0;
else CAPTURED_COMPRESSORS <= CAPTURED_COMPRESSORS | (CAPTURE_COMPRESSORS & x393_i.compressor393_i.eof_written);
if (RST_CLEAN) CAPTURE_COMPRESSORS_REN_D <= 0;
else CAPTURE_COMPRESSORS_REN_D <= x393_i.compressor393_i.fifo_ren;
if (RST_CLEAN) CAPTURE_COMPRESSORS_REN_D2 <= 0;
else CAPTURE_COMPRESSORS_REN_D2 <= CAPTURE_COMPRESSORS_REN_D;
end
initial begin
@(posedge CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN0]);
file_cmprs_chn0 = $fopen("simulation_data/compressor_out_0.dat","w");
$display("capture compressor chn0 file opened, CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN0]= %x @%t",CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN0], $time);
while (CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN0]) begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN0]) begin
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 8 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 16 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 24 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 32 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 40 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 48 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 56 +: 8]);
$fwrite(file_cmprs_chn0,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_cmprs_chn0,"\n");
$display("capture compressor chn0 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN0]) begin
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 8 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 16 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 24 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 32 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 40 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 48 +: 8]);
$fwrite(file_cmprs_chn0," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN0 + 56 +: 8]);
$fwrite(file_cmprs_chn0,"\n");
end
end
end
$fclose(file_cmprs_chn0);
$display("capture compressor chn0 ended @%t",$time);
end
initial begin
@(posedge CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN1]);
file_cmprs_chn1 = $fopen("simulation_data/compressor_out_1.dat","w");
$display("capture compressor chn1 file opened, CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN1]= %x @%t",CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN1], $time);
while (CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN1]) begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN1]) begin
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 8 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 16 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 24 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 32 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 40 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 48 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 56 +: 8]);
$fwrite(file_cmprs_chn1,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_cmprs_chn1,"\n");
$display("capture compressor chn1 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN1]) begin
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 8 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 16 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 24 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 32 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 40 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 48 +: 8]);
$fwrite(file_cmprs_chn1," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN1 + 56 +: 8]);
$fwrite(file_cmprs_chn1,"\n");
end
end
end
$fclose(file_cmprs_chn1);
$display("capture compressor chn1 ended @%t",$time);
end
initial begin
@(posedge CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN2]);
file_cmprs_chn2 = $fopen("simulation_data/compressor_out_2.dat","w");
$display("capture compressor chn2 file opened, CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN2]= %x @%t",CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN2], $time);
while (CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN2]) begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN2]) begin
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 8 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 16 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 24 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 32 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 40 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 48 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 56 +: 8]);
$fwrite(file_cmprs_chn2,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_cmprs_chn2,"\n");
$display("capture compressor chn2 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN2]) begin
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 8 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 16 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 24 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 32 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 40 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 48 +: 8]);
$fwrite(file_cmprs_chn2," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN2 + 56 +: 8]);
$fwrite(file_cmprs_chn2,"\n");
end
end
end
$fclose(file_cmprs_chn2);
$display("capture compressor chn2 ended @%t",$time);
end
initial begin
@(posedge CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN3]);
file_cmprs_chn3 = $fopen("simulation_data/compressor_out_3.dat","w");
$display("capture compressor chn3 file opened, CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN3]= %x @%t",CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN3], $time);
while (CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN3]) begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN3]) begin
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 8 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 16 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 24 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 32 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 40 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 48 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 56 +: 8]);
$fwrite(file_cmprs_chn3,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_cmprs_chn3,"\n");
$display("capture compressor chn3 first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN3]) begin
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 8 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 16 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 24 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 32 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 40 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 48 +: 8]);
$fwrite(file_cmprs_chn3," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN3 + 56 +: 8]);
$fwrite(file_cmprs_chn3,"\n");
end
end
end
$fclose(file_cmprs_chn3);
$display("capture compressor chn3 ended @%t",$time);
end
/*
integer file_cmprs_chn;
localparam capture compressor chn0 = 0;
initial begin
@(posedge CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN]);
file_cmprs_chn = $fopen("compressor_out.dat","w");
$display("capture compressor chn file opened, CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN]= %x @%t",CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN], $time);
while (CAPTURE_COMPRESSORS[WRITE_COMPRESSOR_CHN]) begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN]) begin
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 8 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 16 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 24 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 32 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 40 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 48 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 56 +: 8]);
$fwrite(file_cmprs_chn,"\n");
end
end
if (CAPTURE_FOREVER) begin
$fwrite(file_cmprs_chn,"\n");
$display("capture chn first frame done, continue capturing @%t",$time);
forever begin
@(posedge x393_i.hclk);
if (CAPTURE_COMPRESSORS_REN_D2[WRITE_COMPRESSOR_CHN]) begin
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 8 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 16 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 24 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 32 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 40 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 48 +: 8]);
$fwrite(file_cmprs_chn," %x",x393_i.compressor393_i.fifo_rdata[64*WRITE_COMPRESSOR_CHN + 56 +: 8]);
$fwrite(file_cmprs_chn,"\n");
end
end
end
$fclose(file_cmprs_chn);
$display("capture compressor chn ended @%t",$time);
end
*/
endmodule endmodule
x393_testbench04.sav 0 → 100644
View file @ 82e11ec7
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed May 4 20:52:00 2016
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160504133628289.fst"
[dumpfile_mtime] "Wed May 4 20:03:27 2016"
[dumpfile_size] 89230413
[savefile] "/home/andrey/git/x393/x393_testbench04.sav"
[timestart] 0
[size] 1823 1180
[pos] -1 -1
*-24.733164 47500000 121282388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.simul_axi_hp_wr_i.
[treeopen] x393_testbench03.x393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.
[sst_width] 257
[signals_width] 340
[sst_expanded] 1
[sst_vpaned_height] 575
@820
x393_testbench03.TEST_TITLE[639:0]
@800200
-all_cmprs_out
@28
x393_testbench03.x393_i.hclk
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_eof
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_rdata[63:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_ren
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.fifo_eof
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.fifo_rdata[63:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.fifo_ren
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.fifo_eof
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.fifo_rdata[63:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.fifo_ren
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.fifo_eof
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.fifo_rdata[63:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.fifo_ren
@22
x393_testbench03.setup_sensor_channel.num_sensor[1:0]
x393_testbench03.setup_compressor_channel.num_sensor[1:0]
@23
x393_testbench03.setup_compressor_channel.qbank[31:0]
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_qpage[2:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_qpage[2:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_qpage[2:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_qpage[2:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.bayer_phase[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.bayer_phase[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.bayer_phase[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.bayer_phase[1:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.coring_num[2:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmd_we
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmd_a[2:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmd_data[31:0]
x393_testbench03.x393_i.compressor393_i.fifo_ren[3:0]
x393_testbench03.x393_i.compressor393_i.fifo_rdata[255:0]
@c00022
x393_testbench03.x393_i.compressor393_i.fifo_eof[3:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.fifo_eof[3:0]
(1)x393_testbench03.x393_i.compressor393_i.fifo_eof[3:0]
(2)x393_testbench03.x393_i.compressor393_i.fifo_eof[3:0]
(3)x393_testbench03.x393_i.compressor393_i.fifo_eof[3:0]
@1401200
-group_end
@800022
x393_testbench03.x393_i.compressor393_i.frame_start_dst[3:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.frame_start_dst[3:0]
(1)x393_testbench03.x393_i.compressor393_i.frame_start_dst[3:0]
(2)x393_testbench03.x393_i.compressor393_i.frame_start_dst[3:0]
(3)x393_testbench03.x393_i.compressor393_i.frame_start_dst[3:0]
@c00022
x393_testbench03.x393_i.compressor393_i.eof_written[3:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.eof_written[3:0]
(1)x393_testbench03.x393_i.compressor393_i.eof_written[3:0]
(2)x393_testbench03.x393_i.compressor393_i.eof_written[3:0]
(3)x393_testbench03.x393_i.compressor393_i.eof_written[3:0]
@1401200
-group_end
@28
x393_testbench03.RST_CLEAN
@1001200
-group_end
@800022
x393_testbench03.CAPTURE_COMPRESSORS[3:0]
@28
(0)x393_testbench03.CAPTURE_COMPRESSORS[3:0]
(1)x393_testbench03.CAPTURE_COMPRESSORS[3:0]
(2)x393_testbench03.CAPTURE_COMPRESSORS[3:0]
(3)x393_testbench03.CAPTURE_COMPRESSORS[3:0]
@1001200
-group_end
@800022
x393_testbench03.CAPTURED_COMPRESSORS[3:0]
@28
(0)x393_testbench03.CAPTURED_COMPRESSORS[3:0]
(1)x393_testbench03.CAPTURED_COMPRESSORS[3:0]
(2)x393_testbench03.CAPTURED_COMPRESSORS[3:0]
(3)x393_testbench03.CAPTURED_COMPRESSORS[3:0]
@1001200
-group_end
@200
-
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.left_marg[4:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.left_marg[4:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.left_marg[4:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.left_marg[4:0]
@1000200
-all_cmprs_out
@c00200
-all_sensor_data
@22
x393_testbench03.PX1_D[11:0]
x393_testbench03.PX2_D[11:0]
x393_testbench03.PX3_D[11:0]
x393_testbench03.PX4_D[11:0]
@28
x393_testbench03.PX2_DCLK
@22
x393_testbench03.PX2_D[11:0]
@28
x393_testbench03.PX2_FLASH
x393_testbench03.PX2_HACT
x393_testbench03.PX2_MCLK
x393_testbench03.PX2_MCLK_PRE
x393_testbench03.PX2_MRST
x393_testbench03.PX2_OFST
x393_testbench03.PX2_SHUTTER
@22
x393_testbench03.sns2_dn[7:0]
x393_testbench03.sns2_dp[7:0]
x393_testbench03.sns1_dn[7:0]
x393_testbench03.sns1_dp[7:0]
@200
-
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.pxd[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.pxd[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.pxd[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
@200
-
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.dout[15:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.dout[15:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.dout[15:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.dout[15:0]
@800022
x393_testbench03.CAPTURE_SENSORS[3:0]
@28
(0)x393_testbench03.CAPTURE_SENSORS[3:0]
(1)x393_testbench03.CAPTURE_SENSORS[3:0]
(2)x393_testbench03.CAPTURE_SENSORS[3:0]
(3)x393_testbench03.CAPTURE_SENSORS[3:0]
@800022
x393_testbench03.CAPTURED_SENSORS[3:0]
@28
(0)x393_testbench03.CAPTURED_SENSORS[3:0]
(1)x393_testbench03.CAPTURED_SENSORS[3:0]
(2)x393_testbench03.CAPTURED_SENSORS[3:0]
(3)x393_testbench03.CAPTURED_SENSORS[3:0]
@1001200
-group_end
-group_end
@1401200
-all_sensor_data
@c00200
-membridge
@200
-
@22
x393_testbench03.x393_i.membridge_i.cmd_a[3:0]
x393_testbench03.x393_i.membridge_i.cmd_data[31:0]
@28
x393_testbench03.x393_i.membridge_i.cmd_we
@22
x393_testbench03.x393_i.membridge_i.lo_addr64[28:0]
x393_testbench03.x393_i.membridge_i.size64[28:0]
x393_testbench03.x393_i.membridge_i.start64[28:0]
x393_testbench03.x393_i.membridge_i.len64[28:0]
x393_testbench03.x393_i.membridge_i.width64_mclk[13:0]
x393_testbench03.x393_i.membridge_i.width64_minus1_mclk[13:0]
x393_testbench03.x393_i.membridge_i.mode_reg[4:0]
@28
x393_testbench03.x393_i.membridge_i.wlast
x393_testbench03.x393_i.membridge_i.set_ctrl_w
x393_testbench03.x393_i.membridge_i.start_hclk
x393_testbench03.x393_i.membridge_i.rdwr_reset_addr
x393_testbench03.x393_i.membridge_i.done
x393_testbench03.x393_i.membridge_i.busy
x393_testbench03.x393_i.membridge_i.rw_in_progress
x393_testbench03.x393_i.membridge_i.read_started
x393_testbench03.x393_i.membridge_i.next_page_rd
@22
x393_testbench03.x393_i.membridge_i.afi_araddr[31:0]
x393_testbench03.x393_i.membridge_i.afi_awaddr[31:0]
@28
x393_testbench03.x393_i.membridge_i.afi_awvalid
@22
x393_testbench03.x393_i.membridge_i.afi_rcount[7:0]
@c00022
x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
@28
(0)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(1)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(2)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(3)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(4)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(5)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(6)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
(7)x393_testbench03.x393_i.membridge_i.axi_arw_requested[7:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
@28
(0)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(1)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(2)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(3)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(4)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(5)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(6)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
(7)x393_testbench03.x393_i.membridge_i.axi_wr_pending[7:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.membridge_i.buf_left64[28:0]
x393_testbench03.x393_i.membridge_i.wresp_conf[7:0]
@28
x393_testbench03.x393_i.membridge_i.afi_wlast
x393_testbench03.x393_i.membridge_i.wlast
x393_testbench03.x393_i.membridge_i.afi_wready
x393_testbench03.x393_i.membridge_i.afi_wvalid
x393_testbench03.x393_i.membridge_i.left_was_1
x393_testbench03.x393_i.membridge_i.src_was_f
@22
x393_testbench03.x393_i.membridge_i.src_wcntr[3:0]
@28
x393_testbench03.x393_i.membridge_i.frame_done
x393_testbench03.x393_i.membridge_i.read_no_more
x393_testbench03.x393_i.membridge_i.read_over
x393_testbench03.x393_i.membridge_i.left_zero
x393_testbench03.x393_i.membridge_i.left_was_1
x393_testbench03.x393_i.membridge_i.is_last_in_page
x393_testbench03.x393_i.membridge_i.rw_in_progress
x393_testbench03.x393_i.membridge_i.left_many
x393_testbench03.x393_i.membridge_i.safe_some_left_rd_w
@22
x393_testbench03.x393_i.membridge_i.buf_in_line64[13:0]
x393_testbench03.x393_i.membridge_i.last_in_line64[13:0]
x393_testbench03.x393_i.membridge_i.buf_in_line64_r[6:0]
x393_testbench03.x393_i.membridge_i.afi_len_plus1[4:0]
@28
x393_testbench03.x393_i.membridge_i.advance_rel_addr
x393_testbench03.x393_i.membridge_i.page_ready_chn
x393_testbench03.x393_i.membridge_i.page_ready
@800200
-write_from_sys
@28
x393_testbench03.x393_i.membridge_i.is_last_in_page
@22
x393_testbench03.x393_i.membridge_i.bufwr_we[3:0]
@28
x393_testbench03.x393_i.membridge_i.next_page_wr_w
x393_testbench03.x393_i.membridge_i.page_ready_wr
@22
x393_testbench03.x393_i.membridge_i.write_pages_ready[2:0]
@200
-
@800200
-wr_ddr3_buf
@28
x393_testbench03.x393_i.membridge_i.xfer_reset_page_wr
x393_testbench03.x393_i.membridge_i.buf_rpage_nxt
x393_testbench03.x393_i.membridge_i.buf_rd
@22
x393_testbench03.x393_i.membridge_i.buf_rdata[63:0]
@1000200
-wr_ddr3_buf
@c00200
-linear_rw
@28
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_done
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_grant
@22
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mode_reg[12:0]
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0]
@200
-
@28
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_in_row_w
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_row_w
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.last_block
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pre_want_r1
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.want_r
@22
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_r[2:0]
@28
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pre_want
@c00022
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(1)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(2)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(3)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(4)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(5)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(6)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(7)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
(8)x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.recalc_r[8:0]
@1401200
-group_end
-linear_rw
@c00200
-memctrl16
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn[3:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.ext_buf_page_nxt
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata1[63:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.buf_rd_chn1
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.buf_rpage_nxt_chn1
@22
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.buf_rdata_chn1[63:0]
@28
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_done
x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrun
@1401200
-memctrl16
@c00200
-linear_rw_iface
@28
x393_testbench03.x393_i.membridge_i.frame_start_chn
x393_testbench03.x393_i.membridge_i.next_page_chn
x393_testbench03.x393_i.membridge_i.cmd_wrmem
x393_testbench03.x393_i.membridge_i.page_ready_chn
x393_testbench03.x393_i.membridge_i.frame_done_chn
@22
x393_testbench03.x393_i.membridge_i.line_unfinished_chn1[15:0]
@28
x393_testbench03.x393_i.membridge_i.suspend_chn1
@1401200
-linear_rw_iface
@1000200
-write_from_sys
@c00200
-read_to_sys
@22
x393_testbench03.x393_i.membridge_i.afi_wacount[5:0]
x393_testbench03.x393_i.membridge_i.afi_wcount[7:0]
@28
x393_testbench03.x393_i.membridge_i.afi_bvalid
x393_testbench03.x393_i.membridge_i.bufrd_rd_w
@800028
x393_testbench03.x393_i.membridge_i.bufrd_rd[2:0]
@28
(0)x393_testbench03.x393_i.membridge_i.bufrd_rd[2:0]
(1)x393_testbench03.x393_i.membridge_i.bufrd_rd[2:0]
(2)x393_testbench03.x393_i.membridge_i.bufrd_rd[2:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.membridge_i.read_pages_ready[2:0]
@28
x393_testbench03.x393_i.membridge_i.page_ready_rd
x393_testbench03.x393_i.membridge_i.done_page_rd_w
x393_testbench03.x393_i.membridge_i.next_page_rd_w
x393_testbench03.x393_i.membridge_i.read_started
x393_testbench03.x393_i.membridge_i.is_last_in_page
(2)x393_testbench03.x393_i.membridge_i.bufrd_rd[2:0]
@22
x393_testbench03.x393_i.membridge_i.axi_wr_left[7:0]
@200
-
@22
x393_testbench03.x393_i.membridge_i.read_page[1:0]
@28
x393_testbench03.x393_i.membridge_i.frame_done_chn
x393_testbench03.x393_i.membridge_i.read_busy
@1401200
-read_to_sys
-membridge
@c00200
-simul_axi_hp_wr0
@22
x393_testbench03.simul_axi_hp_wr_i.write_address[31:0]
x393_testbench03.simul_axi_hp_wr_i.wacount[5:0]
@28
x393_testbench03.simul_axi_hp_wr_i.enough_data
@22
x393_testbench03.simul_axi_hp_wr_i.wdata_i.wa[6:0]
x393_testbench03.simul_axi_hp_wr_i.wdata_i.ra[6:0]
x393_testbench03.simul_axi_hp_wr_i.wdata_i.rnum_in_fifo[7:0]
x393_testbench03.simul_axi_hp_wr_i.wdata_i.wnum_in_fifo[7:0]
@28
x393_testbench03.simul_axi_hp_wr_i.aclk
x393_testbench03.simul_axi_hp_wr_i.wlast
x393_testbench03.simul_axi_hp_wr_i.wvalid
x393_testbench03.simul_axi_hp_wr_i.inc_num_full_data
x393_testbench03.simul_axi_hp_wr_i.start_write_burst_w
@22
x393_testbench03.simul_axi_hp_wr_i.num_full_data[7:0]
@200
-
@1401200
-simul_axi_hp_wr0
[pattern_trace] 1
[pattern_trace] 0
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