got first images from mt9f002 (81da483f) · Commits · Elphel / x393

.project

+8 −8

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		@@ -62,42 +62,42 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107204814914.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151110124146463.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107204814914.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151110124625814.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

compressor_jp/bit_stuffer_metadata.v

+1 −1

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		@@ -146,7 +146,7 @@ module bit_stuffer_metadata(

		// just for testing
		`ifdef DEBUG_RING
		assign dbg_ = ts_rstb;
		assign dbg_ts_rstb = ts_rstb;
		assign dbg_ts_dout = ts_dout;

		always @ (posedge xclk) begin

compressor_jp/huffman_stuffer_meta.v

+5 −0

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		@@ -161,6 +161,11 @@ module huffman_stuffer_meta(
		.data_out_valid (data_out_valid), // output reg
		.done (done), // output reg
		.running (running) // output reg
		`ifdef DEBUG_RING
		,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
		.dbg_ts_rstb (dbg_ts_rstb), // output
		.dbg_ts_dout (dbg_ts_dout) // output[7:0]
		`endif
		);

		endmodule

compressor_jp/jp_channel.v

+15 −2

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		@@ -376,6 +376,7 @@ module jp_channel#(
		// wire flush; // output reg @ negedge xclk2x
		wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
		wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
		wire xrst2xn = xrst;
		`endif


		@@ -418,7 +419,19 @@ module jp_channel#(
		reg [15:0] dbg_zds_cntr;
		wire [2:0] dbg_block_mem_wa;
		wire [2:0] dbg_block_mem_wa_save;
		`ifndef USE_XCLK2X
		// temporarily assigning unused debug signals to 0
		assign dbg_add_invalid = 0;
		assign dbg_mb_release_buf = 0;
		assign etrax_dma = 0;
		assign dbg_ts_rstb = 0; // output
		assign dbg_ts_dout = 0; //output [7:0]
		assign dbg_flushing = 0;
		assign dbg_test_lbw = 0;
		assign dbg_gotLastBlock = 0;
		assign dbg_fifo_or_full = 0;

		`endif
		timestamp_to_parallel dbg_timestamp_to_parallel_i (
		`ifdef USE_XCLK2X
		.clk (~xclk2x), // input
		@@ -428,7 +441,7 @@ module jp_channel#(
		.pre_stb (dbg_ts_rstb), // input
		.tdata (dbg_ts_dout), // input[7:0]
		.sec (dbg_sec), // output[31:0] reg
		.usec (dbg_usec), // output[19:0] reg
		.usec (dbg_usec[19:0]), // output[19:0] reg
		.done() // output
		);

fpga_version.vh

+4 −1

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		@@ -31,8 +31,11 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*******************************************************************************/
		parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
		parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
		// parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
		// parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
		// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
		// Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
		// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
		// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
		// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)