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Commit 81da483f authored by Andrey Filippov's avatar Andrey Filippov
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got first images from mt9f002

parent 9d943d8e
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.project
View file @ 81da483f
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107204814914.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151110124146463.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107204814914.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
compressor_jp/bit_stuffer_metadata.v
View file @ 81da483f
......@@ -146,7 +146,7 @@ module bit_stuffer_metadata(
// just for testing
`ifdef DEBUG_RING
assign dbg_ = ts_rstb;
assign dbg_ts_rstb = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
......
compressor_jp/huffman_stuffer_meta.v
View file @ 81da483f
......@@ -161,6 +161,11 @@ module huffman_stuffer_meta(
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
......
compressor_jp/jp_channel.v
View file @ 81da483f
......@@ -376,6 +376,7 @@ module jp_channel#(
// wire flush; // output reg @ negedge xclk2x
wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
wire xrst2xn = xrst;
`endif
......@@ -418,7 +419,19 @@ module jp_channel#(
reg [15:0] dbg_zds_cntr;
wire [2:0] dbg_block_mem_wa;
wire [2:0] dbg_block_mem_wa_save;
`ifndef USE_XCLK2X
// temporarily assigning unused debug signals to 0
assign dbg_add_invalid = 0;
assign dbg_mb_release_buf = 0;
assign etrax_dma = 0;
assign dbg_ts_rstb = 0; // output
assign dbg_ts_dout = 0; //output [7:0]
assign dbg_flushing = 0;
assign dbg_test_lbw = 0;
assign dbg_gotLastBlock = 0;
assign dbg_fifo_or_full = 0;
`endif
timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
......@@ -428,7 +441,7 @@ module jp_channel#(
.pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg
.usec (dbg_usec), // output[19:0] reg
.usec (dbg_usec[19:0]), // output[19:0] reg
.done() // output
);
......
fpga_version.vh
View file @ 81da483f
......@@ -31,8 +31,11 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
// parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
// parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
......
includes/x393_simulation_parameters.vh
View file @ 81da483f
......@@ -41,7 +41,11 @@
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
`ifdef HISPI
parameter FCLK0_PERIOD = 40.91, // 24.444MHz
`else
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
......
py393/dbg/x393_mcntrl.pickle
View file @ 81da483f
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py393/vrlg.py
View file @ 81da483f
This diff is collapsed.
py393/x393_cmprs.py
View file @ 81da483f
......@@ -301,6 +301,7 @@ class X393Cmprs(object):
tile_height= 18
base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = disable_need,
repetitive= True,
single = False,
......
py393/x393_jpeg.py
View file @ 81da483f
......@@ -819,6 +819,27 @@ class X393Jpeg(object):
ff d9
"""
"""
cd /usr/local/verilog/; test_mcntrl.py @hargs
measure_all "*DI"
setup_all_sensors True None 0xf
write_sensor_i2c 0 1 0 0x030600b4
print_sensor_i2c 0 0x306 0xff 0x10 0
print_sensor_i2c 0 0x303a 0xff 0x10 0
print_sensor_i2c 0 0x301a 0xff 0x10 0
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x31c68402
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
#test pattern - 100% color bars
write_sensor_i2c 0 1 0 0x30700003
#test pattern - fadiong color bars
write_sensor_i2c 0 1 0 0x30700003
print_sensor_i2c 0 0x3070 0xff 0x10 0
Camera compressors testing sequence
cd /usr/local/verilog/; test_mcntrl.py @hargs
#or (for debug)
......@@ -1001,6 +1022,10 @@ jpeg_write "img.jpeg" all
write_sensor_i2c 0 1 0 0x91900004
print_sensor_i2c 0
print_debug 0x8 0xb
#Set "MSB first"and packet mode
write_sensor_i2c 0 1 0 0x31c60402
#r
add hwmon:
......@@ -1019,5 +1044,9 @@ root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8
root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8007100.ps7-xadc/vccint
966
write_sensor_i2c 0 1 0 0xff200000
print_sensor_i2c 0
"""
py393/x393_mcntrl.py
View file @ 81da483f
......@@ -40,7 +40,8 @@ __status__ = "Development"
#import time
import vrlg
def func_encode_mode_scan_tiled (disable_need = False,
def func_encode_mode_scan_tiled (skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
......@@ -52,6 +53,7 @@ def func_encode_mode_scan_tiled (disable_need = False,
chn_reset = False):
"""
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
@param disable_need - disable 'need' generation, only 'want' (compressor channels),
@param repetitive - run repetitive frames (add this to older 'master' tests)
@param single - run single frame
......@@ -77,6 +79,7 @@ def func_encode_mode_scan_tiled (disable_need = False,
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
return rslt
'''
......
py393/x393_mcntrl_membridge.py
View file @ 81da483f
......@@ -308,6 +308,7 @@ class X393McntrlMembridge(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_tests.py
View file @ 81da483f
......@@ -290,6 +290,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -442,6 +443,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -556,6 +558,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -698,6 +701,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_timing.py
View file @ 81da483f
......@@ -64,7 +64,8 @@ class X393McntrlTiming(object):
fSDCLK=fVCO/CLKOUT1_DIVIDE
tSDCLK=1000.0/fSDCLK # in ns
phaseStep=1000.0/(fVCO*56.0) # 1 unit of phase shift (now 112 for the full period
fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
# fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
fREF=fCLK_IN*vrlg.MULTICLK_MULT/vrlg.MULTICLK_DIV_DLYREF/vrlg.MULTICLK_DIVCLK
dlyStep=1000.0/fREF/32/2 # Approximate, depending on calibration
dlyFStep=0.01 # fine step
return{"SDCLK_PERIOD":tSDCLK,
......
py393/x393_sens_cmprs.py
View file @ 81da483f
This diff is collapsed.
py393/x393_sensor.py
View file @ 81da483f
......@@ -262,7 +262,7 @@ class X393Sensor(object):
rslt |= 1 << vrlg.SENSI2C_TBL_RNWREG # this is read register command (0 - write register)
if two_byte_addr > 1:
two_byte_addr = 1
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_SA
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_NABRD
rslt |= (num_bytes_rd & ((1 << vrlg.SENSI2C_TBL_NBRD_BITS) - 1)) << vrlg.SENSI2C_TBL_NBRD
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
return rslt
......@@ -474,6 +474,8 @@ class X393Sensor(object):
verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, td)
if verbose > 1:
print ("ta= 0x%x, td = 0x%x"%(ta,td))
def write_sensor_i2c (self,
num_sensor,
......@@ -495,7 +497,7 @@ class X393Sensor(object):
sent for such extra word, only the lower bytes are sent.
2 - register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
read address in teh table is programmed to be a single-byte one
read address in the table is programmed to be a single-byte one
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1057,6 +1059,7 @@ class X393Sensor(object):
"""
base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = True,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_utils.py
View file @ 81da483f
......@@ -96,6 +96,10 @@ class X393Utils(object):
"""
if bitfile is None:
bitfile=DEFAULT_BITFILE
print ("Sensor ports power off")
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
......
sensor/sens_10398.v
View file @ 81da483f
......@@ -271,7 +271,7 @@ module sens_10398 #(
// generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
always @(posedge pclk) begin
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2) -1;
else pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;
// treat MSB separately to make 50% duty cycle
if (prst) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= 0;
......
sensor/sensor_channel.v
View file @ 81da483f
......@@ -462,13 +462,30 @@ module sensor_channel#(
`ifdef DEBUG_RING
reg vact_to_fifo_r;
// reg vact_to_fifo_r;
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
`ifdef HISPI
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact;
if (sof) debug_line_cntr <= 0;
else if (hact && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
if (prst) hact_cntr <= 0;
else if (hact && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end
`else
always @(posedge ipclk) begin
vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact_to_fifo;
......@@ -485,6 +502,7 @@ module sensor_channel#(
else if (vact_to_fifo && !vact_to_fifo_r) vact_cntr <= vact_cntr + 1;
end
`endif
debug_slave #(
.SHIFT_WIDTH (128),
.READ_WIDTH (128),
......@@ -501,7 +519,12 @@ module sensor_channel#(
// .rd_data ({6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0], debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
.rd_data ({
lens_pxd_in, gamma_pxd_in[15:0],
pxd_to_fifo[11:0],pxd[11:0],gamma_pxd_out[7:0],
`ifdef HISPI
12'b0,
`else
pxd_to_fifo[11:0],
`endif
pxd[11:0],gamma_pxd_out[7:0],
6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0],
debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
......
status_read.v
View file @ 81da483f
......@@ -95,6 +95,9 @@ module status_read#(
assign axird_selected = select_r;
initial begin
ram [DATA_2DEPTH] = FPGA_VERSION;
`ifdef HISPI
ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor
`endif
end
always @ (posedge axi_clk) begin
if (arst) select_r <= 0;
......
system_defines.vh
View file @ 81da483f
......@@ -41,7 +41,7 @@
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
`define DEBUG_RING 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
......
x393_testbench03.sav
View file @ 81da483f
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Nov 8 07:30:39 2015
[*] Tue Nov 10 02:42:47 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151107210810890.fst"
[dumpfile_mtime] "Sun Nov 8 04:40:36 2015"
[dumpfile_size] 202201184
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151108002110369.fst"
[dumpfile_mtime] "Sun Nov 8 07:54:16 2015"
[dumpfile_size] 250548392
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0
[timestart] 62721200
[size] 1823 1180
[pos] 1920 0
*-25.279701 81782497 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-15.279701 62772842 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -35,12 +35,14 @@
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
......@@ -63,7 +65,7 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 445
[sst_width] 233
[signals_width] 348
[sst_expanded] 1
[sst_vpaned_height] 514
......@@ -86,6 +88,17 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.rst_mmcm
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@1001200
-group_end
@200
-
@c00200
-sens_hispi12l4
@28
......@@ -637,6 +650,8 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-sens_hispi_lane0
@1401200
-sens_hispi12l4
@29
x393_testbench03.ffclk0p
@200
-
@1000200
......@@ -1026,7 +1041,7 @@ x393_testbench03.simul_sensor12bits_i.c
x393_testbench03.simul_sensor12bits_i.state[3:0]
@28
x393_testbench03.simul_sensor12bits_i.stoppedd
@23
@22
x393_testbench03.simul_sensor12bits_i.cntrd[15:0]
@200
-
......
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