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Commit 81da483f authored by Andrey Filippov's avatar Andrey Filippov
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got first images from mt9f002

parent 9d943d8e
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.project
View file @ 81da483f
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107204814914.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151110124146463.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107204814914.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151110124625814.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
compressor_jp/bit_stuffer_metadata.v
View file @ 81da483f
......@@ -146,7 +146,7 @@ module bit_stuffer_metadata(
// just for testing
`ifdef DEBUG_RING
assign dbg_ = ts_rstb;
assign dbg_ts_rstb = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
......
compressor_jp/huffman_stuffer_meta.v
View file @ 81da483f
......@@ -161,6 +161,11 @@ module huffman_stuffer_meta(
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
......
compressor_jp/jp_channel.v
View file @ 81da483f
......@@ -376,6 +376,7 @@ module jp_channel#(
// wire flush; // output reg @ negedge xclk2x
wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
wire xrst2xn = xrst;
`endif
......@@ -418,7 +419,19 @@ module jp_channel#(
reg [15:0] dbg_zds_cntr;
wire [2:0] dbg_block_mem_wa;
wire [2:0] dbg_block_mem_wa_save;
`ifndef USE_XCLK2X
// temporarily assigning unused debug signals to 0
assign dbg_add_invalid = 0;
assign dbg_mb_release_buf = 0;
assign etrax_dma = 0;
assign dbg_ts_rstb = 0; // output
assign dbg_ts_dout = 0; //output [7:0]
assign dbg_flushing = 0;
assign dbg_test_lbw = 0;
assign dbg_gotLastBlock = 0;
assign dbg_fifo_or_full = 0;
`endif
timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
......@@ -428,7 +441,7 @@ module jp_channel#(
.pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg
.usec (dbg_usec), // output[19:0] reg
.usec (dbg_usec[19:0]), // output[19:0] reg
.done() // output
);
......
fpga_version.vh
View file @ 81da483f
......@@ -31,8 +31,11 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h0393006c; // will try debug for HiSPi. xclk violated by -0.030, slices 15062 (76.65%)
// parameter FPGA_VERSION = 32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
// parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// Worked OK, but different phase for sensor 0 (all quadrants as 1,3 OK)
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
......
includes/x393_simulation_parameters.vh
View file @ 81da483f
......@@ -41,7 +41,11 @@
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
`ifdef HISPI
parameter FCLK0_PERIOD = 40.91, // 24.444MHz
`else
parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
......
py393/dbg/x393_mcntrl.pickle
View file @ 81da483f
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/vrlg.py
View file @ 81da483f
......@@ -177,7 +177,6 @@ CLKFBOUT_PHASE_SENSOR = float
DFLT_REFRESH_PERIOD = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
NUM_CYCLES_20__TYPE = str
CMPRS_CSAT_CB__RAW = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
CMPRS_CBIT_RUN_BITS__TYPE = str
......@@ -207,14 +206,12 @@ MEMBRIDGE_WIDTH64__RAW = str
LOGGER_CONF_MSG_BITS__RAW = str
SENS_GAMMA_MODE_REPET = int
SENSI2C_TBL_DLY__RAW = str
CLKFBOUT_MULT_REF = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
RTC_SET_STATUS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
FFCLK0_IBUF_DELAY_VALUE__RAW = str
DEBUG_READ_REG_ADDR = int
WINDOW_HEIGHT = int
CAMSYNC_TRIG_DELAY0__RAW = str
......@@ -243,13 +240,13 @@ SENSOR_16BIT_BIT__RAW = str
HIST_SAXI_AWCACHE__TYPE = str
SENSI2C_CMD_RUN_PBITS__TYPE = str
LOGGER_CONF_SYN_BITS__TYPE = str
MULTICLK_DIVCLK__RAW = str
GPIO_ADDR__TYPE = str
CAMSYNC_TRIG_SRC = int
SENS_CTRL_GP1__RAW = str
CLKOUT_DIV_PCLK__TYPE = str
LOGGER_PAGE_IMU = int
MEMCLK_IOSTANDARD__RAW = str
CLKFBOUT_MULT_SYNC__TYPE = str
MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
......@@ -257,9 +254,11 @@ DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
NUM_CYCLES_30 = int
HISPI_DELAY_CLK0__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
HISPI_MMCM1 = str
SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
......@@ -267,7 +266,6 @@ SENS_LENS_RADDR__TYPE = str
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
FFCLK0_DQS_BIAS = str
CMPRS_JP4DIFF__TYPE = str
LOGGER_CONF_DBG__RAW = str
FRAME_START_ADDRESS_INC__TYPE = str
......@@ -275,7 +273,6 @@ DLY_DQS_IDELAY__TYPE = str
CLK_PHASE = float
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCONTR_SENS_STATUS_BASE__TYPE = str
SENSI2C_CMD_TAND__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
SENS_LENS_RADDR = int
......@@ -297,10 +294,12 @@ REF_JITTER1__RAW = str
CAMSYNC_MASK__TYPE = str
SENS_JTAG_PGMEN__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
SENS_CTRL_RST_MMCM = int
MCONTR_BUF3_RD_ADDR__TYPE = str
LOGGER_CONF_EN_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
MAX_TILE_WIDTH__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int
BUF_IPCLK2X_SENS1__RAW = str
SENSOR_MODE_WIDTH__RAW = str
......@@ -340,7 +339,7 @@ DFLT_WBUF_DELAY__RAW = str
CAMSYNC_POST_MAGIC__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
NUM_CYCLES_24__RAW = str
SENS_REFCLK_FREQUENCY__TYPE = str
NUM_CYCLES_13__RAW = str
LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
LAST_FRAME_BITS__RAW = str
......@@ -368,6 +367,7 @@ DIVCLK_DIVIDE = int
CMD_PAUSE_BITS__RAW = str
SENSI2C_TBL_DLY_BITS = int
IDELAY_VALUE__RAW = str
MULTICLK_PHASE_SYNC__TYPE = str
MCONTR_CMPRS_STATUS_BASE = int
BUFFER_DEPTH32 = int
SENS_CTRL_QUADRANTS__TYPE = str
......@@ -380,12 +380,10 @@ SENS_GAMMA_HEIGHT01__TYPE = str
CMPRS_HIFREQ_REG_INC = int
STATUS_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
NUM_CYCLES_13__RAW = str
TEST01_START_FRAME = int
RTC_SET_USEC__RAW = str
LOGGER_CONF_SYN_BITS__RAW = str
CAMSYNC_ADDR__TYPE = str
DIVCLK_DIVIDE_AXIHP__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
MULT_SAXI_BSLOG1__TYPE = str
LOGGER_CONF_MSG_BITS__TYPE = str
......@@ -408,12 +406,14 @@ NUM_CYCLES_20 = int
NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
CMDFRAMESEQ_REL__TYPE = str
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
NUM_CYCLES_LOW_BIT__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK = int
SENSI2C_SLEW = str
DFLT_WBUF_DELAY__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
SENSI2C_STATUS_REG_INC__TYPE = str
......@@ -421,9 +421,8 @@ CMPRS_FRMT_MBRM1_BITS__RAW = str
SCANLINE_EXTRA_PAGES = int
LD_DLY_LANE1_ODELAY__RAW = str
LOGGER_CONF_EN_BITS__RAW = str
DIVCLK_DIVIDE_SYNC__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
SENS_LENS_FAT0_IN_MASK__TYPE = str
PHASE_CLK2X_XCLK = float
RSEL = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
......@@ -435,6 +434,7 @@ CONTROL_ADDR__RAW = str
TILED_STARTY__RAW = str
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
HISPI_DELAY_CLK1__TYPE = str
NUM_CYCLES_14__TYPE = str
MCONTR_CMPRS_INC__TYPE = str
TILED_EXTRA_PAGES = int
......@@ -445,22 +445,22 @@ SENS_JTAG_TDI__RAW = str
MCONTR_SENS_STATUS_BASE = int
AXI_WR_ADDR_BITS__RAW = str
SENSI2C_CMD_RUN__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
CMPRS_CORING_MODE = int
DIVCLK_DIVIDE_SYNC__TYPE = str
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
FFCLK1_IOSTANDARD = str
SENS_JTAG_TMS__TYPE = str
MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
SENSIO_STATUS__TYPE = str
CLKIN_PERIOD_AXIHP__TYPE = str
GPIO_SLEW = str
LOGGER_CONF_SYN__TYPE = str
CAMSYNC_DELAY__RAW = str
LOGGER_CONF_DBG_BITS__RAW = str
FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
CLKFBOUT_MULT_SYNC = int
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long
SENS_LENS_C = int
......@@ -472,6 +472,7 @@ TABLE_HUFFMAN_INDEX = int
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
HISPI_DELAY_CLK1__RAW = str
SENSI2C_TBL_RNWREG__RAW = str
RTC_SEC_USEC_ADDR = int
LOGGER_CONF_DBG = int
......@@ -480,7 +481,6 @@ LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str
MCLK_PHASE__TYPE = str
DIVCLK_DIVIDE_XCLK__RAW = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
MCONTR_BUF2_WR_ADDR__TYPE = str
......@@ -491,29 +491,28 @@ SENS_REF_JITTER1__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
CMPRS_TABLES__TYPE = str
RTC_MHZ__RAW = str
FRAME_HEIGHT_BITS = int
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
CLKOUT_DIV_SYNC__RAW = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
CMPRS_TABLES__TYPE = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str
STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str
CLKIN_PERIOD__TYPE = str
SENS_GAMMA_CTRL = int
CLKFBOUT_MULT_AXIHP__RAW = str
SENSIO_RADDR = int
BUF_CLK1X_PCLK__RAW = str
BUF_CLK1X_XCLK2X = str
GPIO_N__TYPE = str
MCONTR_BUF4_RD_ADDR__TYPE = str
NUM_CYCLES_16__RAW = str
......@@ -523,7 +522,7 @@ SENSIO_STATUS = int
HIST_SAXI_MODE_ADDR_REL = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
BUFFER_DEPTH32__TYPE = str
CLKIN_PERIOD_AXIHP = int
CMPRS_CBIT_CMODE_JPEG18 = int
MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
HISTOGRAM_RADDR0__TYPE = str
LOGGER_CONF_SYN_BITS = int
......@@ -545,9 +544,9 @@ CMPRS_HIFREQ_REG_BASE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
DQTRI_LAST__TYPE = str
MULTICLK_DIVCLK__TYPE = str
DLY_DQ_ODELAY = long
BUF_IPCLK_SENS1__TYPE = str
FFCLK0_IFD_DELAY_VALUE__TYPE = str
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
HISPI_IOSTANDARD__TYPE = str
......@@ -567,7 +566,7 @@ GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str
SENSI2C_CMD_ACIVE_EARLY0 = int
CMPRS_CSAT_CB__RAW = str
CMD_PAUSE_BITS = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
HISPI_IOSTANDARD__RAW = str
......@@ -587,7 +586,7 @@ DQSTRI_LAST__RAW = str
WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int
MULT_SAXI_CNTRL_ADDR = int
FFCLK1_IBUF_LOW_PWR = str
MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
CMPRS_CBIT_CMODE_MONO4__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
......@@ -610,7 +609,7 @@ CMPRS_AFIMUX_RADDR0__RAW = str
CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
FFCLK1_DQS_BIAS__TYPE = str
SENS_REFCLK_FREQUENCY__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
......@@ -625,14 +624,13 @@ SENS_LENS_ADDR_MASK__RAW = str
SENS_CTRL_QUADRANTS__RAW = str
RTC_MASK__RAW = str
SENS_LENS_ADDR_MASK__TYPE = str
FFCLK0_IFD_DELAY_VALUE__RAW = str
SENS_LENS_AX__TYPE = str
PXD_DRIVE__TYPE = str
HIST_SAXI_NRESET = int
MULT_SAXI_HALF_BRAM_IN__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
DFLT_DQM_PATTERN__RAW = str
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
......@@ -641,24 +639,24 @@ REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str
CMPRS_CBIT_DCSUB__TYPE = str
DFLT_INV_CLK_DIV__TYPE = str
PHASE_CLK2X_XCLK__TYPE = str
MEMBRIDGE_WIDTH64__TYPE = str
SENS_GAMMA_MODE_BAYER__RAW = str
MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
CMPRS_CBIT_FOCUS_BITS__TYPE = str
STATUS_ADDR__RAW = str
NUM_CYCLES_30__TYPE = str
HISPI_MMCM1__TYPE = str
SDCLK_PHASE__RAW = str
SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE = str
SENSI2C_CMD_RUN__RAW = str
FFCLK1_IFD_DELAY_VALUE__RAW = str
SENS_GAMMA_MODE_WIDTH__TYPE = str
MCNTRL_TILED_STARTADDR__TYPE = str
DLY_LD_MASK = int
MCONTR_LINTILE_BYTE32 = int
NUM_CYCLES_09__RAW = str
SENS_SYNC_LBITS__RAW = str
MEMBRIDGE_SIZE64__TYPE = str
LOGGER_STATUS_MASK__TYPE = str
SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
......@@ -671,7 +669,6 @@ SENS_JTAG_TMS = int
MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_PS_EN_RST__TYPE = str
BUF_CLK1X_PCLK2X__TYPE = str
FFCLK1_IFD_DELAY_VALUE__TYPE = str
MCNTRL_TILED_CHN4_ADDR = int
MCONTR_SENS_INC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
......@@ -701,7 +698,6 @@ NUM_CYCLES_01 = int
NUM_CYCLES_02 = int
NUM_CYCLES_03 = int
SENSIO_ADDR_MASK__TYPE = str
DIVCLK_DIVIDE_XCLK = int
NUM_CYCLES_08 = int
NUM_CYCLES_09 = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
......@@ -725,7 +721,6 @@ CMPRS_CBIT_RUN_ENABLE = int
INITIALIZE_OFFSET = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
CMPRS_CSAT_CB = int
CLKFBOUT_MULT_AXIHP__TYPE = str
VERBOSE = int
DLY_LANE1_ODELAY = long
LOGGER_PERIOD__RAW = str
......@@ -734,7 +729,6 @@ SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str
RTC_BITC_PREDIV = int
SENS_SS_MOD_PERIOD__TYPE = str
BUF_CLK1X_SYNC__RAW = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
MEMBRIDGE_LEN64__RAW = str
......@@ -755,6 +749,7 @@ CMPRS_JP4__RAW = str
CMPRS_HIFREQ_REG_BASE__RAW = str
SS_MOD_PERIOD = int
MCONTR_CMPRS_BASE__TYPE = str
FFCLK1_IBUF_LOW_PWR = str
HISPI_CAPACITANCE__TYPE = str
TEST01_SUSPEND__TYPE = str
SENS_LENS_POST_SCALE = int
......@@ -770,11 +765,10 @@ CMPRS_AFIMUX_MASK = int
DLY_PHASE = int
CONTROL_RBACK_DEPTH__RAW = str
MCONTR_LINTILE_NRESET__RAW = str
CLKOUT_DIV_XCLK2X__RAW = str
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MCNTRL_SCANLINE_MASK = int
CLKOUT_DIV_XCLK2X = int
MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
CLKFBOUT_MULT__RAW = str
......@@ -800,7 +794,7 @@ LD_DLY_LANE0_ODELAY__RAW = str
PXD_CLK_DIV_BITS__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMDSEQMUX_ADDR = int
CLKOUT_DIV_AXIHP = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR = int
DLY_DQS_IDELAY__RAW = str
......@@ -817,6 +811,7 @@ SENS_LENS_FAT0_OUT__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
MULTICLK_DIV_XCLK__TYPE = str
SENS_SYNC_LATE_DFLT = int
SENSI2C_STATUS_REG_BASE__RAW = str
AFI_LO_ADDR64__RAW = str
......@@ -827,8 +822,10 @@ DEBUG_LOAD__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
TILE_HEIGHT__RAW = str
MULTICLK_PHASE_SYNC = float
MEMBRIDGE_MODE__RAW = str
SENSI2C_TBL_SA_BITS__RAW = str
HISPI_MMCM3__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
READ_BLOCK_OFFSET__RAW = str
HISTOGRAM_LEFT_TOP__TYPE = str
......@@ -838,6 +835,7 @@ LOGGER_CONF_IMU = int
DLY_DQS_IDELAY = long
HISTOGRAM_WIDTH_HEIGHT__TYPE = str
TEST01_NEXT_PAGE = int
MULTICLK_DIV_XCLK = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
PXD_IBUF_LOW_PWR = str
NUM_CYCLES_17__TYPE = str
......@@ -850,7 +848,6 @@ CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
HISPI_IFD_DELAY_VALUE__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
CLKOUT_DIV_SYNC = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
......@@ -863,14 +860,15 @@ SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
BUF_IPCLK_SENS3__RAW = str
CLK_STATUS__RAW = str
MULTICLK_BUF_AXIHP = str
FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
SENS_CTRL_RST_MMCM = int
HISPI_DQS_BIAS__TYPE = str
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
CMPRS_CSAT_CB__TYPE = str
CMDSEQMUX_STATUS = int
HISPI_MMCM0__TYPE = str
TILE_WIDTH = int
GPIO_MASK = int
DLY_LANE0_ODELAY = long
......@@ -893,7 +891,7 @@ MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
CHNBUF_READ_LATENCY__TYPE = str
CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str
RTC_MHZ__RAW = str
HISPI_MMCM1__RAW = str
TEST_INITIAL_BURST__TYPE = str
NUM_CYCLES_19__RAW = str
MCNTRL_PS_MASK__RAW = str
......@@ -909,18 +907,20 @@ SENS_GAMMA_MODE_WIDTH__RAW = str
PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
DIVCLK_DIVIDE_AXIHP__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
SENS_SYNC_RADDR = int
T_RFC__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
SENSI2C_REL_RADDR__RAW = str
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
MULTICLK_MULT__TYPE = str
SS_EN__TYPE = str
CMDSEQMUX_STATUS = int
SENSI2C_TBL_RNWREG__TYPE = str
FRAME_START_ADDRESS_INC = int
TILED_STARTY = int
......@@ -932,11 +932,9 @@ CAMSYNC_PRE_MAGIC__RAW = str
PXD_CLK_DIV_BITS = int
SENSOR_CHN_EN_BIT = int
LD_DLY_LANE0_ODELAY = int
FFCLK1_IBUF_DELAY_VALUE__RAW = str
CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
SENSI2C_CMD_TAND = int
MEMBRIDGE_SIZE64 = int
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int
......@@ -950,9 +948,9 @@ CAMSYNC_MASTER_BIT__TYPE = str
HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MULTICLK_DIV_DLYREF__RAW = str
VERBOSE__TYPE = str
BUF_CLK1X_PCLK__TYPE = str
BUF_CLK1X_AXIHP__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
CLKFBOUT_MULT_PCLK__RAW = str
MCONTR_SENS_STATUS_INC__TYPE = str
......@@ -964,6 +962,7 @@ MCNTRL_TILED_WINDOW_WH = int
CMDFRAMESEQ_MASK = int
CLK_ADDR = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MULTICLK_PHASE_FB = float
NUM_XFER_BITS__RAW = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
CMPRS_CSAT_CB_BITS__RAW = str
......@@ -977,6 +976,8 @@ GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP46__RAW = str
MULTICLK_DIV_SYNC__TYPE = str
MULTICLK_BUF_DLYREF__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_FBITS__RAW = str
......@@ -992,7 +993,7 @@ NUM_CYCLES_02__TYPE = str
MCNTRL_TILED_STARTADDR = int
TILE_HEIGHT__TYPE = str
MCNTRL_TILED_CHN4_ADDR__TYPE = str
CMPRS_JP4 = int
HISPI_NUMLANES__TYPE = str
TILED_STARTX__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
......@@ -1003,10 +1004,11 @@ SLEW_CMDA = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str
CMPRS_CBIT_CMODE_JPEG18 = int
CONTROL_RBACK_ADDR = int
T_REFI__RAW = str
MULTICLK_PHASE_SYNC__RAW = str
CLKFBOUT_MULT_SENSOR = int
HISPI_MMCM2__RAW = str
CMPRS_AFIMUX_EN = int
COLADDR_NUMBER = int
MCNTRL_TILED_STARTADDR__RAW = str
......@@ -1014,10 +1016,14 @@ TABLE_FOCUS_INDEX__TYPE = str
CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str
MULTICLK_PHASE_AXIHP__RAW = str
FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
TILED_KEEP_OPEN__RAW = str
MULTICLK_BUF_XCLK__RAW = str
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str
MCONTR_SENS_BASE = int
......@@ -1028,7 +1034,6 @@ STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
BUF_CLK1X_XCLK2X__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
SENSI2C_TBL_NBRD__TYPE = str
......@@ -1060,7 +1065,6 @@ SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
FFCLK1_IBUF_DELAY_VALUE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
MAX_TILE_WIDTH = int
NUM_CYCLES_09__TYPE = str
......@@ -1087,6 +1091,7 @@ NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENS_SYNC_MINBITS = int
MULTICLK_BUF_DLYREF = str
MCNTRL_SCANLINE_WINDOW_STARTXY = int
BUF_IPCLK_SENS2__RAW = str
CMPRS_STATUS_CNTRL__TYPE = str
......@@ -1094,6 +1099,7 @@ MCONTR_RD_MASK = int
CMPRS_COLOR_SATURATION = int
NUM_CYCLES_21__RAW = str
NEWPAR__RAW = str
MULTICLK_PHASE_DLYREF__RAW = str
SENSIO_DELAYS__RAW = str
CMDFRAMESEQ_RUN_BIT = int
SENS_SYNC_MINPER = int
......@@ -1117,7 +1123,6 @@ CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
DEBUG_CMD_LATENCY__TYPE = str
FFCLK1_IBUF_DELAY_VALUE__TYPE = str
TILED_KEEP_OPEN = int
MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str
......@@ -1133,12 +1138,13 @@ MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
GPIO_SET_PINS = int
CMPRS_FRMT_LMARG__RAW = str
SENSOR_CHN_EN_BIT__TYPE = str
LOGGER_BIT_DURATION = int
CAMSYNC_MODE__TYPE = str
......@@ -1157,7 +1163,6 @@ PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str
HISPI_NUMLANES__TYPE = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
......@@ -1168,7 +1173,7 @@ MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
LOGGER_PERIOD__TYPE = str
WSEL = int
SENS_REFCLK_FREQUENCY__RAW = str
LOGGER_STATUS_MASK__TYPE = str
MEMBRIDGE_SIZE64__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
......@@ -1186,7 +1191,6 @@ RTC_SET_CORR__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ__RAW = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
FFCLK0_IBUF_DELAY_VALUE = str
CLK_STATUS = int
GPIO_ADDR__RAW = str
MEMBRIDGE_START64__TYPE = str
......@@ -1209,6 +1213,7 @@ HIST_SAXI_NRESET__RAW = str
CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MULTICLK_DIV_AXIHP__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str
......@@ -1250,7 +1255,6 @@ SENS_GAMMA_MODE_REPET__RAW = str
SENSOR_DATA_WIDTH = int
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
SLEW_DQS__TYPE = str
DIVCLK_DIVIDE_AXIHP = int
SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int
SCANLINE_STARTX = int
......@@ -1273,7 +1277,6 @@ CMPRS_CBIT_RUN_STANDALONE__TYPE = str
TILED_STARTX__RAW = str
WRITE_BLOCK_OFFSET__TYPE = str
SENS_SYNC_LATE_DFLT__TYPE = str
BUF_CLK1X_SYNC__TYPE = str
CAMSYNC_MODE = int
CLK_MASK__TYPE = str
MCNTRL_SCANLINE_STARTADDR = int
......@@ -1283,12 +1286,10 @@ MULT_SAXI_HALF_BRAM_IN__TYPE = str
DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
CLKOUT_DIV_XCLK = int
WINDOW_X0__RAW = str
FRAME_START_ADDRESS = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
DIVCLK_DIVIDE_SYNC = int
CMPRS_GROUP_ADDR = int
LOGGER_CONF_GPS_BITS__TYPE = str
SENS_LENS_AX_MASK__TYPE = str
......@@ -1308,7 +1309,8 @@ MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
MEMBRIDGE_WIDTH64__TYPE = str
MULTICLK_DIV_AXIHP__TYPE = str
HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
DLY_PHASE__TYPE = str
......@@ -1318,16 +1320,17 @@ BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
FFCLK0_IFD_DELAY_VALUE = str
SENSI2C_TBL_NABRD = int
SLEW_CMDA__TYPE = str
NUM_CYCLES_19__TYPE = str
CMPRS_CORING_MODE__RAW = str
MEMBRIDGE_ADDR = int
CMPRS_CSAT_CR_BITS__RAW = str
MULTICLK_IN_PERIOD__RAW = str
CMPRS_CBIT_FOCUS = int
FFCLK1_CAPACITANCE__TYPE = str
SENSOR_FIFO_DELAY = int
MULTICLK_PHASE_AXIHP = float
MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
WBUF_DLY_DFLT = int
SENS_JTAG_PROG = int
......@@ -1340,13 +1343,13 @@ DEBUG_MASK__RAW = str
MEMBRIDGE_ADDR__RAW = str
CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
MULTICLK_IN_PERIOD__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
MCONTR_LINTILE_SKIP_LATE = int
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
RTC_SEC_USEC_ADDR__TYPE = str
BUF_CLK1X_XCLK__RAW = str
WINDOW_X0__TYPE = str
CMPRS_CBIT_QBANK_BITS = int
MCNTRL_TEST01_CHN1_MODE = int
......@@ -1360,7 +1363,6 @@ CMPRS_CBIT_RUN_RST__RAW = str
TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str
WSEL__RAW = str
CLKOUT_DIV_XCLK__TYPE = str
SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
......@@ -1376,7 +1378,6 @@ MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
CLKOUT_DIV_AXIHP__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
......@@ -1404,12 +1405,11 @@ MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str
CLKFBOUT_USE_FINE_PS__TYPE = str
CMPRS_FRMT_LMARG = int
FFCLK0_IBUF_DELAY_VALUE__TYPE = str
CMPRS_AFIMUX_EN__RAW = str
CMPRS_TIMEOUT__RAW = str
MEMCLK_IBUF_LOW_PWR__RAW = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENSI2C_CMD_FIFO_RD__RAW = str
CMPRS_STATUS_REG_INC__TYPE = str
RTC_ADDR__TYPE = str
SENSI2C_ABS_RADDR = int
PXD_IOSTANDARD__RAW = str
......@@ -1423,7 +1423,6 @@ DLY_DM_ODELAY__TYPE = str
SENSIO_CTRL = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
CLKIN_PERIOD_SYNC__RAW = str
SCANLINE_STARTY__RAW = str
GPIO_ADDR = int
SENS_SYNC_MINBITS__RAW = str
......@@ -1444,7 +1443,6 @@ TABLE_FOCUS_INDEX__RAW = str
SENSOR_MODE_WIDTH__TYPE = str
MCONTR_LINTILE_WRITE__RAW = str
MCNTRL_TILED_CHN2_ADDR__RAW = str
CLKFBOUT_MULT_XCLK__RAW = str
CMPRS_CONTROL_REG__TYPE = str
SENS_CTRL_ARST__TYPE = str
CMPRS_CBIT_FOCUS__RAW = str
......@@ -1452,15 +1450,14 @@ CMPRS_MONO8__TYPE = str
NUM_CYCLES_00__RAW = str
IPCLK_PHASE__RAW = str
SENSI2C_CTRL = int
MEMCLK_IBUF_DELAY_VALUE__RAW = str
SENS_SYNC_MULT = int
CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
MCNTRL_TILED_TILE_WHS = int
CLKOUT_DIV_XCLK__RAW = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
DLY_LANE1_DQS_WLV_IDELAY = long
MULTICLK_PHASE_DLYREF = float
HIST_SAXI_ADDR_REL = int
CMDFRAMESEQ_ADDR_BASE = int
CMPRS_AFIMUX_RADDR1 = int
......@@ -1472,13 +1469,10 @@ MCONTR_TOP_0BIT_ADDR = int
NUM_CYCLES_05__RAW = str
MEMBRIDGE_MODE = int
MCNTRL_TILED_FRAME_LAST__TYPE = str
MCONTR_LINTILE_DIS_NEED = int
MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
BUF_CLK1X_SYNC = str
TABLE_CORING_INDEX__RAW = str
SENSI2C_CMD_RESET__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
ADDRESS_NUMBER = int
......@@ -1513,10 +1507,12 @@ BUFFER_DEPTH32__RAW = str
DIVCLK_DIVIDE__RAW = str
MCNTRL_PS_CMD__RAW = str
CAMSYNC_ADDR__RAW = str
CLKFBOUT_MULT_SYNC__RAW = str
MCONTR_BUF3_WR_ADDR = int
SENS_NUM_SUBCHN__TYPE = str
REFRESH_OFFSET__RAW = str
HISPI_MMCM0 = str
HISPI_MMCM3 = str
HISPI_MMCM2 = str
MULT_SAXI_CNTRL_ADDR__TYPE = str
MULT_SAXI_STATUS_REG__TYPE = str
MEMCLK_IOSTANDARD__TYPE = str
......@@ -1526,7 +1522,6 @@ CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str
MEMCLK_IFD_DELAY_VALUE__RAW = str
SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str
SENS_SYNC_MASK__RAW = str
......@@ -1535,7 +1530,10 @@ SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENSI2C_DRIVE = int
NUM_CYCLES_04__RAW = str
SENS_GAMMA_HEIGHT2__RAW = str
SENSI2C_SLEW = str
HISPI_DELAY_CLK0 = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK3 = str
MULT_SAXI_BSLOG0__TYPE = str
DQTRI_FIRST__RAW = str
DIVCLK_DIVIDE__TYPE = str
......@@ -1543,6 +1541,7 @@ WBUF_DLY_WLV = int
MCONTR_BUF3_WR_ADDR__RAW = str
MEMBRIDGE_WIDTH64 = int
MCNTRL_TEST01_CHN3_MODE = int
MULTICLK_DIV_DLYREF = int
TABLE_HUFFMAN_INDEX__RAW = str
LD_DLY_PHASE__RAW = str
TEST_INITIAL_BURST__RAW = str
......@@ -1562,11 +1561,11 @@ DEFAULT_STATUS_MODE__TYPE = str
HISTOGRAM_LEFT_TOP = int
PHASE_CLK2X_PCLK = float
GPIO_SLEW__RAW = str
MULTICLK_PHASE_DLYREF__TYPE = str
TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str
CMPRS_AFIMUX_SA_LEN__RAW = str
BUF_IPCLK2X_SENS0__RAW = str
CLKIN_PERIOD_SYNC = int
MCONTR_BUF4_WR_ADDR__RAW = str
CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str
......@@ -1579,7 +1578,7 @@ LOGGER_CONFIG__TYPE = str
MCNTRL_TEST01_MASK = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
CMPRS_AFIMUX_EN__RAW = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str
NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str
......@@ -1591,7 +1590,6 @@ MCONTR_PHY_16BIT_EXTRA__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MAX_TILE_HEIGHT__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
FFCLK0_DQS_BIAS__TYPE = str
HISTOGRAM_WIDTH_HEIGHT__RAW = str
WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
......@@ -1613,7 +1611,6 @@ MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
CAMSYNC_MASTER_BIT = int
CLKFBOUT_MULT_REF__RAW = str
DLY_LD_MASK__RAW = str
CMDFRAMESEQ_RST_BIT__TYPE = str
LD_DLY_LANE1_ODELAY = int
......@@ -1621,13 +1618,13 @@ CMPRS_AFIMUX_MASK__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
CLKIN_PERIOD_SYNC__TYPE = str
CLKFBOUT_DIV_REF = int
SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
HISPI_IFD_DELAY_VALUE__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
MULTICLK_BUF_AXIHP__TYPE = str
GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
......@@ -1637,7 +1634,6 @@ TILED_STARTY__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str
MEMCLK_IFD_DELAY_VALUE__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
......@@ -1655,16 +1651,15 @@ CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
CAMSYNC_TRIG_DST__RAW = str
CLKIN_PERIOD_XCLK__TYPE = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str
FRAME_START_ADDRESS__RAW = str
IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
HIST_SAXI_MODE_ADDR_REL__RAW = str
CLKOUT_DIV_XCLK2X__TYPE = str
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
SENSI2C_TBL_NBWR_BITS = int
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS3 = str
......@@ -1672,6 +1667,7 @@ BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS1 = str
LOGGER_CONFIG = int
DLY_LD__RAW = str
HISPI_MMCM3__TYPE = str
NUM_CYCLES_12__TYPE = str
MCONTR_LINTILE_EXTRAPG = int
MEMCLK_IOSTANDARD = str
......@@ -1681,7 +1677,6 @@ SENSI2C_STATUS_REG_REL = int
MULT_SAXI_HALF_BRAM__TYPE = str
SENSOR_CTRL_ADDR_MASK = int
NUM_CYCLES_16__TYPE = str
DIVCLK_DIVIDE_XCLK__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
CMDFRAMESEQ_MASK__RAW = str
SENS_CTRL_LD_DLY__TYPE = str
......@@ -1705,14 +1700,15 @@ CMPRS_CBIT_FRAMES_SINGLE = int
SENS_SYNC_LATE = int
CMDFRAMESEQ_CTRL__RAW = str
SENSIO_DELAYS = int
MULTICLK_BUF_SYNC = str
MCONTR_BUF0_RD_ADDR__TYPE = str
CLKIN_PERIOD_XCLK__RAW = str
CMPRS_STATUS_REG_INC__TYPE = str
DLY_LANE0_IDELAY__TYPE = str
MCNTRL_PS_ADDR__TYPE = str
WINDOW_WIDTH__RAW = str
MULTICLK_MULT__RAW = str
MCONTR_PHY_16BIT_ADDR__RAW = str
SENS_CTRL_MRST__RAW = str
BUF_CLK1X_XCLK = str
SENS_GAMMA_HEIGHT2__TYPE = str
IPCLK2X_PHASE__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR = int
......@@ -1738,6 +1734,7 @@ CAMSYNC_SNDEN_BIT__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str
CONTROL_ADDR_MASK = int
......@@ -1809,6 +1806,7 @@ SENS_JTAG_TCK__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
LOGGER_BIT_DURATION__RAW = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
......@@ -1817,12 +1815,10 @@ SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
SS_MODE__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
CLKOUT_DIV_SYNC__TYPE = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
SENSIO_RADDR__RAW = str
......@@ -1832,7 +1828,6 @@ MCLK_PHASE = float
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
BUF_CLK1X_XCLK__TYPE = str
MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
......@@ -1861,7 +1856,7 @@ CMDFRAMESEQ_DEPTH__TYPE = str
DLY_LANE0_IDELAY__RAW = str
TABLE_CORING_INDEX__TYPE = str
HISTOGRAM_RADDR1__RAW = str
CLKFBOUT_DIV_REF__TYPE = str
SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str
......@@ -1870,7 +1865,6 @@ MCONTR_BUF3_RD_ADDR__RAW = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
BUF_CLK1X_XCLK2X__TYPE = str
LOGGER_CONF_GPS_BITS = int
NUM_CYCLES_07__RAW = str
CLKFBOUT_PHASE = float
......@@ -1882,7 +1876,6 @@ SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
HISPI_DQS_BIAS__RAW = str
FFCLK1_DQS_BIAS = str
MCONTR_LINTILE_WRITE = int
TILE_VSTEP__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
......@@ -1907,7 +1900,7 @@ STATUS_PSHIFTER_RDY_MASK = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENS_LENS_C_MASK__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
CLKFBOUT_DIV_REF__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
......@@ -1932,7 +1925,6 @@ SENS_JTAG_PROG__TYPE = str
TILE_VSTEP = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
CAMSYNC_EN_BIT__RAW = str
BUF_CLK1X_AXIHP = str
SENSIO_WIDTH = int
MCONTR_PHY_0BIT_DLY_RST__RAW = str
BUF_CLK1X_PCLK2X__RAW = str
......@@ -1948,11 +1940,11 @@ MCNTRL_TEST01_ADDR__TYPE = str
CMPRS_STATUS_REG_BASE = int
MCONTR_LINTILE_NRESET = int
CMPRS_CBIT_RUN_BITS = int
MEMCLK_IFD_DELAY_VALUE = str
SENS_LENS_AY_MASK = int
BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MEMBRIDGE_LEN64 = int
HISPI_MMCM2__TYPE = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
RTC_SET_SEC = int
......@@ -1963,20 +1955,19 @@ CMPRS_MONO16 = int
REF_JITTER1 = float
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
CLKIN_PERIOD_AXIHP__RAW = str
MCONTR_LINTILE_DIS_NEED = int
SENS_LENS_BX_MASK = int
DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
SENS_JTAG_TMS__TYPE = str
FFCLK1_IOSTANDARD = str
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
MULT_SAXI_BSLOG2__TYPE = str
TILED_STARTX = int
MEMBRIDGE_MASK__TYPE = str
FFCLK1_DQS_BIAS__RAW = str
SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
NUM_CYCLES_28__TYPE = str
......@@ -1989,9 +1980,10 @@ SENS_GAMMA_BUFFER = int
CMDFRAMESEQ_ABS__TYPE = str
NUM_CYCLES_06__RAW = str
SENS_JTAG_TDI = int
CLKFBOUT_MULT_AXIHP = int
CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = long
MCNTRL_PS_CMD = int
......@@ -2000,8 +1992,8 @@ MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
GPIO_SLEW = str
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
SENSI2C_REL_RADDR = int
......@@ -2015,20 +2007,18 @@ CAMSYNC_TRIG_SRC__TYPE = str
SENSI2C_CMD_FIFO_RD = int
LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
PHASE_CLK2X_XCLK__RAW = str
SENS_LENS_AY__RAW = str
SS_EN = str
CLKFBOUT_MULT_XCLK = int
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ARO__RAW = str
BUF_IPCLK2X_SENS0__TYPE = str
MULTICLK_BUF_SYNC__RAW = str
MCONTR_PHY_0BIT_DLY_SET__RAW = str
CLKIN_PERIOD_XCLK = int
NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str
......@@ -2055,24 +2045,24 @@ CMPRS_BASE_INC__TYPE = str
SENSI2C_CMD_ACIVE__TYPE = str
NUM_FRAME_BITS__TYPE = str
CLKFBOUT_MULT_SENSOR__TYPE = str
CLKFBOUT_MULT_REF__TYPE = str
SENSI2C_TBL_SA = int
SENSI2C_CTRL_MASK__RAW = str
CLK_CNTRL = int
SENSI2C_TBL_NABRD__RAW = str
BUF_CLK1X_AXIHP__RAW = str
MULTICLK_PHASE_XCLK = float
LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
CLKOUT_DIV_AXIHP__RAW = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MULTICLK_IN_PERIOD = int
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
MULTICLK_PHASE_FB__RAW = str
TABLE_HUFFMAN_INDEX__TYPE = str
RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str
MEMCLK_IBUF_DELAY_VALUE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int
......@@ -2083,7 +2073,7 @@ MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int
CMPRS_AFIMUX_REG_ADDR0__RAW = str
CMPRS_FRMT_LMARG__RAW = str
GPIO_SET_PINS = int
NUM_CYCLES_22__TYPE = str
DLY_PHASE__RAW = str
MCONTR_SENS_INC__RAW = str
......@@ -2092,7 +2082,6 @@ TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
RTC_MASK = int
CLKIN_PERIOD_SENSOR = float
MEMCLK_IBUF_DELAY_VALUE__TYPE = str
SENS_GAMMA_CTRL__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
SENS_CTRL_ARST = int
......@@ -2102,7 +2091,6 @@ CMDFRAMESEQ_DEPTH__RAW = str
SENS_LENS_BX_MASK__RAW = str
SENSI2C_TBL_NBWR_BITS__RAW = str
WRITE_BLOCK_OFFSET__RAW = str
FFCLK0_DQS_BIAS__RAW = str
MCONTR_LINTILE_SINGLE__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
SENS_GAMMA_BUFFER__TYPE = str
......@@ -2110,8 +2098,8 @@ SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int
MCNTRL_PS_MASK__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
HISPI_DELAY_CLK3__TYPE = str
MCONTR_LINTILE_BYTE32__TYPE = str
FFCLK1_IFD_DELAY_VALUE = str
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
FRAME_START_ADDRESS__TYPE = str
......@@ -2127,7 +2115,6 @@ NUM_CYCLES_05__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR__TYPE = str
AXI_WR_ADDR_BITS = int
CLKFBOUT_MULT_XCLK__TYPE = str
FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
......@@ -2140,10 +2127,10 @@ RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
SENS_BANDWIDTH = str
MEMCLK_IBUF_LOW_PWR = str
HISPI_DELAY_CLK3__RAW = str
CAMSYNC_TRIG_DST__TYPE = str
CMPRS_AFIMUX_RADDR1__TYPE = str
MCONTR_PHY_STATUS_CNTRL__TYPE = str
SENS_LENS_AY__RAW = str
MULT_SAXI_WLOG = int
DLY_CMDA_ODELAY__RAW = str
SENSOR_GROUP_ADDR__TYPE = str
......@@ -2173,6 +2160,7 @@ CMPRS_CBIT_CMODE_MONO1 = int
CMPRS_CBIT_CMODE_MONO6 = int
SENS_SS_EN = str
CMPRS_CBIT_CMODE_MONO4 = int
HISPI_DELAY_CLK2__RAW = str
SS_MOD_PERIOD__TYPE = str
TILE_HEIGHT = int
MULT_SAXI_MASK__RAW = str
......
py393/x393_cmprs.py
View file @ 81da483f
......@@ -301,6 +301,7 @@ class X393Cmprs(object):
tile_height= 18
base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = disable_need,
repetitive= True,
single = False,
......
py393/x393_jpeg.py
View file @ 81da483f
......@@ -819,6 +819,27 @@ class X393Jpeg(object):
ff d9
"""
"""
cd /usr/local/verilog/; test_mcntrl.py @hargs
measure_all "*DI"
setup_all_sensors True None 0xf
write_sensor_i2c 0 1 0 0x030600b4
print_sensor_i2c 0 0x306 0xff 0x10 0
print_sensor_i2c 0 0x303a 0xff 0x10 0
print_sensor_i2c 0 0x301a 0xff 0x10 0
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x31c68402
print_sensor_i2c 0 0x31c6 0xff 0x10 0
write_sensor_i2c 0 1 0 0x301a001c
print_sensor_i2c 0 0x31c6 0xff 0x10 0
#test pattern - 100% color bars
write_sensor_i2c 0 1 0 0x30700003
#test pattern - fadiong color bars
write_sensor_i2c 0 1 0 0x30700003
print_sensor_i2c 0 0x3070 0xff 0x10 0
Camera compressors testing sequence
cd /usr/local/verilog/; test_mcntrl.py @hargs
#or (for debug)
......@@ -1001,6 +1022,10 @@ jpeg_write "img.jpeg" all
write_sensor_i2c 0 1 0 0x91900004
print_sensor_i2c 0
print_debug 0x8 0xb
#Set "MSB first"and packet mode
write_sensor_i2c 0 1 0 0x31c60402
#r
add hwmon:
......@@ -1019,5 +1044,9 @@ root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8
root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8007100.ps7-xadc/vccint
966
write_sensor_i2c 0 1 0 0xff200000
print_sensor_i2c 0
"""
py393/x393_mcntrl.py
View file @ 81da483f
......@@ -40,7 +40,8 @@ __status__ = "Development"
#import time
import vrlg
def func_encode_mode_scan_tiled (disable_need = False,
def func_encode_mode_scan_tiled (skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
reset_frame = False,
......@@ -52,6 +53,7 @@ def func_encode_mode_scan_tiled (disable_need = False,
chn_reset = False):
"""
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
@param disable_need - disable 'need' generation, only 'want' (compressor channels),
@param repetitive - run repetitive frames (add this to older 'master' tests)
@param single - run single frame
......@@ -66,17 +68,18 @@ def func_encode_mode_scan_tiled (disable_need = False,
"""
rslt = 0;
rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_EN # inverted
rslt |= (0,1)[enable] << vrlg.MCONTR_LINTILE_NRESET
rslt |= (0,1)[write_mem] << vrlg.MCONTR_LINTILE_WRITE
rslt |= (extra_pages & ((1 << vrlg.MCONTR_LINTILE_EXTRAPG_BITS) - 1)) << vrlg.MCONTR_LINTILE_EXTRAPG
rslt |= (0,1)[keep_open] << vrlg.MCONTR_LINTILE_KEEP_OPEN
rslt |= (0,1)[byte32] << vrlg.MCONTR_LINTILE_BYTE32
rslt |= (0,1)[reset_frame] << vrlg.MCONTR_LINTILE_RST_FRAME
rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_EN # inverted
rslt |= (0,1)[enable] << vrlg.MCONTR_LINTILE_NRESET
rslt |= (0,1)[write_mem] << vrlg.MCONTR_LINTILE_WRITE
rslt |= (extra_pages & ((1 << vrlg.MCONTR_LINTILE_EXTRAPG_BITS) - 1)) << vrlg.MCONTR_LINTILE_EXTRAPG
rslt |= (0,1)[keep_open] << vrlg.MCONTR_LINTILE_KEEP_OPEN
rslt |= (0,1)[byte32] << vrlg.MCONTR_LINTILE_BYTE32
rslt |= (0,1)[reset_frame] << vrlg.MCONTR_LINTILE_RST_FRAME
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[single] << vrlg.MCONTR_LINTILE_SINGLE
rslt |= (0,1)[repetitive] << vrlg.MCONTR_LINTILE_REPEAT
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
return rslt
'''
......
py393/x393_mcntrl_membridge.py
View file @ 81da483f
......@@ -308,6 +308,7 @@ class X393McntrlMembridge(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_tests.py
View file @ 81da483f
......@@ -290,6 +290,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -442,6 +443,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -556,6 +558,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -698,6 +701,7 @@ class X393McntrlTests(object):
0) # chn_reset
'''
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_mcntrl_timing.py
View file @ 81da483f
......@@ -64,7 +64,8 @@ class X393McntrlTiming(object):
fSDCLK=fVCO/CLKOUT1_DIVIDE
tSDCLK=1000.0/fSDCLK # in ns
phaseStep=1000.0/(fVCO*56.0) # 1 unit of phase shift (now 112 for the full period
fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
# fREF=fCLK_IN*vrlg.CLKFBOUT_MULT_REF/vrlg.CLKFBOUT_DIV_REF
fREF=fCLK_IN*vrlg.MULTICLK_MULT/vrlg.MULTICLK_DIV_DLYREF/vrlg.MULTICLK_DIVCLK
dlyStep=1000.0/fREF/32/2 # Approximate, depending on calibration
dlyFStep=0.01 # fine step
return{"SDCLK_PERIOD":tSDCLK,
......
py393/x393_sens_cmprs.py
View file @ 81da483f
......@@ -68,6 +68,15 @@ GLBL_MEMBRIDGE_END = None
GLBL_BUFFER_END = None
GLBL_WINDOW = None
SENSOR_INTERFACE_PARALLEL = "PAR12"
SENSOR_INTERFACE_HISPI = "HISPI"
# for now - single sensor type per interface
SENSOR_INTERFACES={SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}
SENSOR_DEFAULTS= {SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100},
SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
class X393SensCmprs(object):
DRY_MODE = True # True
DEBUG_MODE = 1
......@@ -132,33 +141,96 @@ class X393SensCmprs(object):
global BUFFER_ADDRESS, BUFFER_LEN
return BUFFER_ADDRESS + BUFFER_LEN
def setSensorClock(self, freq_MHz = 24.0):
def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS", quiet = 0):
"""
Set up external clock for sensor-synchronous circuitry (and sensor(s) themselves.
Currently required clock frequency is 1/4 of the sensor clock, so it is 24MHz for 96MHz sensor
@param freq_MHz - input clock frequency (MHz). Currently for 96MHZ sensor clock it should be 24.0
@param freq_MHz - input clock frequency (MHz). Currently for 96MHZ sensor clock it should be 24.0
@param iface - one of the supported interfaces
(see ls /sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070/output_drivers)
@param quiet - reduce output
"""
with open ( SI5338_PATH + "/output_drivers/2V5_LVDS", "w") as f:
with open ( SI5338_PATH + "/output_drivers/" + iface, "w") as f:
print("2", file = f)
with open ( SI5338_PATH + "/output_clocks/out2_freq_fract","w") as f:
print("%d"%(round(1000000*freq_MHz)), file = f )
def setSensorPower(self, sub_pair=0, power_on=0):
if quiet == 0:
print ("Set sensor clock to %f MHz, driver type \"%s\""%(freq_MHz,iface))
def setSensorPower(self, sub_pair=0, power_on=0, quiet=0):
"""
@param sub_pair - pair of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4
@param power_on - 1 - power on, 0 - power off (both sensor power and interface/FPGA bank voltage)
@param quiet - reduce output
"""
if quiet == 0:
print (("vcc_sens01 vp33sens01", "vcc_sens23 vp33sens23")[sub_pair]+" -> "+POWER393_PATH + "/channels_"+ ("dis","en")[power_on])
with open (POWER393_PATH + "/channels_"+ ("dis","en")[power_on],"w") as f:
print(("vcc_sens01 vp33sens01", "vcc_sens23 vp33sens23")[sub_pair], file = f)
def setSensorIfaceVoltage(self, sub_pair, voltage_mv, quiet = 0):
"""
Set interface voltage (should be done before power is on)
@param sub_pair - pair of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4
@param voltage_mv - desired interface voltage (1800..2800 mv)
@param quiet - reduce output
"""
with open (POWER393_PATH + "/voltages_mv/"+ ("vcc_sens01", "vcc_sens23")[sub_pair],"w") as f:
print(voltage_mv, file = f)
if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1)
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
"""
Set interface voltage and turn on power for interface and the sensors
@param sub_pair - pair of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4
@param voltage_mv - desired interface voltage (1800..2800 mv)
@param quiet - reduce output
"""
self.setSensorPower(sub_pair = sub_pair, power_on = 0)
time.sleep(0.2)
self.setSensorIfaceVoltage(sub_pair=sub_pair, voltage_mv = voltage_mv)
time.sleep(0.2)
with open (POWER393_PATH + "/channels_en","w") as f:
print(("vcc_sens01", "vcc_sens23")[sub_pair], file = f)
if quiet == 0:
print ("Turned on interface power %f V for sensors %s"%(voltage_mv*0.001,("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
with open (POWER393_PATH + "/channels_en","w") as f:
print(("vp33sens01", "vp33sens23")[sub_pair], file = f)
if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
def getSensorInterfaceType(self):
"""
Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
@return "PAR12" or "HISPI"
"""
return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def setupSensorsPowerClock(self,quiet=0):
"""
Set interface voltage for all sensors, clock for frequency and sensor power
for the interface matching bitstream file
"""
ifaceType = self.getSensorInterfaceType();
if quiet == 0:
print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType))
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
self.setSensorClock(freq_MHz = SENSOR_INTERFACES[ifaceType]["freq"], iface = SENSOR_INTERFACES[ifaceType]["iface"])
# def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS"):
def setup_sensor_channel (self,
exit_step = None,
num_sensor = 0,
# histogram_start_phys_page, # Calculate from?
# frame_full_width, # 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width = 2592, # 2592
window_height = 1944, # 1944
window_left = 0, # 0
window_top = 0, # 0? 1?
window_width = None, # 2592, # 2592
window_height = None, # 1944, # 1944
window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1?
# compressor_left_margin = 0, #0?`1?
# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?
# frame_start_address_inc,
......@@ -166,10 +238,10 @@ class X393SensCmprs(object):
colorsat_blue = 0x180, # 0x90 fo 1x
colorsat_red = 0x16c, # 0xb6 for x1
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 1935, #0,
histogram_left = None, # 0,
histogram_top = None, # 0,
histogram_width_m1 = None, # 2559, #0,
histogram_height_m1 = None, # 1935, #0,
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -203,6 +275,29 @@ class X393SensCmprs(object):
@return True if all done, False if exited prematurely through exit_step
"""
# @param compressor_left_margin - 0..31 - left margin for compressor (to the nearest 32-byte column)
sensorType = self.getSensorInterfaceType()
if verbose > 0 :
print ("Sensor port %d interface type: %s"%(num_sensor, sensorType))
if window_width is None:
window_width = SENSOR_DEFAULTS[sensorType]["width"]
if window_height is None:
window_height = SENSOR_DEFAULTS[sensorType]["height"]
if window_left is None:
window_left = SENSOR_DEFAULTS[sensorType]["left"]
if window_top is None:
window_top = SENSOR_DEFAULTS[sensorType]["top"]
#setting up histogram window, same for parallel, similar for serial
if histogram_left is None:
histogram_left = 0
if histogram_top is None:
histogram_top = 0
if histogram_width_m1 is None:
histogram_width_m1 = window_width - 33
if histogram_height_m1 is None:
histogram_height_m1 = window_height - 9
align_to_bursts = 64 # align full width to multiple of align_to_bursts. 64 is the size of memory access
width_in_bursts = window_width >> 4
......@@ -479,11 +574,23 @@ class X393SensCmprs(object):
trig = False)
return True
def specify_window (self,
window_width = 2592, # 2592
window_height = 1944, # 1944
window_left = 0, # 0
window_top = 0, # 0? 1?
window_width = None, # 2592
window_height = None, # 1944
window_left = None, # 0
window_top = None, # 0? 1?
verbose = 1
):
sensorType = self.getSensorInterfaceType()
if verbose > 0 :
print ("Sensor interface type: %s"%(sensorType))
if window_width is None:
window_width = SENSOR_DEFAULTS[sensorType]["width"]
if window_height is None:
window_height = SENSOR_DEFAULTS[sensorType]["height"]
if window_left is None:
window_left = SENSOR_DEFAULTS[sensorType]["left"]
if window_top is None:
window_top = SENSOR_DEFAULTS[sensorType]["top"]
global GLBL_WINDOW
GLBL_WINDOW = {"width": window_width,
"height": window_height,
......@@ -526,23 +633,19 @@ class X393SensCmprs(object):
exit_step = None,
sensor_mask = 0x1, # channel 0 only
gamma_load = False,
# histogram_start_phys_page, # Calculate from?
# frame_full_width, # 13-bit Padded line length (8-row increment), in 8-bursts (16 bytes)
window_width = 2592, # 2592
window_height = 1944, # 1944
window_left = 0, # 0
window_top = 0, # 0? 1?
window_width = None, # 2592, # 2592
window_height = None, # 1944, # 1944
window_left = None, # 0, # 0
window_top = None, # 0, # 0? 1?
compressor_left_margin = 0, #0?`1?
# frame_start_address, # calculate through num_sensor, num frames, frame size and start addr?
# frame_start_address_inc,
last_buf_frame = 1, # - just 2-frame buffer
colorsat_blue = 0x180, # 0x90 fo 1x
colorsat_red = 0x16c, # 0xb6 for x1
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 799, #0,
histogram_left = None,
histogram_top = None,
histogram_width_m1 = None, # 2559, #0,
histogram_height_m1 = None, # 799, #0,
circbuf_chn_size= 0x1000000, #16777216
verbose = 1):
"""
......@@ -580,19 +683,40 @@ class X393SensCmprs(object):
@param histogram_width_m1 - one less than window width. If 0 - use frame right margin (end of HACT)
@param histogram_height_m1 - one less than window height. If 0 - use frame bottom margin (end of VACT)
@param circbuf_chn_size - circular buffer size for each channel, in bytes
@parame verbose - verbose level
@param verbose - verbose level
@return True if all done, False if exited prematurely by exit_step
"""
global GLBL_CIRCBUF_CHN_SIZE, GLBL_CIRCBUF_STARTS, GLBL_CIRCBUF_END, GLBL_MEMBRIDGE_START, GLBL_MEMBRIDGE_END, GLBL_BUFFER_END, GLBL_WINDOW
# camsync_setup (
# 4'hf ); # sensor_mask); #
sensorType = self.getSensorInterfaceType()
if verbose > 0 :
print ("Sensor interface type: %s"%(sensorType))
if window_width is None:
window_width = SENSOR_DEFAULTS[sensorType]["width"]
if window_height is None:
window_height = SENSOR_DEFAULTS[sensorType]["height"]
if window_left is None:
window_left = SENSOR_DEFAULTS[sensorType]["left"]
if window_top is None:
window_top = SENSOR_DEFAULTS[sensorType]["top"]
#setting up histogram window, same for parallel, similar for serial
if histogram_left is None:
histogram_left = 0
if histogram_top is None:
histogram_top = 0
if histogram_width_m1 is None:
histogram_width_m1 = window_width - 33
if histogram_height_m1 is None:
histogram_height_m1 = window_height - 1145
self.specify_phys_memory(circbuf_chn_size = circbuf_chn_size)
self.specify_window (window_width = window_width,
window_height = window_height,
window_left = window_left,
window_top = window_top)
window_top = window_top,
verbose = 0)
#TODO: calculate addresses/lengths
"""
......@@ -628,7 +752,11 @@ class X393SensCmprs(object):
membridge_start = GLBL_MEMBRIDGE_START,
membridge_end = GLBL_MEMBRIDGE_END,
verbose = verbose)
# if verbose >0 :
# print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
# self.setSensorPower(sub_pair=0, power_on=0)
"""
if sensor_mask & 3: # Need power for sens1 and sens 2
if verbose >0 :
print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
......@@ -640,6 +768,10 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== Sensor clock setup 24MHz (will output 96MHz) =========================")
self.setSensorClock(freq_MHz = 24.0)
"""
if verbose >0 :
print ("===================== Set up sensor and interface power, clock generator =========================")
self.setupSensorsPowerClock(quiet = (verbose >0))
if exit_step == 1: return False
if verbose >0 :
print ("===================== GPIO_SETUP =========================")
......@@ -735,6 +867,9 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== I2C_SETUP =========================")
slave_addr = SENSOR_DEFAULTS[sensorType]["slave"]
i2c_delay= SENSOR_DEFAULTS[sensorType]["i2c_delay"]
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = True,
......@@ -745,40 +880,75 @@ class X393SensCmprs(object):
active_sda = True,
early_release_0 = True,
verbose = verbose)
if sensorType == SENSOR_INTERFACE_PARALLEL:
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0,
slave_addr = slave_addr,
rah = 0,
num_bytes = 3,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 1,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
# aliases for indices 0x90 and 0x91
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0x90,
slave_addr = slave_addr,
rah = 0,
num_bytes = 3,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 0x91,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd ( #for compatibility with HiSPi mode, last page for read
num_sensor = num_sensor,
page = 0xff,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 1,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
# aliases for indices 0x90 and 0x91
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0x90,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 0x91,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
elif sensorType == SENSOR_INTERFACE_HISPI:
for page in (0,1,2,3,4,5,6, # SMIA configuration registers
0x10,0x11,0x12,0x13,0x14, # SMIA limit registers
0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, # Manufacturer registers
0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e):
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = page,
slave_addr = slave_addr,
rah = page,
num_bytes = 4,
bit_delay = i2c_delay,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd ( # last page used for read
num_sensor = num_sensor,
page = 0xff,
two_byte_addr = 1,
num_bytes_rd = 2,
bit_delay = i2c_delay,
verbose = verbose)
else:
raise ("Unknown sensor type: %s"%(sensorType))
# Turn off reset (is it needed?)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
......@@ -953,6 +1123,7 @@ class X393SensCmprs(object):
Setup video memory
"""
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = False,
disable_need = False,
repetitive= True,
single = False,
......@@ -1023,9 +1194,9 @@ class X393SensCmprs(object):
("sensor_channel3_i", "sensor_channel"),
("histogram_saxi_i", "histogram_saxi")),
"sensor_channel":(("sens_histogram0_i", "sens_histogram"),
("sens_histogram1_i", "sens_histogram"),
("sens_histogram2_i", "sens_histogram"),
("sens_histogram3_i", "sens_histogram"),
# ("sens_histogram1_i", "sens_histogram"),
# ("sens_histogram2_i", "sens_histogram"),
# ("sens_histogram3_i", "sens_histogram"),
("debug_line_cntr", 16),
("debug_lines", 16),
......
py393/x393_sensor.py
View file @ 81da483f
......@@ -262,7 +262,7 @@ class X393Sensor(object):
rslt |= 1 << vrlg.SENSI2C_TBL_RNWREG # this is read register command (0 - write register)
if two_byte_addr > 1:
two_byte_addr = 1
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_SA
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_NABRD
rslt |= (num_bytes_rd & ((1 << vrlg.SENSI2C_TBL_NBRD_BITS) - 1)) << vrlg.SENSI2C_TBL_NBRD
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
return rslt
......@@ -474,6 +474,8 @@ class X393Sensor(object):
verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, td)
if verbose > 1:
print ("ta= 0x%x, td = 0x%x"%(ta,td))
def write_sensor_i2c (self,
num_sensor,
......@@ -495,7 +497,7 @@ class X393Sensor(object):
sent for such extra word, only the lower bytes are sent.
2 - register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
read address in teh table is programmed to be a single-byte one
read address in the table is programmed to be a single-byte one
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1057,6 +1059,7 @@ class X393Sensor(object):
"""
base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = True,
disable_need = False,
repetitive= True,
single = False,
......
py393/x393_utils.py
View file @ 81da483f
......@@ -96,6 +96,10 @@ class X393Utils(object):
"""
if bitfile is None:
bitfile=DEFAULT_BITFILE
print ("Sensor ports power off")
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
......
sensor/sens_10398.v
View file @ 81da483f
......@@ -271,7 +271,7 @@ module sens_10398 #(
// generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
always @(posedge pclk) begin
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2) -1;
else pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;
// treat MSB separately to make 50% duty cycle
if (prst) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= 0;
......
sensor/sensor_channel.v
View file @ 81da483f
......@@ -462,13 +462,30 @@ module sensor_channel#(
`ifdef DEBUG_RING
reg vact_to_fifo_r;
// reg vact_to_fifo_r;
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
`ifdef HISPI
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact;
if (sof) debug_line_cntr <= 0;
else if (hact && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
if (prst) hact_cntr <= 0;
else if (hact && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end
`else
always @(posedge ipclk) begin
vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact_to_fifo;
......@@ -485,6 +502,7 @@ module sensor_channel#(
else if (vact_to_fifo && !vact_to_fifo_r) vact_cntr <= vact_cntr + 1;
end
`endif
debug_slave #(
.SHIFT_WIDTH (128),
.READ_WIDTH (128),
......@@ -501,7 +519,12 @@ module sensor_channel#(
// .rd_data ({6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0], debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
.rd_data ({
lens_pxd_in, gamma_pxd_in[15:0],
pxd_to_fifo[11:0],pxd[11:0],gamma_pxd_out[7:0],
`ifdef HISPI
12'b0,
`else
pxd_to_fifo[11:0],
`endif
pxd[11:0],gamma_pxd_out[7:0],
6'b0,hist_grant,hist_request, hist_gr[3:0], hist_rq[3:0], hact_cntr[15:0],
debug_lines[15:0], debug_line_cntr[15:0]}), // input[31:0]
......
status_read.v
View file @ 81da483f
......@@ -94,7 +94,10 @@ module status_read#(
assign axird_rdata=axi_status_rdata_r;
assign axird_selected = select_r;
initial begin
ram [DATA_2DEPTH] = FPGA_VERSION;
ram [DATA_2DEPTH] = FPGA_VERSION;
`ifdef HISPI
ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor
`endif
end
always @ (posedge axi_clk) begin
if (arst) select_r <= 0;
......
system_defines.vh
View file @ 81da483f
......@@ -41,7 +41,7 @@
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
`define DEBUG_RING 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
......
x393_testbench03.sav
View file @ 81da483f
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Nov 8 07:30:39 2015
[*] Tue Nov 10 02:42:47 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151107210810890.fst"
[dumpfile_mtime] "Sun Nov 8 04:40:36 2015"
[dumpfile_size] 202201184
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151108002110369.fst"
[dumpfile_mtime] "Sun Nov 8 07:54:16 2015"
[dumpfile_size] 250548392
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0
[timestart] 62721200
[size] 1823 1180
[pos] 1920 0
*-25.279701 81782497 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-15.279701 62772842 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -35,12 +35,14 @@
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
......@@ -63,7 +65,7 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 445
[sst_width] 233
[signals_width] 348
[sst_expanded] 1
[sst_vpaned_height] 514
......@@ -86,6 +88,17 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.rst_mmcm
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.pxd_clk_cntr[3:0]
@1001200
-group_end
@200
-
@c00200
-sens_hispi12l4
@28
......@@ -637,6 +650,8 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-sens_hispi_lane0
@1401200
-sens_hispi12l4
@29
x393_testbench03.ffclk0p
@200
-
@1000200
......@@ -1026,7 +1041,7 @@ x393_testbench03.simul_sensor12bits_i.c
x393_testbench03.simul_sensor12bits_i.state[3:0]
@28
x393_testbench03.simul_sensor12bits_i.stoppedd
@23
@22
x393_testbench03.simul_sensor12bits_i.cntrd[15:0]
@200
-
......
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