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Commit 7b13989a authored by Andrey Filippov's avatar Andrey Filippov
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more bugs fixing with simulation

parent 943fc4a1
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includes/x393_parameters.vh
View file @ 7b13989a
......@@ -103,7 +103,7 @@
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
includes/x393_tasks_pio_sequences.vh
View file @ 7b13989a
......@@ -98,7 +98,7 @@ task set_write_block;
cmd_addr <= MCONTR_CMD_WR_ADDR + WRITE_BLOCK_OFFSET;
// activate
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// see if pause is needed . See when buffer read should be started - maybe before WR command
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......@@ -115,15 +115,23 @@ task set_write_block;
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining writes
for (i = 1; i < 63; i = i + 1) begin
for (i = 1; i < 62; i = i + 1) begin
// write
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// One last write pair w/o buffer
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0],3,1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0);
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
......
memctrl/cmd_encod_linear_rd.v
View file @ 7b13989a
......@@ -74,7 +74,7 @@ module cmd_encod_linear_rd #(
reg [NUM_XFER_BITS-1:0] num128; // number of 128-bit words to transfer
reg skip_next_page;
reg gen_run;
reg gen_run_d;
// reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -82,7 +82,7 @@ module cmd_encod_linear_rd #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
......@@ -94,8 +94,8 @@ module cmd_encod_linear_rd #(
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
......@@ -136,19 +136,20 @@ module cmd_encod_linear_rd #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
bank[2:0], // bank (here OK to be any)
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -178,7 +179,7 @@ module cmd_encod_linear_rd #(
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
......
memctrl/cmd_encod_linear_wr.v
View file @ 7b13989a
This diff is collapsed.
memctrl/cmd_encod_tiled_32_rd.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_32_rd #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_32_rd #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -162,8 +162,8 @@ module cmd_encod_tiled_32_rd #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -247,18 +247,19 @@ module cmd_encod_tiled_32_rd #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -282,7 +283,7 @@ module cmd_encod_tiled_32_rd #(
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
3'b0, // bank (here OK to be any)
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -295,6 +296,7 @@ module cmd_encod_tiled_32_rd #(
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/cmd_encod_tiled_32_wr.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_32_wr #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_32_wr #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -169,8 +169,8 @@ module cmd_encod_tiled_32_wr #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -233,7 +233,7 @@ module cmd_encod_tiled_32_wr #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) ; // here does not matter, just to work with masked ACTIVATE
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
......@@ -245,27 +245,29 @@ module cmd_encod_tiled_32_wr #(
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'hf: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d; *****
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -290,7 +292,7 @@ module cmd_encod_tiled_32_wr #(
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done // end of sequence ****
3'b0, // bank (here OK to be any)
rom_r[ENC_ODT], // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -304,6 +306,7 @@ module cmd_encod_tiled_32_wr #(
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/cmd_encod_tiled_rd.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_rd #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_rd #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -162,8 +162,8 @@ module cmd_encod_tiled_rd #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -242,18 +242,19 @@ module cmd_encod_tiled_rd #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -277,7 +278,7 @@ module cmd_encod_tiled_rd #(
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
3'b0, // bank (here OK to be any)
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -290,6 +291,7 @@ module cmd_encod_tiled_rd #(
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/cmd_encod_tiled_wr.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_wr #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_wr #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -136,12 +136,12 @@ module cmd_encod_tiled_wr #(
wire [FULL_ADDR_NUMBER-1:0] row_col_bank_next_w; // RA,CA, BA - valid @pre_act;
reg cut_buf_rd;
// reg cut_buf_rd;
always @ (posedge clk) begin
if (!gen_run) cut_buf_rd <= 0;
else if ((gen_addr==(LOOP_LAST-1)) && !loop_continue) cut_buf_rd <= 1;
end
// always @ (posedge clk) begin
// if (!gen_run) cut_buf_rd <= 0;
// else if ((gen_addr==(LOOP_LAST-1)) && loop_continue) cut_buf_rd <= 1; //*******
// end
assign row_col_bank_next_w= last_row?
{top_rc,bank}: // can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile)
......@@ -169,8 +169,8 @@ module cmd_encod_tiled_wr #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -233,7 +233,7 @@ module cmd_encod_tiled_wr #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) ; // here does not matter, just to work with masked ACTIVATE
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
......@@ -243,7 +243,7 @@ module cmd_encod_tiled_wr #(
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
......@@ -252,17 +252,17 @@ module cmd_encod_tiled_wr #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run || gen_run; // gen_run_d; *****
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -281,12 +281,12 @@ module cmd_encod_tiled_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
3'b0, // bank (here OK to be any)
rom_r[ENC_ODT], // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -296,9 +296,10 @@ module cmd_encod_tiled_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/mcntrl393.v
View file @ 7b13989a
......@@ -103,7 +103,7 @@ module mcntrl393 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
memctrl/memctrl16.v
View file @ 7b13989a
......@@ -86,7 +86,7 @@ module memctrl16 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
memctrl/phy/mcontr_sequencer.v
View file @ 7b13989a
......@@ -482,7 +482,7 @@ module mcontr_sequencer #(
always @ (posedge mclk) begin
if (buf_wr) mem_read_mode <= 1; // last was buf_wr, not buf_rd
if (buf_wr_ndly) mem_read_mode <= 1; // last was buf_wr, not buf_rd
else if (buf_rd) mem_read_mode <= 0;
end
......
util_modules/mcont_from_chnbuf_reg.v
View file @ 7b13989a
......@@ -22,7 +22,7 @@
module mcont_from_chnbuf_reg #(
parameter CHN_NUMBER=0,
parameter CHN_LATENCY=1 // 0 - no extra latency in extrenal BRAM - data available next cycle after regen (1 extra from ren)
parameter CHN_LATENCY=2 // 0 - no extra latency in extrenal BRAM - data available next cycle after regen (1 extra from ren)
)(
input rst,
input clk,
......@@ -37,6 +37,7 @@ module mcont_from_chnbuf_reg #(
output reg rpage_nxt,
input [63:0] buf_rdata_chn
);
reg [63:0] buf_rdata_chn_r; /// *** temporary register to delay buffer read data - may be used to implement multi-clock mux to ease timing
reg buf_chn_sel;
reg [CHN_LATENCY:0] latency_reg=0;
always @ (posedge rst or posedge clk) begin
......@@ -58,8 +59,11 @@ module mcont_from_chnbuf_reg #(
end
// always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
// always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
always @ (posedge clk) buf_rdata_chn_r <= buf_rdata_chn; // THIS WILL BE REPLACED BY MULTI-CYCLE MUX
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn_r;
always @ (posedge clk) rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
//buf_rdata_chn_r
endmodule
x393.v
View file @ 7b13989a
......@@ -108,7 +108,7 @@ module x393 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......@@ -360,7 +360,12 @@ module x393 #(
wire [31:0] status_rdata; //
wire status_selected;
wire [31:0] mcntrl_axird_rdata; // read data from the memory controller
wire mcntrl_axird_selected; // memory controoler has valid data output on mcntrl_axird_rdata
reg status_selected_ren; // status_selected (set at axird_start_burst) delayed when ren is active
reg mcntrl_axird_selected_ren; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active
reg status_selected_regen; // status_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
reg mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
wire mclk;
......@@ -375,7 +380,8 @@ module x393 #(
// Use this later
// assign axird_rdata= ({32{status_selected}} & status_rdata[31:0]) | ({32{mcntrl_axird_selected}} & mcntrl_axird_rdata[31:0]);
//Debug with this (to show 'x)
assign axird_rdata= status_selected?status_rdata[31:0] : (mcntrl_axird_selected? mcntrl_axird_rdata[31:0]:'bx);
// assign axird_rdata= status_selected?status_rdata[31:0] : (mcntrl_axird_selected? mcntrl_axird_rdata[31:0]:'bx);
assign axird_rdata= status_selected_regen?status_rdata[31:0] : (mcntrl_axird_selected_regen? mcntrl_axird_rdata[31:0]:'bx);
assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
......@@ -383,6 +389,24 @@ module x393 #(
wire comb_rst=~frst[0] | frst[1];
reg axi_rst_pre=1'b1;
// delay status_selected and mcntrl_axird_selected to match data for multiplexing
always @(posedge axi_rst or posedge axird_bram_rclk) begin
if (axi_rst) status_selected_ren <= 1'b0;
else if (axird_ren) status_selected_ren <= status_selected;
if (axi_rst) status_selected_regen <= 1'b0;
else if (axird_regen) status_selected_regen <= status_selected_ren;
if (axi_rst) mcntrl_axird_selected_ren <= 1'b0;
else if (axird_ren) mcntrl_axird_selected_ren <= mcntrl_axird_selected;
if (axi_rst) mcntrl_axird_selected_regen <= 1'b0;
else if (axird_regen) mcntrl_axird_selected_regen <= mcntrl_axird_selected_ren;
end
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
......
x393_testbench01.sav
View file @ 7b13989a
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x393_testbench01.tf
View file @ 7b13989a
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