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Commit 7b13989a authored by Andrey Filippov's avatar Andrey Filippov
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more bugs fixing with simulation

parent 943fc4a1
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includes/x393_parameters.vh
View file @ 7b13989a
......@@ -103,7 +103,7 @@
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
includes/x393_tasks_pio_sequences.vh
View file @ 7b13989a
......@@ -98,7 +98,7 @@ task set_write_block;
cmd_addr <= MCONTR_CMD_WR_ADDR + WRITE_BLOCK_OFFSET;
// activate
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// see if pause is needed . See when buffer read should be started - maybe before WR command
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......@@ -115,16 +115,24 @@ task set_write_block;
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining writes
for (i = 1; i < 63; i = i + 1) begin
for (i = 1; i < 62; i = i + 1) begin
// write
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// One last write pair w/o buffer
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0],3,1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......
memctrl/cmd_encod_linear_rd.v
View file @ 7b13989a
......@@ -74,7 +74,7 @@ module cmd_encod_linear_rd #(
reg [NUM_XFER_BITS-1:0] num128; // number of 128-bit words to transfer
reg skip_next_page;
reg gen_run;
reg gen_run_d;
// reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -82,7 +82,7 @@ module cmd_encod_linear_rd #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
......@@ -94,8 +94,8 @@ module cmd_encod_linear_rd #(
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
......@@ -136,19 +136,20 @@ module cmd_encod_linear_rd #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
bank[2:0], // bank (here OK to be any)
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -160,7 +161,7 @@ module cmd_encod_linear_rd #(
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
{{ADDRESS_NUMBER-COLADDR_NUMBER{1'b0}},col[COLADDR_NUMBER-4:0],3'b0}, // [14:0] addr; // 15-bit row/column adderss
......@@ -177,9 +178,9 @@ module cmd_encod_linear_rd #(
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
/*
......
memctrl/cmd_encod_linear_wr.v
View file @ 7b13989a
......@@ -22,7 +22,6 @@
`timescale 1ns/1ps
module cmd_encod_linear_wr #(
// parameter BASEADDR = 0,
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
......@@ -32,8 +31,6 @@ module cmd_encod_linear_wr #(
input rst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
// input cmd_stb, // strobe (with first byte) for the command a/d
input [2:0] bank_in, // bank address
input [ADDRESS_NUMBER-1:0] row_in, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column (3 LSBs should be 0?)
......@@ -44,7 +41,7 @@ module cmd_encod_linear_wr #(
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
localparam ROM_WIDTH=13;
localparam ROM_WIDTH=12;
localparam ROM_DEPTH=4;
localparam ENC_NOP= 0;
......@@ -57,13 +54,26 @@ module cmd_encod_linear_wr #(
localparam ENC_PAUSE_SHIFT= 8; // [9:8] - 2- bit pause (for NOP commandes)
localparam ENC_PRE_DONE= 10;
localparam ENC_BUF_PGNEXT= 11;
localparam ENC_DUAL_CYC= 12; // 2-cycle command (with nop or skip) to count number of buffer reads (longer pauses are not used with buffer reads)
localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
localparam ENC_CMD_WRITE= 1;
localparam ENC_CMD_PRECHARGE=2;
localparam ENC_CMD_ACTIVATE= 3;
localparam REPEAT_ADDR=4;
// read buffer is always at addr 0 and 1,
localparam REPEAT_ADDR= 5; // loop here (2-cycle command write)
localparam PRELAST_WRITE_ADDR='h6; // jump here (from 4) if only 2 writes are needed (are fall from 4 wnen 1 write is left
localparam LAST_WRITE_ADDR= 'h8; // jump here (from 4) if only 2 writes are needed (are fall from 4 wnen 1 write is left
localparam NO_WRITE_ADDR= 'ha; // jump here (from 4) if only 1 write is needed
localparam WRITE_ADDR1= 3;
localparam WRITE_ADDR2= 5;
// localparam WRITE_ADDR3= 6;
// localparam WRITE_ADDR4= 8;
localparam CUT_SINGLE_ADDR= 2; // cut read buffer after this address if only one burst is needed
localparam CUT_DUAL_ADDR= 4; // cut read buffer after this address if two bursts are needed
localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)
localparam CMD_WRITE= 3;
......@@ -77,7 +87,7 @@ module cmd_encod_linear_wr #(
reg skip_next_page;
reg gen_run;
reg gen_run_d;
// reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -85,27 +95,25 @@ module cmd_encod_linear_wr #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg buf_rd_23; // read buffer at steps 2&3 (0 if only 1 read is required)
// reg done;
reg start_d;
// reg [ROM_DEPTH-1:0] gen_addr_jump; // next conditonal address
reg [NUM_XFER_BITS:0] num_bufrd_left; //counts number of buffer reads left
wire [NUM_XFER_BITS:0] num_bufrd_left_next_w; //next clock value of the counter
wire next_zero_w=(num_bufrd_left_next_w==0);
wire next_zero_w= single_write?((gen_addr==CUT_SINGLE_ADDR)?1:0):(dual_write?(gen_addr==CUT_DUAL_ADDR):0);
reg cut_buf_rd;
reg single_write; // only one burst has to be written
reg dual_write; // Two bursts have to be written
reg few_write; //write 1,2 or 3 bursts
wire write_addr_w; // gen_addr that generates write commands
reg [ROM_DEPTH-1:0] jump_gen_addr; // will overrun as stop comes from ROM
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2];
assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
assign full_cmd= rom_cmd[1]?(rom_cmd[0]?CMD_ACTIVATE:CMD_PRECHARGE):(rom_cmd[0]?CMD_WRITE:CMD_NOP);
assign num_bufrd_left_next_w= num_bufrd_left - (rom_r[ENC_DUAL_CYC]?2:1);
// prepare jump address? and bufrd during 2,3
assign write_addr_w= (gen_addr==WRITE_ADDR1) || (gen_addr==WRITE_ADDR2); // do not need to update after WRITE_ADDR2
// make num128 7-bits to accommodate 64!
always @ (posedge clk) begin
start_d <= start;
if (start_d) num_bufrd_left <= {num128[NUM_XFER_BITS-1:0],1'b0};
else if (rom_r[ENC_BUF_RD]) num_bufrd_left <= num_bufrd_left_next_w;
cut_buf_rd <= rom_r[ENC_BUF_RD] && (cut_buf_rd || next_zero_w);
end
always @ (posedge rst or posedge clk) begin
......@@ -114,19 +122,46 @@ module cmd_encod_linear_wr #(
else if (start) gen_run<= 1;
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop
if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(REPEAT_ADDR-1)) && few_write) gen_addr <= jump_gen_addr;
// else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS:1]==0)) gen_addr <= gen_addr+1; // not in a loop
else if ((gen_addr !=REPEAT_ADDR) || (num128==2)) gen_addr <= gen_addr+1; // not in a loop
//counting loops
if (rst) num128 <= 0;
else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};
else if (!gen_run) num128 <= 0; //
else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME
if (rst) num128 <= 0;
else if (start) num128 <= {(num128_in==0)?1'b1:1'b0,num128_in};
else if (!gen_run) num128 <= 0; //
// else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1; // ????? - FIXME
else if (write_addr_w) num128 <= num128 -1;
if (rst) single_write <= 0;
else if (start_d) single_write <= (num128[NUM_XFER_BITS:1]==0); // could not be 0
if (rst) dual_write <= 0;
else if (start_d) dual_write <= (num128==2);
// if (rst) triple_write <= 0;
// else if (start_d) triple_write <= (num128==3);
if (rst) few_write <= 0;
else if (start_d) few_write <=(num128[NUM_XFER_BITS:2]==0); // (0,)1,2 or3
//
// if (rst) few_write <= 0;
// else few_write <= single_write | dual_write | triple_write;
if (rst) jump_gen_addr <= 0;
else jump_gen_addr <= single_write ? NO_WRITE_ADDR : (dual_write ? LAST_WRITE_ADDR:PRELAST_WRITE_ADDR);
//triple_write
// reg single_write; // only one burst has to be written
// reg dual_write; // Two bursts have to be written
end
always @ (posedge clk) if (start) begin
......@@ -146,35 +181,41 @@ module cmd_encod_linear_wr #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DUAL_CYC); // dual cycle
4'h2: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT); // single cycle
4'h3: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);// | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h2: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT); // single cycle
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // single cycle
// next may loop
4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DUAL_CYC); // dual cycle
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'h6: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
4'h5: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h6: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT);
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_SEL) | (1 << ENC_ODT); // dual cycle
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'hc: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
// else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
else if (gen_run) begin
if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
bank[2:0], // bank (here OK to be any)
rom_r[ENC_ODT], // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -186,7 +227,7 @@ module cmd_encod_linear_wr #(
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
{{ADDRESS_NUMBER-COLADDR_NUMBER{1'b0}},col[COLADDR_NUMBER-4:0],3'b0}, // [14:0] addr; // 15-bit row/column adderss
......@@ -203,6 +244,7 @@ module cmd_encod_linear_wr #(
rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
......
memctrl/cmd_encod_tiled_32_rd.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_32_rd #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_32_rd #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -162,8 +162,8 @@ module cmd_encod_tiled_32_rd #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -247,18 +247,19 @@ module cmd_encod_tiled_32_rd #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -280,9 +281,9 @@ module cmd_encod_tiled_32_rd #(
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
3'b0, // bank (here OK to be any)
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -294,7 +295,8 @@ module cmd_encod_tiled_32_rd #(
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/cmd_encod_tiled_32_wr.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_32_wr #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_32_wr #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -169,8 +169,8 @@ module cmd_encod_tiled_32_wr #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -233,7 +233,7 @@ module cmd_encod_tiled_32_wr #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) ; // here does not matter, just to work with masked ACTIVATE
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
......@@ -245,27 +245,29 @@ module cmd_encod_tiled_32_wr #(
4'h8: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
4'ha: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hc: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_AUTOPRE) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hd: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'he: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
4'hf: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d; *****
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -288,9 +290,9 @@ module cmd_encod_tiled_32_wr #(
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done // end of sequence ****
3'b0, // bank (here OK to be any)
rom_r[ENC_ODT], // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -303,7 +305,8 @@ module cmd_encod_tiled_32_wr #(
// rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
end
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/cmd_encod_tiled_rd.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_rd #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_rd #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -162,8 +162,8 @@ module cmd_encod_tiled_rd #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -242,18 +242,19 @@ module cmd_encod_tiled_rd #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -275,9 +276,9 @@ module cmd_encod_tiled_rd #(
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
3'b0, // bank (here OK to be any)
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -289,7 +290,8 @@ module cmd_encod_tiled_rd #(
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/cmd_encod_tiled_wr.v
View file @ 7b13989a
......@@ -104,7 +104,7 @@ module cmd_encod_tiled_wr #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -112,7 +112,7 @@ module cmd_encod_tiled_wr #(
wire [1:0] rom_cmd;
wire [1:0] rom_skip;
wire [2:0] full_cmd;
reg done;
// reg done;
reg [FULL_ADDR_NUMBER-4:0] top_rc; // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
reg first_col;
......@@ -136,12 +136,12 @@ module cmd_encod_tiled_wr #(
wire [FULL_ADDR_NUMBER-1:0] row_col_bank_next_w; // RA,CA, BA - valid @pre_act;
reg cut_buf_rd;
// reg cut_buf_rd;
always @ (posedge clk) begin
if (!gen_run) cut_buf_rd <= 0;
else if ((gen_addr==(LOOP_LAST-1)) && !loop_continue) cut_buf_rd <= 1;
end
// always @ (posedge clk) begin
// if (!gen_run) cut_buf_rd <= 0;
// else if ((gen_addr==(LOOP_LAST-1)) && loop_continue) cut_buf_rd <= 1; //*******
// end
assign row_col_bank_next_w= last_row?
{top_rc,bank}: // can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile)
......@@ -169,8 +169,8 @@ module cmd_encod_tiled_wr #(
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
else gen_run_d <= gen_run;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
......@@ -233,7 +233,7 @@ module cmd_encod_tiled_wr #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) ; // here does not matter, just to work with masked ACTIVATE
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
4'h2: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT);
......@@ -243,7 +243,7 @@ module cmd_encod_tiled_wr #(
4'h6: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h7: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
// end loop
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'h9: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_DQS_TOGGLE);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT);
......@@ -252,17 +252,17 @@ module cmd_encod_tiled_wr #(
endcase
end
always @ (posedge rst or posedge clk) begin
if (rst) done <= 0;
else done <= pre_done;
// if (rst) done <= 0;
// else done <= pre_done;
if (rst) enc_wr <= 0;
else enc_wr <= gen_run || gen_run_d;
else enc_wr <= gen_run || gen_run; // gen_run_d; *****
if (rst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run_d;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
else if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
{{ADDRESS_NUMBER-COLADDR_NUMBER-1{1'b0}},
......@@ -281,12 +281,12 @@ module cmd_encod_tiled_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_skip ( // encode pause
else enc_cmd <= func_encode_skip ( // encode pause
{{CMD_PAUSE_BITS-2{1'b0}},rom_skip[1:0]}, // skip; // number of extra cycles to skip (and keep all the other outputs)
done, // end of sequence
pre_done, // done, // end of sequence
3'b0, // bank (here OK to be any)
rom_r[ENC_ODT], // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -296,9 +296,10 @@ module cmd_encod_tiled_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT] && !skip_next_page);// buf_rst; // connect to external buffer (but only if not paused)
end
end
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
......
memctrl/mcntrl393.v
View file @ 7b13989a
......@@ -103,7 +103,7 @@ module mcntrl393 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
memctrl/memctrl16.v
View file @ 7b13989a
......@@ -86,7 +86,7 @@ module memctrl16 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
memctrl/phy/mcontr_sequencer.v
View file @ 7b13989a
......@@ -482,7 +482,7 @@ module mcontr_sequencer #(
always @ (posedge mclk) begin
if (buf_wr) mem_read_mode <= 1; // last was buf_wr, not buf_rd
if (buf_wr_ndly) mem_read_mode <= 1; // last was buf_wr, not buf_rd
else if (buf_rd) mem_read_mode <= 0;
end
......
util_modules/mcont_from_chnbuf_reg.v
View file @ 7b13989a
......@@ -22,7 +22,7 @@
module mcont_from_chnbuf_reg #(
parameter CHN_NUMBER=0,
parameter CHN_LATENCY=1 // 0 - no extra latency in extrenal BRAM - data available next cycle after regen (1 extra from ren)
parameter CHN_LATENCY=2 // 0 - no extra latency in extrenal BRAM - data available next cycle after regen (1 extra from ren)
)(
input rst,
input clk,
......@@ -37,7 +37,8 @@ module mcont_from_chnbuf_reg #(
output reg rpage_nxt,
input [63:0] buf_rdata_chn
);
reg buf_chn_sel;
reg [63:0] buf_rdata_chn_r; /// *** temporary register to delay buffer read data - may be used to implement multi-clock mux to ease timing
reg buf_chn_sel;
reg [CHN_LATENCY:0] latency_reg=0;
always @ (posedge rst or posedge clk) begin
if (rst) buf_chn_sel <= 0;
......@@ -58,8 +59,11 @@ module mcont_from_chnbuf_reg #(
end
// always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
// always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
always @ (posedge clk) buf_rdata_chn_r <= buf_rdata_chn; // THIS WILL BE REPLACED BY MULTI-CYCLE MUX
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn_r;
always @ (posedge clk) rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
//buf_rdata_chn_r
endmodule
x393.v
View file @ 7b13989a
......@@ -108,7 +108,7 @@ module x393 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......@@ -360,7 +360,12 @@ module x393 #(
wire [31:0] status_rdata; //
wire status_selected;
wire [31:0] mcntrl_axird_rdata; // read data from the memory controller
wire mcntrl_axird_selected; // memory controoler has valid data output on mcntrl_axird_rdata
reg status_selected_ren; // status_selected (set at axird_start_burst) delayed when ren is active
reg mcntrl_axird_selected_ren; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active
reg status_selected_regen; // status_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
reg mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
wire mclk;
......@@ -375,7 +380,8 @@ module x393 #(
// Use this later
// assign axird_rdata= ({32{status_selected}} & status_rdata[31:0]) | ({32{mcntrl_axird_selected}} & mcntrl_axird_rdata[31:0]);
//Debug with this (to show 'x)
assign axird_rdata= status_selected?status_rdata[31:0] : (mcntrl_axird_selected? mcntrl_axird_rdata[31:0]:'bx);
// assign axird_rdata= status_selected?status_rdata[31:0] : (mcntrl_axird_selected? mcntrl_axird_rdata[31:0]:'bx);
assign axird_rdata= status_selected_regen?status_rdata[31:0] : (mcntrl_axird_selected_regen? mcntrl_axird_rdata[31:0]:'bx);
assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
......@@ -383,6 +389,24 @@ module x393 #(
wire comb_rst=~frst[0] | frst[1];
reg axi_rst_pre=1'b1;
// delay status_selected and mcntrl_axird_selected to match data for multiplexing
always @(posedge axi_rst or posedge axird_bram_rclk) begin
if (axi_rst) status_selected_ren <= 1'b0;
else if (axird_ren) status_selected_ren <= status_selected;
if (axi_rst) status_selected_regen <= 1'b0;
else if (axird_regen) status_selected_regen <= status_selected_ren;
if (axi_rst) mcntrl_axird_selected_ren <= 1'b0;
else if (axird_ren) mcntrl_axird_selected_ren <= mcntrl_axird_selected;
if (axi_rst) mcntrl_axird_selected_regen <= 1'b0;
else if (axird_regen) mcntrl_axird_selected_regen <= mcntrl_axird_selected_ren;
end
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
......
x393_testbench01.sav
View file @ 7b13989a
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Mon Feb 23 20:32:53 2015
[*] Wed Feb 25 01:15:51 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150223124353972.lxt"
[dumpfile_mtime] "Mon Feb 23 20:02:26 2015"
[dumpfile_size] 1073748834
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150224165149452.lxt"
[dumpfile_mtime] "Wed Feb 25 00:03:44 2015"
[dumpfile_size] 668213066
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 8460000
[timestart] 60788700
[size] 1823 1180
[pos] 2059 -3
*-23.698502 45624323 55877500 55843010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 2059 0
*-16.698502 60850000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_deser_32bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 285
[signals_width] 402
[sst_width] 235
[signals_width] 428
[sst_expanded] 1
[sst_vpaned_height] 628
@800200
......@@ -43,7 +49,7 @@ x393_testbench01.SIMUL_AXI_FULL[0]
@22
x393_testbench01.SIMUL_AXI_ADDR[15:0]
x393_testbench01.SIMUL_AXI_READ[31:0]
@c00200
@800200
-top_extra
@22
x393_testbench01.NUM_WORDS_READ[31:0]
......@@ -138,7 +144,14 @@ x393_testbench01.x393_i.status_selected[0]
x393_testbench01.x393_i.mcntrl_axird_selected[0]
@22
x393_testbench01.x393_i.mcntrl_axird_rdata[31:0]
@1401200
@200
-
@29
x393_testbench01.x393_i.axird_start_burst[0]
@28
x393_testbench01.x393_i.axird_ren[0]
x393_testbench01.x393_i.axird_regen[0]
@1000200
-top_extra
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mclk[0]
......@@ -214,7 +227,7 @@ x393_testbench01.wait_status_condition.status_mode[1:0]
-WAIT_STATUS_CONDITION
@1000200
-top_simulation
@c00200
@800200
-axi
@28
x393_testbench01.x393_i.axi_aclk[0]
......@@ -286,7 +299,7 @@ x393_testbench01.x393_i.axiwr_wclk[0]
x393_testbench01.x393_i.axiwr_wdata[31:0]
@28
x393_testbench01.x393_i.axiwr_wen[0]
@1401200
@1000200
-axi
@c00200
-cmd_mux
......@@ -345,7 +358,7 @@ x393_testbench01.x393_i.cmd_mux_i.wdata_fifo_out[31:0]
x393_testbench01.x393_i.cmd_mux_i.wr_en[0]
@1401200
-cmd_mux
@c00200
@800200
-status_read
@22
x393_testbench01.x393_i.status_read_i.ad[7:0]
......@@ -379,7 +392,7 @@ x393_testbench01.x393_i.status_read_i.waddr[7:0]
x393_testbench01.x393_i.status_read_i.wdata[31:0]
@28
x393_testbench01.x393_i.status_read_i.we[0]
@1401200
@1000200
-status_read
@c00200
-status_router_top
......@@ -1014,6 +1027,13 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
@1401200
-mcntrl393_test01
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rrun[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd_cur[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.sequence_done[0]
@200
-
-
......@@ -1281,9 +1301,8 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_4mux_i.start_w[0]
@1401200
-enc4mux
@800200
-PS_PIO
@c00200
-PS_PIO
-PS_PIO_STATUS
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.ad[7:0]
......@@ -1375,7 +1394,7 @@ x393_testbench01.x393_i.mcntrl393_i.buf0wr_we[0]
-other_m393
@200
-
@800200
@c00200
-PS_PIO_RD
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.data_in[63:0]
......@@ -1397,11 +1416,11 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0]
@1000200
@1401200
-PS_PIO_RD
@200
-
@800200
@c00200
-PS_PIO_WR
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.data_out[63:0]
......@@ -1423,7 +1442,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1000200
@1401200
-PS_PIO_WR
@200
-
......@@ -1516,9 +1535,9 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0]
@1000200
@1401200
-PS_PIO
@c00200
@800200
-LINEAR_CH1
@200
-
......@@ -1553,7 +1572,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.wd
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.status_generate_i.we[0]
@1401200
-status_gen
@c00200
@800200
-chn1wr
@22
x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.data_out[63:0]
......@@ -1575,9 +1594,9 @@ x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn1wr_buf_i.rpage_set[0]
@1401200
@1000200
-chn1wr
@c00200
@800200
-chn1rd
@22
x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.data_in[63:0]
......@@ -1599,8 +1618,125 @@ x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn1rd_buf_i.wpage_set[0]
@1401200
@1000200
-chn1rd
@c00200
-encod_lin_wr
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.cut_buf_rd[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_r[11:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_wr[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.bank_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.cut_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_cmd[31:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.full_cmd[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.next_zero_w[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128_in[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_cmd[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rom_skip[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.row_in[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.start_d[0]
@1401200
-encod_lin_wr
@800200
-encod_lin_rd
@200
-
@800200
-read_block_buf_chn
@22
x393_testbench01.read_block_buf_chn.chn[3:0]
x393_testbench01.read_block_buf_chn.num_read[31:0]
@28
x393_testbench01.read_block_buf_chn.page[1:0]
@22
x393_testbench01.read_block_buf_chn.start_addr[29:0]
@28
x393_testbench01.read_block_buf_chn.wait_done[0]
@1000200
-read_block_buf_chn
@800200
-debug_buf_wpage_nxt
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_wr[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_wr_ndly[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mem_read_mode[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rst_d[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_wpage_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.buf_wpage_nxt_chn1[0]
@1000200
-debug_buf_wpage_nxt
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.bank_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.full_cmd[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.gen_addr[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.num128[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.num128_in[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rom_cmd[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rom_r[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rom_skip[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.row_in[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start_col[6:0]
@1000200
-encod_lin_rd
@200
-
@c00200
......@@ -1796,10 +1932,609 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
@1401200
@1000200
-LINEAR_CH1
@c00200
-TILED_CH2
-ch2wr
@22
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.data_out[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.raddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2wr_buf_i.rpage_set[0]
@1401200
-ch2wr
@c00200
-ch2rd
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.data_in[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.waddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_set[0]
@1401200
-ch2rd
@c00200
-encod_tiled_wr
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_r[11:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.loop_continue[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_done[0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.bank[2:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.col_bank[9:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enable_autopre[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.first_col[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.last_row[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.next_bank_w[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.next_rowcol_w[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_cols128_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_cols_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_rows_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.num_rows_m1[5:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.pre_write[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_r[11:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rom_skip[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.row_col_bank[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.row_col_bank_next_w[24:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rowcol_inc_in[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.scan_col[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.scan_row[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.start_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_wr_i.top_rc[21:0]
@1401200
-encod_tiled_wr
@c00200
-encod_tiled_rd
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rom_r[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.pre_done[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_done[0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.col_bank[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enable_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enable_autopre[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.first_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.full_cmd[2:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.keep_open_in[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.num_cols_in_m1[5:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.pre_act[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.row_col_bank_next_w[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.rowcol_inc_in[13:0]
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@28
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_col[6:0]
@28
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@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.start_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_16_rw_i.cmd_encod_tiled_rd_i.top_rc[21:0]
@1401200
-encod_tiled_rd
@c00200
-ch2rd
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.data_in[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.ext_regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.waddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn2rd_buf_i.wpage_set[0]
@1401200
-ch2rd
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@c00200
-TILED32_CH4
-ch4wr
@22
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.data_out[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.raddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn4wr_buf_i.rpage_set[0]
@1401200
-ch4wr
@c00200
-ch4rd
@22
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.data_in[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.ext_regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.waddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn4rd_buf_i.wpage_set[0]
@1401200
-ch4rd
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_r[12:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_wr[0]
@800022
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
@28
(29)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
(30)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
(31)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_done[0]
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@200
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@c00200
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@200
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@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.col_bank[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enable_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enable_autopre[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.first_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.full_cmd[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_addr[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.keep_open_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.last_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.last_row[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.loop_continue[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.next_bank_w[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.next_rowcol_w[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_cols128_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_cols_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_rows_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.num_rows_m1[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.pre_write[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_cmd[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rom_r[12:0]
@28
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@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.row_col_bank[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.row_col_bank_next_w[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rowcol_inc_in[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.scan_col[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.scan_row[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_d[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.start_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_wr_i.top_rc[21:0]
@1401200
-encod_tiled_wr32
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rom_r[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_wr[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_done[0]
@200
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@c00200
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@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.col_bank[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enable_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enable_autopre[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.first_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.full_cmd[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_addr[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.keep_open_in[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.last_row[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.loop_continue[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.next_bank_w[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.next_rowcol_w[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_cols128_m2[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_cols_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_rows_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_act[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_read[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.row_col_bank_next_w[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rowcol_inc_in[13:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.rst[0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.scan_col[5:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_bank[2:0]
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x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_d[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.top_rc[21:0]
@1401200
-encod_tiled_rd32
@c00200
-tiled_ch4
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.byte32[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_rst_d[0]
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x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_wrmem[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.continued_tile[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_y[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_finished[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_finished_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width_r[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.i[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.leftover_cols[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.lim_by_tile_width[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_page_left[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished_r0[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished_r1[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mem_page_left[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mode_reg[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.msw_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mul_rslt_w[26:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_page[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1_w[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_r[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1_w[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.page_cntr[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.par_mod_r[8:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pre_want[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.remainder_tile_width[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_left[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rowcol_inc[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_start_addr_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_tile_whs_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_x0y0_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr_r[21:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_not_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.suspend[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_height_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_rows[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_width_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_y0[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_limited_by_mem_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_limited_by_mem_page_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_need[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done_d[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_neg[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_pos[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_row[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start32_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_rd_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_wr_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0]
@1401200
-tiled_ch4
-TILED32_CH4
@c00200
-mmcm_phase_cntr
@28
......@@ -2349,7 +3084,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_in[0]
@1401200
-phy_cmd
@c00200
@800200
-cmd1_buf
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel[0]
......@@ -2358,7 +3093,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause[0]
@800028
@800022
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
......@@ -2383,7 +3118,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.wc
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0]
@1401200
@1000200
-cmd1_buf
@c00200
-max_0001
......
x393_testbench01.tf
View file @ 7b13989a
......@@ -29,19 +29,19 @@
//`define TEST_READ_PATTERN 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
`define TESTL_SHORT_SCANLINE 1
`define TEST_SCANLINE_WRITE 1
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_SCANLINE_READ 1
`define TEST_READ_SHOW 1
`define TEST_TILED_WRITE 1
//`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_TILED_READ 1
//`define TEST_TILED_READ 1
`define TEST_TILED_WRITE32 1
`define TEST_TILED_READ32 1
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
......@@ -232,20 +232,18 @@ module x393_testbench01 #(
//NUM_XFER_BITS=6
localparam SCANLINE_PAGES_PER_ROW= (WINDOW_WIDTH>>NUM_XFER_BITS)+((WINDOW_WIDTH[NUM_XFER_BITS-1:0]==0)?0:1);
localparam TILES_PER_ROW= (WINDOW_WIDTH/TILE_WIDTH)+ ((WINDOW_WIDTH % TILE_WIDTH==0)?0:1);
// localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-TILE_HEIGHT)/TILE_VSTEP) + (((WINDOW_HEIGHT-TILE_HEIGHT)%TILE_VSTEP==0)?0:1) +1;
// localparam TILE_ROWS_PER_WINDOW= (WINDOW_HEIGHT/TILE_VSTEP) + ((WINDOW_HEIGHT%TILE_VSTEP==0)?0:1);
localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-1)/TILE_VSTEP) + 1;
// localparam SCANLINE_PAGES_PER_ROW= (WINDOW_WIDTH>>NUM_XFER_BITS)+((WINDOW_WIDTH[NUM_XFER_BITS-1:0]==0)?0:1);
// localparam TILES_PER_ROW= (WINDOW_WIDTH/TILE_WIDTH)+ ((WINDOW_WIDTH % TILE_WIDTH==0)?0:1);
// localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-1)/TILE_VSTEP) + 1;
localparam TILE_SIZE= TILE_WIDTH*TILE_HEIGHT;
// localparam TILE_SIZE= TILE_WIDTH*TILE_HEIGHT;
// localparam integer SCANLINE_FULL_XFER= 1<<NUM_XFER_BITS; // 64 - full page transfer in 8-bursts
// localparam integer SCANLINE_LAST_XFER= WINDOW_WIDTH % (1<<NUM_XFER_BITS); // last page transfer size in a row
// integer ii;
integer SCANLINE_XFER_SIZE;
// integer SCANLINE_XFER_SIZE;
localparam TEST_INITIAL_BURST= 4; // 3;
always #(CLKIN_PERIOD/2) CLK = ~CLK;
initial begin
......@@ -337,17 +335,83 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`ifdef TEST_READ_BLOCK
test_read_block;
`endif
`ifdef TESTL_SHORT_SCANLINE
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1, // input wait_done;
1, //WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1, // input show_data;
1, // WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1, // input wait_done;
2, //WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1, // input show_data;
2, // WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1, // input wait_done;
3, //WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1, // input show_data;
3, // WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
`endif
`ifdef TEST_SCANLINE_WRITE
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1); // input wait_done;
1, // input wait_done;
WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
`endif
`ifdef TEST_SCANLINE_READ
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1); // input show_data;
1, // input show_data;
WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0);
`endif
`ifdef TEST_TILED_WRITE
......@@ -356,36 +420,64 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
0, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1); // wait_done;
1, // wait_done;
WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0,
TILE_WIDTH,
TILE_HEIGHT,
TILE_VSTEP);
`endif
`ifdef TEST_TILED_READ
test_tiled_read (
2, // [3:0] channel;
0, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1); // show_data;
2, // [3:0] channel;
0, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1, // show_data;
WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0,
TILE_WIDTH,
TILE_HEIGHT,
TILE_VSTEP);
`endif
`ifdef TEST_TILED_WRITE32
test_tiled_write (
4, // 2, // [3:0] channel;
1, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1); // wait_done;
4, // 2, // [3:0] channel;
1, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1, // wait_done;
WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0,
TILE_WIDTH,
TILE_HEIGHT,
TILE_VSTEP);
`endif
`ifdef TEST_TILED_READ32
test_tiled_read (
4, //2, // [3:0] channel;
1, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1); // show_data;
4, //2, // [3:0] channel;
1, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1, // show_data;
WINDOW_WIDTH,
WINDOW_HEIGHT,
WINDOW_X0,
WINDOW_Y0,
TILE_WIDTH,
TILE_HEIGHT,
TILE_VSTEP);
`endif
#20000;
$finish;
end
......@@ -1090,6 +1182,11 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input [1:0] extra_pages;
input wait_done;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
reg [29:0] start_addr;
integer mode;
......@@ -1098,7 +1195,11 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
reg [29:0] test_mode_address;
integer ii;
integer xfer_size;
integer pages_per_row;
integer startx,starty; // temporary - because of the vdt bug with integer ports
begin
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t",
channel, extra_pages, wait_done, $time);
case (channel)
......@@ -1130,8 +1231,8 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
write_contol_register(start_addr+ MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);
configure_channel_priority(channel,0); // lowest priority channel 3
......@@ -1140,25 +1241,27 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
// VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
xfer_size= ((pages_per_row>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
((ii % pages_per_row) < (pages_per_row-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
(window_width % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
({16'b0,window_width}));
$display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
startx=window_left + ((ii % pages_per_row)<<NUM_XFER_BITS);
starty=window_top + (ii / pages_per_row);
write_block_scanline_chn(
channel,
(ii & 3),
SCANLINE_XFER_SIZE,
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);\
xfer_size,
startx, //window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
starty); // window_top + (ii / pages_per_row)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii< (WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW) ;ii = ii+1) begin // here assuming 1 page per line
for (ii=0;ii< (window_height * pages_per_row) ;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
status_address, //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
......@@ -1168,23 +1271,26 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
'hf << 16, // mask for the 4-bit page number
1, // not equal to
(ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
xfer_size= ((pages_per_row>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
((ii % pages_per_row) < (pages_per_row-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
(window_width % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
({16'b0,window_width}));
$display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
startx=window_left + ((ii % pages_per_row)<<NUM_XFER_BITS);
starty=window_top + (ii / pages_per_row);
write_block_scanline_chn(
channel,
(ii & 3),
SCANLINE_XFER_SIZE,
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);
xfer_size,
startx, // window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
starty); // window_top + (ii / pages_per_row)); // SCANLINE_CUR_Y);
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
......@@ -1206,6 +1312,10 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input [1:0] extra_pages;
input show_data;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
reg [29:0] start_addr;
integer mode;
......@@ -1213,7 +1323,11 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
integer xfer_size;
integer pages_per_row;
begin
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_read: channel=%d, extra_pages=%d, show_data=%d @%t",
channel, extra_pages, show_data, $time);
case (channel)
......@@ -1246,23 +1360,23 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
// program to the
write_contol_register(start_addr + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<(WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW);ii = ii+1) begin
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
for (ii=0;ii<(window_height * pages_per_row);ii = ii+1) begin
xfer_size= ((pages_per_row>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
((ii % pages_per_row) < (pages_per_row-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
(window_width % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
({16'b0,window_width}));
wait_status_condition (
status_address, //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
......@@ -1277,7 +1391,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
read_block_buf_chn (
channel,
(ii & 3),
SCANLINE_XFER_SIZE <<2,
xfer_size <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
......@@ -1291,15 +1405,30 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
input keep_open;
input [1:0] extra_pages;
input wait_done;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
input [ 7:0] tile_width;
input [ 7:0] tile_height;
input [ 7:0] tile_vstep;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
integer tiles_per_row;
integer tile_rows_per_window;
integer tile_size;
integer startx,starty; // temporary - because of the vdt bug with integer ports
begin
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height;
$display("====== test_tiled_write: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, wait_done=%d @%t",
channel, byte32, keep_open, extra_pages, wait_done, $time);
case (channel)
......@@ -1332,10 +1461,11 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
0); // chn_reset
write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, {8'b0,tile_vstep,tile_height,tile_width});//tile_width+(tile_height<<8)+(tile_vstep<<16));
write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
......@@ -1343,15 +1473,17 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
$display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
startx = window_left + ((ii % tiles_per_row) * tile_width);
starty = window_top + (ii / tile_rows_per_window); // SCANLINE_CUR_Y);\
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
channel, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
tile_size,
startx, //window_left + ((ii % tiles_per_row) * tile_width),
starty); //window_top + (ii / tile_rows_per_window)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
status_address, // MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
......@@ -1362,12 +1494,14 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
1, // not equal to
(ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
$display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
startx = window_left + ((ii % tiles_per_row) * tile_width);
starty = window_top + (ii / tile_rows_per_window);
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
channel, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
tile_size,
startx, // window_left + ((ii % tiles_per_row) * tile_width),
starty); // window_top + (ii / tile_rows_per_window)); // SCANLINE_CUR_Y);\
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
......@@ -1393,6 +1527,13 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
input keep_open;
input [1:0] extra_pages;
input show_data;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
input [ 7:0] tile_width;
input [ 7:0] tile_height;
input [ 7:0] tile_vstep;
reg [29:0] start_addr;
integer mode;
......@@ -1401,7 +1542,14 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
reg [29:0] test_mode_address;
integer ii;
integer tiles_per_row;
integer tile_rows_per_window;
integer tile_size;
begin
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height;
$display("====== test_tiled_read: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, show_data=%d @%t",
channel, byte32, keep_open, extra_pages, show_data, $time);
case (channel)
......@@ -1434,15 +1582,16 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
0); // chn_reset
write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, {8'b0,tile_vstep,tile_height,tile_width});//(tile_height<<8)+(tile_vstep<<16));
write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
wait_status_condition (
status_address, // MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
......@@ -1456,7 +1605,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
read_block_buf_chn (
channel,
(ii & 3),
TILE_SIZE <<2,
tile_size <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
......
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