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Commit 73fd490f authored by Andrey Filippov's avatar Andrey Filippov
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added implementation reports to git

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------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 4 15:35:18 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42671 | 0 | 78600 | 54.29 |
| LUT as Logic | 39126 | 0 | 78600 | 49.78 |
| LUT as Memory | 3545 | 0 | 26600 | 13.33 |
| LUT as Distributed RAM | 2930 | 0 | | |
| LUT as Shift Register | 615 | 0 | | |
| Slice Registers | 55453 | 0 | 157200 | 35.28 |
| Register as Flip Flop | 55453 | 0 | 157200 | 35.28 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 36 | Yes | - | Set |
| 680 | Yes | - | Reset |
| 962 | Yes | Set | - |
| 53775 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16846 | 0 | 19650 | 85.73 |
| SLICEL | 11074 | 0 | | |
| SLICEM | 5772 | 0 | | |
| LUT as Logic | 39126 | 0 | 78600 | 49.78 |
| using O5 output only | 1 | | | |
| using O6 output only | 30311 | | | |
| using O5 and O6 | 8814 | | | |
| LUT as Memory | 3545 | 0 | 26600 | 13.33 |
| LUT as Distributed RAM | 2930 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2844 | | | |
| LUT as Shift Register | 615 | 0 | | |
| using O5 output only | 341 | | | |
| using O6 output only | 221 | | | |
| using O5 and O6 | 53 | | | |
| LUT Flip Flop Pairs | 25047 | 0 | 78600 | 31.87 |
| fully used LUT-FF pairs | 4757 | | | |
| LUT-FF pairs with one unused LUT output | 18217 | | | |
| LUT-FF pairs with one unused Flip Flop | 17858 | | | |
| Unique Control Sets | 4700 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 85 | 0 | 265 | 32.08 |
| RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 54 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 22 | 22 | 155 | 14.19 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 38 | 38 | 250 | 15.20 |
| IDELAYE2 only | 20 | 20 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 32 | 32 | 163 | 19.63 |
| ISERDES | 32 | 32 | | |
| OLOGIC | 44 | 44 | 163 | 26.99 |
| OUTFF_ODDR_Register | 1 | 1 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL | 14 | 0 | 32 | 43.75 |
| BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 3 | 0 | 5 | 60.00 |
| PLLE2_ADV | 4 | 0 | 5 | 80.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 6 | 0 | 20 | 30.00 |
+--------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 53775 | Flop & Latch |
| LUT3 | 11502 | LUT |
| LUT6 | 10432 | LUT |
| LUT2 | 8513 | LUT |
| LUT4 | 8148 | LUT |
| LUT5 | 7749 | LUT |
| RAMD32 | 4318 | Distributed Memory |
| CARRY4 | 2771 | CarryLogic |
| LUT1 | 1596 | LUT |
| RAMS32 | 1456 | Distributed Memory |
| FDSE | 962 | Flop & Latch |
| FDCE | 680 | Flop & Latch |
| SRL16E | 564 | Distributed Memory |
| SRLC32E | 104 | Distributed Memory |
| DSP48E1 | 76 | Block Arithmetic |
| RAMB18E1 | 62 | Block Memory |
| RAMB36E1 | 54 | Block Memory |
| OBUFT | 53 | IO |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| FDPE | 36 | Flop & Latch |
| IBUF | 35 | IO |
| ISERDESE2 | 32 | IO |
| MUXF7 | 30 | MuxFx |
| OBUF | 23 | IO |
| IBUFDS | 22 | IO |
| IDELAYE2 | 20 | IO |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| PULLUP | 16 | I/O |
| BUFG | 14 | Clock |
| BUFR | 6 | Clock |
| PLLE2_ADV | 4 | Clock |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| MMCME2_ADV | 3 | Clock |
| INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| OBUFTDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| ODDR | 1 | IO |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3495.180 ; gain = 0.000 ; free physical = 27077 ; free virtual = 29422
x393_parallel.timing_summary_impl 0 → 100644
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 4 18:08:08 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_parallel_utilization.report
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
----------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 41675 | 0 | 78600 | 53.02 |
| LUT as Logic | 38288 | 0 | 78600 | 48.71 |
| LUT as Memory | 3387 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2850 | 0 | | |
| LUT as Shift Register | 537 | 0 | | |
| Slice Registers | 53972 | 0 | 157200 | 34.33 |
| Register as Flip Flop | 53972 | 0 | 157200 | 34.33 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 16 | Yes | - | Set |
| 688 | Yes | - | Reset |
| 934 | Yes | Set | - |
| 52334 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16426 | 0 | 19650 | 83.59 |
| SLICEL | 10819 | 0 | | |
| SLICEM | 5607 | 0 | | |
| LUT as Logic | 38288 | 0 | 78600 | 48.71 |
| using O5 output only | 6 | | | |
| using O6 output only | 29749 | | | |
| using O5 and O6 | 8533 | | | |
| LUT as Memory | 3387 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2850 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2764 | | | |
| LUT as Shift Register | 537 | 0 | | |
| using O5 output only | 258 | | | |
| using O6 output only | 228 | | | |
| using O5 and O6 | 51 | | | |
| LUT Flip Flop Pairs | 24311 | 0 | 78600 | 30.93 |
| fully used LUT-FF pairs | 4601 | | | |
| LUT-FF pairs with one unused LUT output | 17639 | | | |
| LUT-FF pairs with one unused Flip Flop | 17425 | | | |
| Unique Control Sets | 4703 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 85 | 0 | 265 | 32.08 |
| RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 54 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 2 | 2 | 155 | 1.29 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 78 | 78 | 250 | 31.20 |
| IDELAYE2 only | 60 | 60 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 72 | 72 | 163 | 44.17 |
| ISERDES | 72 | 72 | | |
| OLOGIC | 48 | 48 | 163 | 29.45 |
| OUTFF_ODDR_Register | 5 | 5 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+--------+
| BUFGCTRL | 14 | 0 | 32 | 43.75 |
| BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 5 | 0 | 5 | 100.00 |
| PLLE2_ADV | 2 | 0 | 5 | 40.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 6 | 0 | 20 | 30.00 |
+--------------+------+-------+-----------+--------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52334 | Flop & Latch |
| LUT3 | 11303 | LUT |
| LUT6 | 10124 | LUT |
| LUT2 | 8405 | LUT |
| LUT4 | 7788 | LUT |
| LUT5 | 7581 | LUT |
| RAMD32 | 4198 | Distributed Memory |
| CARRY4 | 2793 | CarryLogic |
| LUT1 | 1620 | LUT |
| RAMS32 | 1416 | Distributed Memory |
| FDSE | 934 | Flop & Latch |
| FDCE | 688 | Flop & Latch |
| SRL16E | 484 | Distributed Memory |
| OBUFT | 121 | IO |
| SRLC32E | 104 | Distributed Memory |
| IBUF | 99 | IO |
| DSP48E1 | 76 | Block Arithmetic |
| ISERDESE2 | 72 | IO |
| RAMB18E1 | 62 | Block Memory |
| IDELAYE2 | 60 | IO |
| RAMB36E1 | 54 | Block Memory |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 30 | MuxFx |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| PULLUP | 16 | I/O |
| FDPE | 16 | Flop & Latch |
| BUFG | 14 | Clock |
| BUFR | 6 | Clock |
| ODDR | 5 | IO |
| MMCME2_ADV | 5 | Clock |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| OBUF | 3 | IO |
| INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| PLLE2_ADV | 2 | Clock |
| OBUFTDS | 2 | IO |
| IBUFDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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