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Commit 730c34f7 authored by Andrey Filippov's avatar Andrey Filippov
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Fixed dst, verified MCLT through all 4 dct/dst

parent b28376ab
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Showing with 559 additions and 135 deletions
dsp/dct_iv.ods
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dsp/dtt_iv8_1d.v
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......@@ -166,14 +166,22 @@ module dtt_iv8_1d#(
en_out_r2 <= en_out_r;
if (en_out_r2) begin
case (phase_cnt[3:1])
3'h0: y_index <= dst_out_r ? 7 : 0;
3'h1: y_index <= dst_out_r ? 0 : 7;
3'h2: y_index <= dst_out_r ? 3 : 4;
3'h3: y_index <= dst_out_r ? 4 : 3;
3'h4: y_index <= dst_out_r ? 6 : 1;
3'h5: y_index <= dst_out_r ? 1 : 6;
3'h6: y_index <= dst_out_r ? 5 : 2;
3'h7: y_index <= dst_out_r ? 2 : 5;
// 3'h0: y_index <= dst_out_r ? 7 : 0;
// 3'h1: y_index <= dst_out_r ? 0 : 7;
// 3'h2: y_index <= dst_out_r ? 3 : 4;
// 3'h3: y_index <= dst_out_r ? 4 : 3;
// 3'h4: y_index <= dst_out_r ? 6 : 1;
// 3'h5: y_index <= dst_out_r ? 1 : 6;
// 3'h6: y_index <= dst_out_r ? 5 : 2;
// 3'h7: y_index <= dst_out_r ? 2 : 5;
3'h0: y_index <= 0;
3'h1: y_index <= 7;
3'h2: y_index <= 4;
3'h3: y_index <= 3;
3'h4: y_index <= 1;
3'h5: y_index <= 6;
3'h6: y_index <= 2;
3'h7: y_index <= 5;
endcase
end else begin
y_index <= 'bx;
......@@ -197,10 +205,10 @@ module dtt_iv8_1d#(
else if (start || restart) run_in <= 1;
else if (phase_cnt==15) run_in <= 0;
// if (start || restart) dst_pre <= dst_in;
if (start) dst_pre <= dst_in;
if (phase_cnt == 12) dst_2 <= dst_pre;
/// if (phase_cnt == 12) dst_2 <= dst_pre;
if (phase_cnt == 13) dst_2 <= dst_pre;
if (phase_cnt == 14) dst_out_r <= dst_2;
......@@ -287,7 +295,8 @@ module dtt_iv8_1d#(
dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ;
// dsp_neg_m_2 <= p03 | p06 | p12 | p15 ;
dsp_neg_m_2_dct <= p02 | p05 | p11 | p14 ;
dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p12 | p13 | p14 ;
// dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p12 | p13 | p14 ;
dsp_neg_m_2_dst <= p03 | p04 | p10 | p15 ;
dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ;
end
......
dsp/dtt_iv_8x8_ad.v
View file @ 730c34f7
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dsp/mclt16x16.v
View file @ 730c34f7
......@@ -85,6 +85,7 @@ module mclt16x16#(
reg [3:0] bayer_d; // same latency as mpix_a_w
reg [7:0] in_cntr; // input counter
reg [16:0] in_busy;
reg [ 1:0] start_r;
wire [17:0] fold_rom_out;
wire [ 7:0] mpix_a_w = fold_rom_out[ 7:0];
wire [ 3:0] mpix_sgn_w = fold_rom_out[11:8];
......@@ -164,8 +165,9 @@ module mclt16x16#(
y_shft_r <= y_shft;
bayer_r <= bayer;
end
start_r <= {start_r[0], start};
// if (in_busy[2]) begin // same latency as mpix_a_w
if (in_busy[1]) begin // same latency as mpix_a_w
if (start_r[1]) begin // same latency as mpix_a_w
x_shft_r2 <= x_shft_r;
y_shft_r2 <= y_shft_r;
end
......@@ -486,7 +488,8 @@ D11 - negate for mode 3 (SS)
.clk (clk), // input
.rst (rst), // input
.start (dtt_start), // input
.mode (dtt_mode), // input[1:0]
// .mode (dtt_mode), // input[1:0]
.mode ({dtt_mode[0],dtt_mode[1]}), // input[1:0]
.xin (dtt_r_data), // input[24:0] signed
.pre_last_in (), // output reg
.mode_out (), // dtt_mode_out), // output[1:0] reg
......
dsp/mclt_test_01.tf
View file @ 730c34f7
......@@ -98,6 +98,9 @@ module mclt_test_01 ();
reg [WND_WIDTH - 1:0] tiles_wnd[0:1023];
reg [DTT_IN_WIDTH - 1:0] java_dtt_in[0:1023];
reg [DTT_IN_WIDTH - 1:0] java_dtt_out0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_out[0:1023];
integer i, n, n_out;
initial begin
$readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs);
......@@ -121,6 +124,11 @@ module mclt_test_01 ();
java_dtt_in['h000 + i] = java_dtt_in0[i];
end
$readmemh("input_data/clt_dtt_out_00_2_x1489_y951.dat",java_dtt_out0);
for (i=0; i<256; i=i+1) begin
java_dtt_out['h000 + i] = java_dtt_out0[i];
end
$readmemh("input_data/tile_02.dat",tile_shift);
shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
......@@ -301,11 +309,9 @@ module mclt_test_01 ();
end
//Compare DTT inputs
// reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_i.data_dtt_in;
// reg [7:0] java_fi_r;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
initial begin
while (RST) @(negedge CLK);
......@@ -316,12 +322,59 @@ module mclt_test_01 ();
for (cntr4 = 0; cntr4 < 256; cntr4 = cntr4 + 1) begin
#1;
diff4 = data_dtt_in - java_data_dtt_in;
if (n2 < 1) diff4a = data_dtt_in - java_data_dtt_in; // TEMPORARY, while no other data
if (n4 < 1) diff4a = data_dtt_in - java_data_dtt_in; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
integer n5, cntr5, diff5, diff5a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = java_dtt_in0[cntr5[7:0]]; // java_dtt_in[n2 * 256 + cntr2];
wire dtt_r_regen = mclt16x16_i.dtt_r_regen;
reg dtt_r_dv; // SuppressThisWarning VEditor just for simulation
always @ (posedge CLK) begin
if (RST) dtt_r_dv <= 0;
else dtt_r_dv <= dtt_r_regen;
end
initial begin
while (RST) @(negedge CLK);
for (n5 = 0; n5 < 4; n5 = n5+1) begin
while ((!dtt_r_dv) || (mclt16x16_i.dtt_r_cntr[7:0] != 2)) begin
@(negedge CLK);
end
for (cntr5 = 0; cntr5 < 256; cntr5 = cntr5 + 1) begin
#1;
diff5 = dtt_r_data - java_dtt_r_data;
if (n5 < 1) diff5a = dtt_r_data - java_dtt_r_data; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
integer n6, cntr6, diff6, diff6a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_out = mclt16x16_i.dtt_rd_data;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out = java_dtt_out0[{cntr6[1:0],cntr6[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
initial begin
while (RST) @(negedge CLK);
for (n6 = 0; n6 < 4; n6 = n6+1) begin
while ((!mclt16x16_i.dtt_rd_regen_dv[2]) || (mclt16x16_i.dtt_rd_cntr[7:0] != 2)) begin
@(negedge CLK);
end
for (cntr6 = 0; cntr6 < 256; cntr6 = cntr6 + 1) begin
#1;
diff6 = data_dtt_out - java_data_dtt_out;
if (n6 < 1) diff6a = data_dtt_out - java_data_dtt_out; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
......
mclt_test_01.sav
View file @ 730c34f7
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