porting delay scan/adjustment functions from the eddr3 Python code

.project

@@ -97,7 +97,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150311172942225.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150313235008423.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,7 +107,7 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150311172942225.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150314001725869.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

includes/x393_localparams.vh

@@ -74,6 +74,8 @@ DLY_PHASE=       0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK
 
 */  
 `ifdef TARGET_MODE
+    localparam T_RFC=50;  // t_rfc=50 for tCK=2.5ns
+    localparam T_REFI=48; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
   `ifdef use200Mhz
     localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
     localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
@@ -113,19 +115,21 @@ DLY_PHASE=       0x2c # 0x1c # mmcm fine phase shift, 1/4 tCK
   `endif   
     localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
 `else
+    localparam T_RFC=50;  // t_rfc=50 for tCK=2.5ns
+    localparam T_REFI=16; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
   `ifdef use200Mhz
     localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
     localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
-    localparam DLY_LANE0_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE0_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
     localparam DLY_LANE0_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
-    localparam DLY_LANE1_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE1_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
     localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
     localparam DLY_CMDA=  256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
 // alternative to set same type delays to the same value    
     localparam DLY_DQ_IDELAY =  'h20 ;// 'h60;
     localparam DLY_DQ_ODELAY =  'ha0; // 'h48;
     localparam DLY_DQS_IDELAY = 'h40; // 'ha0;
-    localparam DLY_DQS_ODELAY = 'h4c; // 
+    localparam DLY_DQS_ODELAY = 'h78; // 
     localparam DLY_DM_ODELAY =  'ha0; // 'h48;
     localparam DLY_CMDA_ODELAY ='h50; // 'h30;
   `else   

includes/x393_tasks_mcntrl_timing.vh

@@ -41,6 +41,10 @@
 
     task axi_set_dqs_odelay_nominal; //SuppressThisWarning VEditor : may be unused
      begin
+        $display("axi_set_dqs_odelay_nominal(0x%x,0x%x) @ %t",
+        (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff,
+        (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff,
+        $time);
 //        axi_set_dqs_idelay(
         write_contol_register(LD_DLY_LANE0_ODELAY + 8,      (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff);
         write_contol_register(LD_DLY_LANE1_ODELAY + 8,      (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff);
@@ -68,6 +72,8 @@
     task axi_set_delays; // set all individual delays
      integer i;
      begin
+         $display("axi_set_delays @ %t",$time);
+     
         for (i=0;i<10;i=i+1) begin
             write_contol_register(LD_DLY_LANE0_ODELAY + i,     (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);
         end

includes/x393_tasks_pio_sequences.vh

@@ -210,7 +210,7 @@ task set_read_pattern;
         end
 // nop - all 3 below are the same? - just repeat?
         //                          skip     done        bank         ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST
-        data <=  func_encode_skip(   0,       0,          0,           0,  0,  1,  0,    0,    0,    1,  1,   0,        0);
+        data <=  func_encode_skip(   0,       0,          0,           0,  0,  1,  0,    0,    0,    1,  0,   0,        0); // was BUF WR
         @(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
 // nop
         //                          skip     done        bank         ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST

memctrl/phy/phy_cmd.v

@@ -70,7 +70,7 @@ module  phy_cmd#(
 // clocks, reset
     input                        clk_in,
     input                        rst_in,
-    output                       mclk,     // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
+    output                       mclk,     // global clock, half DDR3 clock, synchronizes all I/O through the command port
 // inteface to control I/O delays and mmcm
     input                  [7:0] dly_data, // delay value (3 LSB - fine delay)
     input                  [6:0] dly_addr, // select which delay to program

memctrl/phy/phy_top.v

@@ -285,6 +285,7 @@ wire sdclk; // BUFIO
 // mclk - same frequency as clk_div (same dynamic phase adjust), but with BUFG to be used in other regions. Phase to be
 // statically adjusted for clock boundary crossing
 // Phase control included, allowing setting phase in +/- 127 steps, each 1/56 of 1/Fvco (~22ps for Fvco=800MHz)
+// So shifting phase dynamically by plus/- 113 moves SDCLK by a full period (2.5ns) forward and backward (113= 0x71)
 wire clk_pre, clk_div_pre, sdclk_pre, mclk_pre, clk_fb;
 BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
 BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));

py393/hargs

--v
 -d TARGET_MODE=1
 -f /usr/local/verilog/system_defines.vh
 -f /usr/local/verilog/x393_parameters.vh  /usr/local/verilog/x393_localparams.vh

py393/test_mcntrl.py

@@ -44,6 +44,8 @@ from argparse import RawDescriptionHelpFormatter
 
 from import_verilog_parameters import ImportVerilogParameters
 from import_verilog_parameters import VerilogParameters
+from verilog_utils             import hx 
+
 import x393_mem
 import x393_utils
 import x393_axi_control_status
@@ -51,6 +53,7 @@ import x393_pio_sequences
 import x393_mcntrl_timing
 import x393_mcntrl_buffers
 import x393_mcntrl_tests
+import x393_mcntrl_adjust
 __all__ = []
 __version__ = 0.1
 __date__ = '2015-03-01'
@@ -122,11 +125,7 @@ def execTask(commandLine):
     else:
         result = callableTasks[funcName]['func'](callableTasks[funcName]['inst'],*funcArgs)
     return result
-def hx(obj):
-    try:
-        return "0x%x"%obj
-    except:
-        return str(obj)
+
 
 def getFuncArgsString(name):
     funcFArgs=callableTasks[name]['args']
@@ -297,6 +296,8 @@ USAGE
     x393Timing= x393_mcntrl_timing.X393McntrlTiming(verbose,args.simulated)
     x393Buffers=x393_mcntrl_buffers.X393McntrlBuffers(verbose,args.simulated)
     x393Tests=  x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)
+    x393Adjust= x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated)
+    
     '''
     print ("----------------------")
     print("x393_mem.__dict__="+str(x393_mem.__dict__))
@@ -318,6 +319,7 @@ USAGE
     extractTasks(x393_mcntrl_timing.X393McntrlTiming,x393Timing)
     extractTasks(x393_mcntrl_buffers.X393McntrlBuffers,x393Buffers)
     extractTasks(x393_mcntrl_tests.X393McntrlTests,x393Tests)
+    extractTasks(x393_mcntrl_adjust.X393McntrlAdjust,x393Adjust)
 
 #
     """

py393/verilog_utils.py

@@ -31,11 +31,22 @@ __status__ = "Development"
 #import sys
 #import x393_mem
 #MCNTRL_TEST01_CHN4_STATUS_CNTRL=0
-def hx(obj):
+def hx(obj,length=None):
+    frmt="0x%x"
+    if (length):
+        frmt="0x%0"+str(length)+"x"
+    s=""        
     try:
-        return "0x%x"%obj
+        s=frmt%obj
+        s1=s[0:2]
+        for i in range(2,len(s)):
+            if s[i] != '0':
+                break
+            s1+="o"
+        s=s1+s[len(s1):]    
     except:
-        return str(obj)
+        s=str(obj)
+    return s
 '''
 Simulate Verilog concatenation. Input list tuple of items, each being a pair of (value, width)
 '''    
@@ -45,9 +56,9 @@ def concat(items):
     width=0
     for vw in reversed(items):
         v=vw[0]
-        if vw[1]==1: # So True/False will also work, not just 0/1
+        if not isinstance(v,int):
             if v:
-                v=1
+                v=1 # So True/False will also work, not just 0/1
             else:
                 v=0
         val |= (v & ((1 << vw[1])-1))<<width
@@ -108,4 +119,28 @@ def getParWidth(bitRange):
     else:
         return wl[0]
                     
+def hexMultiple(data):
+    if isinstance(data,list) or isinstance(data,tuple):
+        rslt=[]
+        for item in data:
+            if isinstance(item,list) or isinstance(item,tuple):
+                subResult=[]
+                for subItem in item:
+                    try:
+                        rslt.append("0x%x"%subItem)
+                    except:
+                        rslt.append(str(subItem))
+                rslt.append(subResult)
+            else:
+                try:
+                    rslt.append("0x%x"%item)
+                except:
+                    rslt.append(str(item))
+        rslt=str(rslt)
+    else:
+        try:
+            rslt = "0x%x"%item
+        except:
+            rslt = str(item)
+    return rslt        
             
\ No newline at end of file

py393/x393_axi_control_status.py

@@ -72,6 +72,17 @@ class X393AxiControlStatus(object):
         <data> - 32-bit data to write
         """
         self.x393_mem.axi_write_single_w(self.CONTROL_ADDR+reg_addr, data)
+    def test_read_status(self, rpt): # was read_and_wait_status
+        """
+        Read word from the status register 0 and calculate part of the run busy
+        <rpt> - number of times to repeat
+        """
+        num_busy=0
+        for _ in range(rpt):
+            num_busy+=(self.x393_mem.axi_read_addr_w(self.STATUS_ADDR + 0)>>8) & 1
+        ratio=(1.0* num_busy)/rpt
+        print (("num_busy=%d, rpt=%d, ratio=%f"%(num_busy,rpt,100*ratio))+"%")
+        return ratio
     def read_status(self, address): # was read_and_wait_status
         """
         Read word from the status register (up to 26 bits payload and 6-bit sequence number)
@@ -140,17 +151,17 @@ class X393AxiControlStatus(object):
 #        for name in self.__dict__:
 #            print (name+": "+str(name=='MCONTR_PHY_STATUS_REG_ADDR'))
 #        print (self.__dict__['MCONTR_PHY_STATUS_REG_ADDR'])
-        print ("MCONTR_PHY_STATUS_REG_ADDR:          %s"%(hx(self.read_status(self.MCONTR_PHY_STATUS_REG_ADDR))))
-        print ("MCONTR_TOP_STATUS_REG_ADDR:          %s"%(hx(self.read_status(self.MCONTR_TOP_STATUS_REG_ADDR))))
-        print ("MCNTRL_PS_STATUS_REG_ADDR:           %s"%(hx(self.read_status(self.MCNTRL_PS_STATUS_REG_ADDR))))
-        print ("MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR:%s"%(hx(self.read_status(self.MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR))))
-        print ("MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR:%s"%(hx(self.read_status(self.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR))))
-        print ("MCNTRL_TILED_STATUS_REG_CHN2_ADDR:   %s"%(hx(self.read_status(self.MCNTRL_TILED_STATUS_REG_CHN2_ADDR))))
-        print ("MCNTRL_TILED_STATUS_REG_CHN4_ADDR:   %s"%(hx(self.read_status(self.MCNTRL_TILED_STATUS_REG_CHN4_ADDR))))
-        print ("MCNTRL_TEST01_STATUS_REG_CHN1_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR))))
-        print ("MCNTRL_TEST01_STATUS_REG_CHN2_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR))))
-        print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR))))
-        print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR))))
+        print ("MCONTR_PHY_STATUS_REG_ADDR:          %s"%(hx(self.read_status(self.MCONTR_PHY_STATUS_REG_ADDR),8)))
+        print ("MCONTR_TOP_STATUS_REG_ADDR:          %s"%(hx(self.read_status(self.MCONTR_TOP_STATUS_REG_ADDR),8)))
+        print ("MCNTRL_PS_STATUS_REG_ADDR:           %s"%(hx(self.read_status(self.MCNTRL_PS_STATUS_REG_ADDR) ,8)))
+        print ("MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR:%s"%(hx(self.read_status(self.MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),8)))
+        print ("MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR:%s"%(hx(self.read_status(self.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),8)))
+        print ("MCNTRL_TILED_STATUS_REG_CHN2_ADDR:   %s"%(hx(self.read_status(self.MCNTRL_TILED_STATUS_REG_CHN2_ADDR),8)))
+        print ("MCNTRL_TILED_STATUS_REG_CHN4_ADDR:   %s"%(hx(self.read_status(self.MCNTRL_TILED_STATUS_REG_CHN4_ADDR),8)))
+        print ("MCNTRL_TEST01_STATUS_REG_CHN1_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),8)))
+        print ("MCNTRL_TEST01_STATUS_REG_CHN2_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),8)))
+        print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),8)))
+        print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR:  %s"%(hx(self.read_status(self.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8)))
 
     def program_status(self,
                        base_addr,   # input [29:0] base_addr;

py393/x393_pio_sequences.py

@@ -79,7 +79,7 @@ class X393PIOSequences(object):
         <chn>            sub-channel to use: 0 - memory read, 1 - memory write
         <wait_complete>  Do not request a new transaction from the scheduler until previous memory transaction is finished
         """
-        self.write_contol_register(self.MCNTRL_PS_ADDR + self.MCNTRL_PS_CMD,
+        self.x393_axi_tasks.write_contol_register(self.MCNTRL_PS_ADDR + self.MCNTRL_PS_CMD,
                                                   # {17'b0,
                                                   ((0,1)[wait_complete]<<14) |
                                                   ((0,1)[chn]<<13) |
@@ -89,7 +89,8 @@ class X393PIOSequences(object):
  
     def wait_ps_pio_ready(self,         #; // wait PS PIO module can accept comamnds (fifo half empty)
                           mode,         # input [1:0] mode;
-                          sync_seq): # input       sync_seq; //  synchronize sequences
+                          sync_seq,     # input       sync_seq; //  synchronize sequences
+                          timeout=2.0): # maximal timeout in seconds
         """
         Wait until PS PIO module can accept comamnds (fifo half empty) 
         <mode>           status mode (0..3) - see 'help program_status'
@@ -433,7 +434,7 @@ class X393PIOSequences(object):
         <rst>  1 - reset active, 0 - reset off
         """
         
-        self.write_contol_register(self.MCNTRL_PS_ADDR + self.MCNTRL_PS_EN_RST,
+        self.x393_axi_tasks.write_contol_register(self.MCNTRL_PS_ADDR + self.MCNTRL_PS_EN_RST,
                                    ((0,1)[en]<<1) | #{30'b0,en,
                                    (1,0)[rst])  #~rst});
    
@@ -642,7 +643,7 @@ class X393PIOSequences(object):
             cmd_addr += 1
 # nop - all 3 below are the same? - just repeat?
         #                          skip      done        bank                       ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST
-        data=self.func_encode_skip(   0,       0,          0,                        0,  0,  1,  0,    0,    0,    1,  1,   0,        0)
+        data=self.func_encode_skip(   0,       0,          0,                        0,  0,  1,  0,    0,    0,    1,  0,   0,        0)
         self.x393_mem.axi_write_single_w(cmd_addr, data)
         cmd_addr += 1
 # nop
@@ -761,10 +762,10 @@ class X393PIOSequences(object):
         """
         Setup refresh sequence at parameter defined address in the sequencer memory
         <t_rfc>       tRFC =50 for tCK=2.5ns
-        <t_refi>      tREFI 48/97 for hardware, 8 - for simulation
+        <t_refi>      tREFI 48/97 for hardware, 16 - for simulation
         <en_refresh>  enable refresh immediately 
         """
-
+        print("SET REFRESH: tRFC=%d, tREFI=%d"%(t_rfc,t_refi))
         cmd_addr = self.MCONTR_CMD_WR_ADDR + self.REFRESH_OFFSET
         #                           addr                 bank                   RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
         data=self.func_encode_cmd(    0,                   0,                    6,  0,  0,  0,  0,    0,    0,    0,  0,   0,   0,   0)
@@ -876,4 +877,60 @@ class X393PIOSequences(object):
         self.x393_mem.axi_write_single_w(cmd_addr, data)
         cmd_addr += 1
 
-        
+    def read_pattern(self,
+                     num,
+                     show_rslt,
+                     wait_complete=1): # Wait for operation to complete
+        """
+        Read pattern 
+        <num>           number of 32-bit words to read
+        <show_rslt>     print read data
+        <wait_complete> wait read pattern operation to complete (0 - may initiate multiple PS PIO operations)
+        returns list of the read data
+        """
+
+        self.x393_pio_sequences.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
+                        self.READ_PATTERN_OFFSET,   # input [9:0] seq_addr; # sequence start address
+                        2,                          # input [1:0] page;     # buffer page number
+                        0,                          # input       urgent;   # high priority request (only for competion with other channels, will not pass in this FIFO)
+                        0,                          # input       chn;      # channel buffer to use: 0 - memory read, 1 - memory write
+                        wait_complete) # `PS_PIO_WAIT_COMPLETE ) #  wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
+        self.x393_pio_sequences.wait_ps_pio_done(self.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
+        return self.x393_mcntrl_buffers.read_block_buf_chn (0, 2, num, show_rslt )    # chn=0, page=2, number of 32-bit words=num, show_rslt
+
+    def read_block(self,
+                     num,
+                     show_rslt,
+                     wait_complete=1): # Wait for operation to complete
+        """
+        Read block in PS PIO mode 
+        <num>           number of 32-bit words to read
+        <show_rslt>     print read data
+        <wait_complete> wait read pattern operation to complete (0 - may initiate multiple PS PIO operations)
+        returns list of the read data
+        """
+    
+        self.x393_pio_sequences.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
+                        self.READ_BLOCK_OFFSET,   # input [9:0] seq_addr; # sequence start address
+                        3,                     # input [1:0] page;     # buffer page number
+                        0,                     # input       urgent;   # high priority request (only for competion with other channels, will not pass in this FIFO)
+                        0,                     # input       chn;      # channel buffer to use: 0 - memory read, 1 - memory write
+                        wait_complete)         #  wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
+        self.x393_pio_sequences.wait_ps_pio_done(self.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
+        return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt
+
+    def write_block(self,
+                     wait_complete): # Wait for operation to complete
+        """
+        Write block in PS PIO mode 
+        <wait_complete> wait write block operation to complete (0 - may initiate multiple PS PIO operations)
+        """
+#    write_block_buf_chn; # fill block memory - already set in set_up task
+        self.x393_pio_sequences.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
+                        self.WRITE_BLOCK_OFFSET,    # input [9:0] seq_addr; # sequence start address
+                        0,                     # input [1:0] page;     # buffer page number
+                        0,                     # input       urgent;   # high priority request (only for competion with other channels, will not pass in this FIFO)
+                        1,                     # input       chn;      # channel buffer to use: 0 - memory read, 1 - memory write
+                        wait_complete)         # `PS_PIO_WAIT_COMPLETE )#  wait_complete; # Do not request a newer transaction from the scheduler until previous memory transaction is finished
+# temporary - for debugging:
+#        self.x393_pio_sequences.wait_ps_pio_done(self.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)

x393_testbench01.tf

@@ -19,16 +19,18 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
 `timescale 1ns/1ps
+`include "system_defines.vh"
+
 //`define use200Mhz 1
 //`define DEBUG_FIFO 1
 `undef WAIT_MRS
-`define SET_PER_PIN_DEALYS 1 // set individual (including per-DQ pin delays)
+`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
 `define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
 // Disabled already passed test to speedup simulation
 //`define TEST_WRITE_LEVELLING 1
-//`define TEST_READ_PATTERN 1
-//`define TEST_WRITE_BLOCK 1
-//`define TEST_READ_BLOCK 1
+`define TEST_READ_PATTERN 1
+`define TEST_WRITE_BLOCK 1
+`define TEST_READ_BLOCK 1
 //`define TESTL_SHORT_SCANLINE 1
 
 //`define TEST_SCANLINE_WRITE 1
@@ -322,6 +324,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
 `endif    
     enable_refresh(1);
     axi_set_dqs_odelay('h78); //??? dafaults - wrong?
+    axi_set_dqs_odelay_nominal;
     
 `ifdef TEST_WRITE_LEVELLING 
     test_write_levelling;
@@ -485,6 +488,7 @@ end
   initial begin
 //  #10000000;
      #200000;
+//     #42000;
 //   #100000;
 //  #60000;
     $display("finish testbench 2");
@@ -1076,9 +1080,11 @@ simul_axi_read #(
             write_block_buf_chn(0,0,256); // fill block memory (channel, page, number)
 // set all delays
 //#axi_set_delays - from tables, per-pin
-`ifdef SET_PER_PIN_DEALYS
+`ifdef SET_PER_PIN_DELAYS
+            $display("SET_PER_PIN_DELAYS @ %t",$time);
             axi_set_delays; // set all individual delays, aslo runs axi_set_phase()
 `else
+            $display("SET COMMON DELAYS @ %t",$time);
             axi_set_same_delays(DLY_DQ_IDELAY,DLY_DQ_ODELAY,DLY_DQS_IDELAY,DLY_DQS_ODELAY,DLY_DM_ODELAY,DLY_CMDA_ODELAY);
 // set clock phase relative to DDR clk
             axi_set_phase(DLY_PHASE);
@@ -1120,8 +1126,8 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
         
 //        @ (negedge rstb);
         axi_set_dqs_idelay_nominal;
-//        axi_set_dqs_odelay_nominal;
-        axi_set_dqs_odelay('h78);
+        axi_set_dqs_odelay_nominal;
+//        axi_set_dqs_odelay('h78);
         axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY
    end
 endtask
@@ -1626,8 +1632,8 @@ task set_all_sequences;
             set_mrs(1);
             $display("SET REFRESH @ %t",$time);    
             set_refresh(
-                50, // input [ 9:0] t_rfc; // =50 for tCK=2.5ns
-                16); //input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
+                T_RFC, // input [ 9:0] t_rfc; // =50 for tCK=2.5ns
+                T_REFI); //input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
             $display("SET WRITE LEVELING @ %t",$time);    
             set_write_lev(16); // write leveling, 16 times   (full buffer - 128) 
             $display("SET READ PATTERN @ %t",$time);