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Commit 6ed7aef1 authored by Andrey Filippov's avatar Andrey Filippov
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bug fixrd in DCT and other places

parent 30417be4
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Showing with 601 additions and 121 deletions
cocotb/x393_cocotb_02.sav
View file @ 6ed7aef1
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Jul 13 05:40:27 2016 [*] Mon Jul 18 03:09:11 2016
[*] [*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160712232733848.fst" [dumpfile] "/home/andrey/git/x393-neon/simulation/x393_dut-20160717195210458.fst"
[dumpfile_mtime] "Wed Jul 13 05:39:25 2016" [dumpfile_mtime] "Mon Jul 18 02:40:16 2016"
[dumpfile_size] 85164083 [dumpfile_size] 400879350
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav" [savefile] "/home/andrey/git/x393-neon/cocotb/x393_cocotb_02.sav"
[timestart] 52359000 [timestart] 73530000
[size] 1836 1171 [size] 1823 1180
[pos] 0 0 [pos] 1917 0
*-18.056383 53089817 11730000 52973000 53604000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.042217 79400000 123238096 124220833 174385000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut. [treeopen] x393_dut.
[treeopen] x393_dut.ddr3_i.ddr3_i. [treeopen] x393_dut.ddr3_i.ddr3_i.
[treeopen] x393_dut.par12_hispi_psp4l1_i.
[treeopen] x393_dut.par12_hispi_psp4l1_i.cmprs_channel_block[0]. [treeopen] x393_dut.par12_hispi_psp4l1_i.cmprs_channel_block[0].
[treeopen] x393_dut.simul_axi_hp1_wr_i.
[treeopen] x393_dut.simul_axi_master_wdata_i. [treeopen] x393_dut.simul_axi_master_wdata_i.
[treeopen] x393_dut.x393_i. [treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0]. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1]. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_dut.x393_i.compressor393_i.genblk3. [treeopen] x393_dut.x393_i.compressor393_i.genblk3.
[treeopen] x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i. [treeopen] x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i. [treeopen] x393_dut.x393_i.mcntrl393_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i. [treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i. [treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i. [treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i. [treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0]. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.sensors393_i. [treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
...@@ -44,14 +51,12 @@ ...@@ -44,14 +51,12 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3]. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[sst_width] 402 [sst_width] 362
[signals_width] 312 [signals_width] 331
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 604 [sst_vpaned_height] 610
@820 @820
x393_dut.TEST_TITLE[639:0] x393_dut.TEST_TITLE[639:0]
@800200 @800200
...@@ -61,32 +66,9 @@ x393_dut.TEST_TITLE[639:0] ...@@ -61,32 +66,9 @@ x393_dut.TEST_TITLE[639:0]
@28 @28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.locked x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.locked
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.locked_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.locked_2015_3
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0 x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0_2015_3
@200 @200
- -
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.mismatch
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkfb_stopped_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkfbout_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkfboutb_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkin_stopped_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout0_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout0b_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout1_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout1b_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout2_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout2b_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout3_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout3b_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout4_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout5_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_clkout6_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_locked_2016_2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.dif_psdone_2016_2
@1401200 @1401200
-phy_top -phy_top
@1000200 @1000200
...@@ -176,7 +158,7 @@ x393_dut.dutm0_xtra_blag[3:0] ...@@ -176,7 +158,7 @@ x393_dut.dutm0_xtra_blag[3:0]
x393_dut.dutm0_xtra_rdlag[3:0] x393_dut.dutm0_xtra_rdlag[3:0]
@1401200 @1401200
-maxi0 -maxi0
@800200 @c00200
-SENSOR1 -SENSOR1
@28 @28
x393_dut.simul_sensor12bits_i.MCLK x393_dut.simul_sensor12bits_i.MCLK
...@@ -189,12 +171,8 @@ x393_dut.simul_sensor12bits_i.ARST ...@@ -189,12 +171,8 @@ x393_dut.simul_sensor12bits_i.ARST
x393_dut.simul_sensor12bits_i.NMRST x393_dut.simul_sensor12bits_i.NMRST
x393_dut.simul_sensor12bits_i.stopped x393_dut.simul_sensor12bits_i.stopped
x393_dut.simul_sensor12bits_i.DCLK x393_dut.simul_sensor12bits_i.DCLK
@1000200 @1401200
-SENSOR1 -SENSOR1
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst_in
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst
@c00200 @c00200
-memory_timing -memory_timing
@200 @200
...@@ -373,7 +351,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_dat ...@@ -373,7 +351,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_dat
-memory -memory
@1401200 @1401200
-sensor_channel0 -sensor_channel0
@800200 @c00200
-par12_hispi_psp4l1 -par12_hispi_psp4l1
@28 @28
x393_dut.par12_hispi_psp4l1_i.pclk x393_dut.par12_hispi_psp4l1_i.pclk
...@@ -387,13 +365,390 @@ x393_dut.par12_hispi_psp4l1_i.next_line_oclk ...@@ -387,13 +365,390 @@ x393_dut.par12_hispi_psp4l1_i.next_line_oclk
x393_dut.par12_hispi_psp4l1_i.pxd[11:0] x393_dut.par12_hispi_psp4l1_i.pxd[11:0]
x393_dut.par12_hispi_psp4l1_i.sdata[3:0] x393_dut.par12_hispi_psp4l1_i.sdata[3:0]
x393_dut.par12_hispi_psp4l1_i.sdata_dly[3:0] x393_dut.par12_hispi_psp4l1_i.sdata_dly[3:0]
@1401200
-par12_hispi_psp4l1
@c00200
-all_par_hispi
@28
x393_dut.par12_hispi_psp4l0_i.hact
x393_dut.par12_hispi_psp4l1_i.hact
x393_dut.par12_hispi_psp4l2_i.hact
x393_dut.par12_hispi_psp4l3_i.hact
@8022
x393_dut.par12_hispi_psp4l0_i.pxd[11:0]
x393_dut.par12_hispi_psp4l1_i.pxd[11:0]
x393_dut.par12_hispi_psp4l2_i.pxd[11:0]
x393_dut.par12_hispi_psp4l3_i.pxd[11:0]
@200
-hispi_out
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(10)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(11)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(12)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(13)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(14)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
(15)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
@1401200
-group_end
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.waddr[8:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.wpage[1:0]
@1401200
-all_par_hispi
@c00200
-compressor_0
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.mclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frame_start_dst
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_standalone
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.vsync_late
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.reading_frame_r
@200 @200
- -
@1000200 @c00022
-par12_hispi_psp4l1 x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
(3)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
@1401200
-group_end
@c08028
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_go
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frames_numbers_differ
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_src[15:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.line_unfinished_src[15:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_number_dst[15:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.line_unfinished_dst[15:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.suspend
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_done_dst
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_start_xclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_pre_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_pre_start_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_pre_start_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.starting
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.last_mb
@200 @200
- -
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.wpage[1:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_need
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.xfer_grant
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.curr_y[15:0]
@200
-SAXI
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awvalid
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_awaddr[31:0]
@28
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wvalid
@22
x393_dut.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.afi_wdata[63:0]
@28
x393_dut.simul_axi_hp1_wr_i.awvalid
@22
x393_dut.simul_axi_hp1_wr_i.awaddr[31:0]
@28
x393_dut.simul_axi_hp1_wr_i.wvalid
@22
x393_dut.simul_axi_hp1_wr_i.sim_wr_address[31:0]
x393_dut.simul_axi_hp1_wr_i.sim_wr_data[63:0]
@28
x393_dut.simul_axi_hp1_wr_i.sim_wr_valid
@1401200
-compressor_0
@800200
-compressors_all
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.scrambler_i.rst
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.buf_re[3:0]
@1401200
-group_end
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_pxd[7:0]
@8028
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_rd[1:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.scrambler_i.val_in
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_pixel_buf_iface_i.scrambler_i.val_in
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.scrambler_i.val_in
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_pixel_buf_iface_i.scrambler_i.val_in
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.DBG_SCRAMBLED[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_pixel_buf_iface_i.DBG_SCRAMBLED[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.DBG_SCRAMBLED[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_pixel_buf_iface_i.DBG_SCRAMBLED[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_pre_first_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.dct_pre_first_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct_pre_first_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.dct_pre_first_out
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_out[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.dct_out[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct_out[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.dct_out[12:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.scrambler_i.rst
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.DBG_DCT_SCRAMBLED[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.DBG_DCT_SCRAMBLED[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.DBG_DCT_SCRAMBLED[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.DBG_DCT_SCRAMBLED[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.DBG_DCT_DV
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.DBG_DCT_DV
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.DBG_DCT_DV
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.DBG_DCT_DV
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.per_type[2:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.pre_we_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.we_r
@808022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.cntr_in[3:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.cntr_in[3:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.cntr_in[3:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.cntr_in[3:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.cntr_in[3:0]
@1001200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.stage2_pre2_start_out
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct2_out[12:0]
@800200
-reorder
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.pre2_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.en
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.per_type[2:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.pre_we_r
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.cntr_in[3:0]
@29
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.en_out_r
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.dv
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.en_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_reorder_out_i.stop_out
@1000200
-reorder
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.clk
@800200
-stage2
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.pre2_start_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.pre_en_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.en_out
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.dout[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.per_type[2:0]
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase[7:0]
@1401200
-group_end
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct1d_chen_stage2_i.phase_cnt[2:0]
@1000200
-stage2
@800200 @800200
-transpose
@c08022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.wcntr[6:0]
@808022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.rcntr[5:0]
@1001200
-group_end
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.pre2_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.start_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.en_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.dct2d8x8_chen_i.dct_chen_transpose_i.pre2_stop
@1000200
-transpose
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.page_ready_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.page_ready_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.page_ready_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.page_ready_chn
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_start_xclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.starting
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.last_mb
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_rows_left[12:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_last_row
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_last_in_row
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_end_in
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mb_pre_end
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_pre_start_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.frame_pre_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_first_in_row
@c08022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.dct_pipeline_delay_cntr[5:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
(8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_pre_start[8:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.mb_pre_start
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.period_cntr[8:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.mb_release_buf
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.next_page_chn
@8028
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.add_invalid[1:0]
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.next_page_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.next_page_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.next_page_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.next_page_chn
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_wpage_nxt
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_wpage_nxt
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_wpage_nxt
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_wpage_nxt
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_we
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_we
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_we
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_we
@200
-
@8028
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_rd[1:0]
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_pxd[7:0]
@1000200
-compressors_all
@200
-
@c00200
-sensor_channel1 -sensor_channel1
@22 @22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.data_r[31:0] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.data_r[31:0]
...@@ -423,15 +778,13 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398 ...@@ -423,15 +778,13 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i.ipclk2x x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_clock_i.ipclk2x
@1000200 @1000200
-hispi_clock -hispi_clock
@800200 @c00200
-hispi+lanes -hispi+lanes
@28 @28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sof_pclk x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sof_pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.pclk x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.pclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_pclk x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.start_only x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.start_only
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_all_dly x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_all_dly
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.start_fifo_re x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.start_fifo_re
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line
...@@ -642,7 +995,6 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398 ...@@ -642,7 +995,6 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.ra[4:0] (4)x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].sens_hispi_fifo_i.ra[4:0]
@1401200 @1401200
-group_end -group_end
@1000200
-hispi+lanes -hispi+lanes
@c08022 @c08022
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sns_dp[3:0] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sns_dp[3:0]
...@@ -742,11 +1094,21 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.buf_dout[63 ...@@ -742,11 +1094,21 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.buf_dout[63
- -
@1000200 @1000200
-memory -memory
@1401200
-sensor_channel1 -sensor_channel1
@800200 @800200
-ddr3 -ddr3
@22 @8022
x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
@800022
x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0] x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
(1)x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
(2)x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
(3)x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
@1001200
-group_end
@c08022 @c08022
x393_dut.SDD[15:0] x393_dut.SDD[15:0]
@28 @28
...@@ -793,8 +1155,8 @@ x393_dut.SDD[15:0] ...@@ -793,8 +1155,8 @@ x393_dut.SDD[15:0]
-group_end -group_end
@22 @22
x393_dut.SDA[14:0] x393_dut.SDA[14:0]
@28
x393_dut.SDBA[2:0] x393_dut.SDBA[2:0]
@28
x393_dut.SDCAS x393_dut.SDCAS
x393_dut.SDRAS x393_dut.SDRAS
x393_dut.SDWE x393_dut.SDWE
...@@ -879,7 +1241,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late ...@@ -879,7 +1241,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hclk
@1000200 @1000200
-compressor_channel0 -compressor_channel0
@800200 @c00200
-interrupts -interrupts
@800022 @800022
x393_dut.irq_r[8:0] x393_dut.irq_r[8:0]
...@@ -917,7 +1279,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status ...@@ -917,7 +1279,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status
-group_end -group_end
@200 @200
- -
@1000200 @1401200
-interrupts -interrupts
@c00200 @c00200
-afi0_mux -afi0_mux
...@@ -1058,7 +1420,7 @@ x393_dut.x393_i.afi1_wvalid ...@@ -1058,7 +1420,7 @@ x393_dut.x393_i.afi1_wvalid
-x393_afi1 -x393_afi1
@1401200 @1401200
-saxihp1 -saxihp1
@800200 @c00200
-simul_axi_hp1_wr -simul_axi_hp1_wr
@22 @22
x393_dut.simul_axi_hp1_wr_i.sim_bresp_latency[3:0] x393_dut.simul_axi_hp1_wr_i.sim_bresp_latency[3:0]
...@@ -1100,6 +1462,7 @@ x393_dut.simul_axi_hp1_wr_i.wdata_i.half_full ...@@ -1100,6 +1462,7 @@ x393_dut.simul_axi_hp1_wr_i.wdata_i.half_full
x393_dut.simul_axi_hp1_wr_i.wdata_i.fill[7:0] x393_dut.simul_axi_hp1_wr_i.wdata_i.fill[7:0]
@1000200 @1000200
-wdata_i -wdata_i
@1401200
-simul_axi_hp1_wr -simul_axi_hp1_wr
@200 @200
- -
......
cocotb/x393_dut.v
View file @ 6ed7aef1
...@@ -383,7 +383,9 @@ module x393_dut#( ...@@ -383,7 +383,9 @@ module x393_dut#(
`endif `endif
`ifdef HISPI `ifdef HISPI
parameter HBLANK= 92; // 72; // 62; // 52; // 90; // 12; /// 52; //********************* parameter HBLANK= 132; // all in time
/// parameter HBLANK= 122; // 72; // 62; // 52; // 90; // 12; /// 52; //********************* Still too fast
/// parameter HBLANK= 92; // 72; // 62; // 52; // 90; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 9; /// 3; // 9; // 3; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE= 9; /// 3; // 9; // 3; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 8; /// 1; //8; parameter BLANK_ROWS_AFTER= 8; /// 1; //8;
......
compressor_jp/cmprs_frame_sync.v
View file @ 6ed7aef1
...@@ -94,21 +94,23 @@ module cmprs_frame_sync#( ...@@ -94,21 +94,23 @@ module cmprs_frame_sync#(
*/ */
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late // wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
// wire frame_started_mclk; // wire frame_started_mclk;
reg bonded_mode; reg bonded_mode;
reg frame_start_dst_r; reg [3:0] frame_start_dst_r;
reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_* reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late
reg frames_numbers_differ; // src and dest point to different frames (multi-frame buffer mode), disregard line_unfinished_* reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_*
reg line_numbers_sync; // src unfinished line number is > this unfinished line number reg frames_numbers_differ; // src and dest point to different frames (multi-frame buffer mode), disregard line_unfinished_*
reg line_numbers_sync; // src unfinished line number is > this unfinished line number
reg reading_frame_r; // compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame reg reading_frame_r; // compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame
reg broken_frame; // reg broken_frame;
reg aborted_frame; reg aborted_frame;
reg stuffer_running_mclk_r; reg stuffer_running_mclk_r;
reg [CMPRS_TIMEOUT_BITS-1:0] timeout; reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
reg cmprs_en_extend_r=0; reg cmprs_en_extend_r=0;
reg cmprs_en_d; reg cmprs_en_d;
reg suspend_end; // suspend at teh end of the current frame until frame number changes
// reg cmprs_en_xclk; // reg cmprs_en_xclk;
assign frame_start_dst = frame_start_dst_r; assign frame_start_dst = frame_start_dst_r[0];
assign cmprs_en_extend = cmprs_en_extend_r; assign cmprs_en_extend = cmprs_en_extend_r;
assign stuffer_running_mclk = stuffer_running_mclk_r; assign stuffer_running_mclk = stuffer_running_mclk_r;
...@@ -132,17 +134,32 @@ module cmprs_frame_sync#( ...@@ -132,17 +134,32 @@ module cmprs_frame_sync#(
cmprs_en_d <= cmprs_en; cmprs_en_d <= cmprs_en;
broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse /// broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r; aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0; if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
else if (broken_frame || aborted_frame) force_flush_long <= 1; /// else if (broken_frame || aborted_frame) force_flush_long <= 1;
else if (aborted_frame) force_flush_long <= 1;
if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0; /// if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
if (!cmprs_en || frame_done ) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1; else if (frame_started_mclk) reading_frame_r <= 1;
frame_start_dst_r <= cmprs_en && (cmprs_run ? (vsync_late && !reading_frame_r) : cmprs_standalone); if (!cmprs_en) frame_start_pend_r <= 0;
else if (cmprs_run && vsync_late && reading_frame_r) frame_start_pend_r <= 1;
else if (frame_start_dst_r[0]) frame_start_pend_r <= 0;
if (!cmprs_en) suspend_end <= 0;
else if (frame_done) suspend_end <= 1;
else if (frame_start_dst_r[3]) suspend_end <= 0;
frame_start_dst_r[0] <= cmprs_en && (cmprs_run ?
((vsync_late && !reading_frame_r) || (frame_start_pend_r && frame_done)):
cmprs_standalone);
if (!cmprs_en) frame_start_dst_r[3:1] <=0;
else frame_start_dst_r[3:1] <= frame_start_dst_r[2:0];
if (!cmprs_en) bonded_mode <= 0; if (!cmprs_en) bonded_mode <= 0;
else if (cmprs_run) bonded_mode <= 1; else if (cmprs_run) bonded_mode <= 1;
else if (cmprs_standalone) bonded_mode <= 0; else if (cmprs_standalone) bonded_mode <= 0;
...@@ -150,12 +167,10 @@ module cmprs_frame_sync#( ...@@ -150,12 +167,10 @@ module cmprs_frame_sync#(
if (!cmprs_en || !cmprs_run || vsync_late) frames_differ <= 0; if (!cmprs_en || !cmprs_run || vsync_late) frames_differ <= 0;
else if (frame_done_src) frames_differ <= 1'b1; else if (frame_done_src) frames_differ <= 1'b1;
frames_numbers_differ <= frame_number_src != frame_number; frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented
line_numbers_sync <= (line_unfinished_src > line_unfinished); line_numbers_sync <= (line_unfinished_src > line_unfinished);
// suspend <= !bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync);
// suspend <= bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || !line_numbers_sync);
suspend <= bonded_mode && !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync); suspend <= bonded_mode && !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync);
......
compressor_jp/cmprs_macroblock_buf_iface.v
View file @ 6ed7aef1
...@@ -123,7 +123,9 @@ module cmprs_macroblock_buf_iface #( ...@@ -123,7 +123,9 @@ module cmprs_macroblock_buf_iface #(
// reg first_mb; // from mb_pre_start[2] to mb_pre_start[1] // reg first_mb; // from mb_pre_start[2] to mb_pre_start[1]
wire starting; wire starting;
reg frame_pre_run; reg frame_pre_run;
reg [1:0] frame_may_start; // reg [1:0] frame_may_start;
reg frame_start_xclk_r; // next cycle after frame_start_xclk
reg [5:0] dct_pipeline_delay_cntr; reg [5:0] dct_pipeline_delay_cntr;
...@@ -143,19 +145,27 @@ module cmprs_macroblock_buf_iface #( ...@@ -143,19 +145,27 @@ module cmprs_macroblock_buf_iface #(
assign last_mb = mb_last_row && mb_last_in_row; assign last_mb = mb_last_row && mb_last_in_row;
assign starting = |mb_pre_start; assign starting = |mb_pre_start;
// assign mb_pre_start_w = (mb_pre_end_in && (!last_mb || frame_en_w)) || (!frame_pre_run && frame_en_w && !frame_en_r && !starting); /*
// assign frame_pre_start_w = frame_en_w && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_en_r && !starting)); assign mb_pre_start_w = (mb_pre_end_in && (!last_mb || frame_may_start)) ||
assign mb_pre_start_w = (mb_pre_end_in && (!last_mb || frame_may_start)) || ((frame_may_start==2'b1) && !frame_pre_run && !starting); ((frame_may_start==2'b1) && !frame_pre_run && !starting);
assign frame_pre_start_w = frame_may_start[0] && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_may_start[1] && !starting)); assign frame_pre_start_w = frame_may_start[0] && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_may_start[1] && !starting));
*/
assign mb_pre_start_w = mb_pre_end_in || (frame_start_xclk_r && !frame_pre_run && !starting);
assign frame_pre_start_w = (mb_pre_end_in && last_mb) || (frame_start_xclk_r && !frame_pre_run && !starting);
//frame_start_xclk_r
assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock
always @ (posedge xclk) begin always @ (posedge xclk) begin
if (!frame_en) frame_start_xclk_r <= 0;
else frame_start_xclk_r <= frame_start_xclk;
if (!frame_en) frame_en_r <= 0; if (!frame_en) frame_en_r <= 0;
else frame_en_r <= frame_en_w; else frame_en_r <= frame_en_w;
if (!frame_en_w || starting) frame_may_start[0] <= 0; /// if (!frame_en_w || starting) frame_may_start[0] <= 0;
else if (frame_start_xclk) frame_may_start[0] <= 1; /// else if (frame_start_xclk) frame_may_start[0] <= 1;
frame_may_start[1] <= frame_may_start[0]; /// frame_may_start[1] <= frame_may_start[0];
frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start
......
compressor_jp/cmprs_pixel_buf_iface.v
View file @ 6ed7aef1
...@@ -133,6 +133,18 @@ module cmprs_pixel_buf_iface #( ...@@ -133,6 +133,18 @@ module cmprs_pixel_buf_iface #(
// assign data_out = do_r; // assign data_out = do_r;
assign pre_first_out = pre_first_out_r[0]; assign pre_first_out = pre_first_out_r[0];
assign pre2_first_out = pre_first_out_r[1]; assign pre2_first_out = pre_first_out_r[1];
`ifdef DEBUG_COMPRESSOR_SCRAMBLE
wire [31:0] DBG_SCRAMBLED;
scrambler #(
.DATA_BYTE_WIDTH(4)
) scrambler_i (
.clk (xclk), // input wire
.rst (mb_pre_start), // input wire
.val_in (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]), // input wire
.data_in ({24'b0,buf_di}), // input[31:0] wire
.data_out (DBG_SCRAMBLED) // output[31:0] wire
);
`endif
always @(posedge xclk) begin always @(posedge xclk) begin
// mb_h <= mb_h_m1+1; // macroblock height // mb_h <= mb_h_m1+1; // macroblock height
......
compressor_jp/jp_channel.v
View file @ 6ed7aef1
...@@ -153,7 +153,7 @@ module jp_channel#( ...@@ -153,7 +153,7 @@ module jp_channel#(
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// Master(sensor)/slave(compressor) synchronization signals // Master(sensor)/slave(compressor) synchronization signals
output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode // this output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory) // (compress from memory)
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?) input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
...@@ -723,7 +723,7 @@ module jp_channel#( ...@@ -723,7 +723,7 @@ module jp_channel#(
.coring_we (set_coring_w), // input - write color saturation values .coring_we (set_coring_w), // input - write color saturation values
.di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used) .di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used)
.frame_start (frame_start_dst), // input @mclk .frame_start (frame_start_dst), // input @mclk
.frame_start_xclk (frame_start_xclk), // re-clocked, parameters are copied during this pulse .frame_start_xclk (frame_start_xclk), // output re-clocked, parameters are copied during this pulse
.cmprs_en_mclk (cmprs_en_mclk), // output .cmprs_en_mclk (cmprs_en_mclk), // output
.cmprs_en_extend (cmprs_en_extend), // input .cmprs_en_extend (cmprs_en_extend), // input
.cmprs_run_mclk (cmprs_run_mclk), // output reg .cmprs_run_mclk (cmprs_run_mclk), // output reg
...@@ -970,7 +970,20 @@ module jp_channel#( ...@@ -970,7 +970,20 @@ module jp_channel#(
// Each pass (1d) uses 5 DSP48E1 modules (2 - multipliers and 3 SIMD (2x24) adder/subracters // Each pass (1d) uses 5 DSP48E1 modules (2 - multipliers and 3 SIMD (2x24) adder/subracters
// Needs a small (<48, but did not calculate yet) pause between block if they did not come // Needs a small (<48, but did not calculate yet) pause between block if they did not come
// immediately after each other. This pause is needed to restart pipeline // immediately after each other. This pause is needed to restart pipeline
`ifdef DEBUG_COMPRESSOR_SCRAMBLE
wire DBG_DCT_DV;
wire [31:0] DBG_DCT_SCRAMBLED;
scrambler #(
.DATA_BYTE_WIDTH(4)
) scrambler_i (
.clk (xclk), // input wire
.rst (first_block_dct && !DBG_DCT_DV && !dct_pre_first_out), // input wire
.val_in (DBG_DCT_DV), // input wire
.data_in ({19'b0, dct_out}), // input[31:0] wire
.data_out (DBG_DCT_SCRAMBLED) // output[31:0] wire
);
`endif
dct2d8x8_chen #( dct2d8x8_chen #(
.INPUT_WIDTH (10), .INPUT_WIDTH (10),
.OUTPUT_WIDTH (13), .OUTPUT_WIDTH (13),
...@@ -990,8 +1003,12 @@ module jp_channel#( ...@@ -990,8 +1003,12 @@ module jp_channel#(
.xin (yc_nodc), // input[9:0] signed .xin (yc_nodc), // input[9:0] signed
.last_in (dct_last_in), // output reg .last_in (dct_last_in), // output reg
.pre_first_out (dct_pre_first_out), // output .pre_first_out (dct_pre_first_out), // output
`ifdef DEBUG_COMPRESSOR_SCRAMBLE
.dv (DBG_DCT_DV), // output
`else
.dv (), // output .dv (), // output
.d_out (dct_out) // output[12:0] signed `endif
.d_out (dct_out) // output[12:0] signed
); );
wire quant_start; wire quant_start;
......
dsp/dct1d_chen.v
View file @ 6ed7aef1
...@@ -312,10 +312,13 @@ module dct1d_chen#( ...@@ -312,10 +312,13 @@ module dct1d_chen#(
if (rst) per_type <= 0; if (rst) per_type <= 0;
else if (start) per_type <= 3'h1; else if (start) per_type <= 3'h1;
else if (phase[7]) begin else if (phase[7]) begin
if (!per_type[2] && !en) per_type <= 3'h6; /// if (!per_type[2] && !en) per_type <= 3'h6;
if (!per_type[2] && !en) per_type <= 3'h7;
else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1; else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1;
end end
phase <= {phase[6:0], start | (phase[7] & (|per_type) )}; /// phase <= {phase[6:0], start | (phase[7] & (|per_type) & ~(&per_type))}; // both per_type 7 and 0 disables
phase <= {phase[6:0], start | (phase[7] & (|per_type))};
//TODO:
if (rst || start || phase[7]) phase_cnt <= 0; if (rst || start || phase[7]) phase_cnt <= 0;
else if (|phase[6:0]) phase_cnt <= phase_cnt + 1; else if (|phase[6:0]) phase_cnt <= phase_cnt + 1;
...@@ -343,8 +346,10 @@ module dct1d_chen#( ...@@ -343,8 +346,10 @@ module dct1d_chen#(
if (rst || !(en || (|phase))) pre_en_out <= 0; if (rst || !(en || (|phase))) pre_en_out <= 0;
else if (phase[3]) begin else if (phase[3]) begin
if (per_type == 2) pre_en_out <= 1; if (per_type == 2) pre_en_out <= 1;
else if (per_type[2]) pre_en_out <= 0; /// else if (per_type[2]) pre_en_out <= 0;
/// else if (&per_type[2:0]) pre_en_out <= 0;
else if (per_type[2:0]==0) pre_en_out <= 0;
end end
en_out <= pre_en_out; en_out <= pre_en_out;
......
dsp/dct1d_chen_reorder_out.v
View file @ 6ed7aef1
...@@ -75,14 +75,15 @@ module dct1d_chen_reorder_out#( ...@@ -75,14 +75,15 @@ module dct1d_chen_reorder_out#(
else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1; else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1;
end end
if (rst) pre_we_r <= 0; if (rst) pre_we_r <= 0;
else if (pre2_start) pre_we_r <= 1; else if (pre2_start) pre_we_r <= 1;
else if ((per_type == 0) || ((cntr_in==3) && per_type[2])) pre_we_r <= 0; /// else if ((per_type == 0) || ((cntr_in==3) && per_type[2])) pre_we_r <= 0;
else if ((per_type == 0) || ((cntr_in[2:0]==3) && per_type[2])) pre_we_r <= 0;
we_r <= pre_we_r; we_r <= pre_we_r;
if (rst) cntr_in <= 0; if (rst) cntr_in <= 0;
else if (pre2_start) cntr_in <= {~cntr_in[3],3'b0}; else if (pre2_start) cntr_in <= {~cntr_in[3],3'b0};
else if (pre_we_r) cntr_in <= cntr_in + 1; else if (pre_we_r) cntr_in <= cntr_in + 1;
case (cntr_in[2:0]) case (cntr_in[2:0])
3'h0: ina_rom <= {1'b0,3'h4}; 3'h0: ina_rom <= {1'b0,3'h4};
3'h1: ina_rom <= {1'b1,3'h1}; 3'h1: ina_rom <= {1'b1,3'h1};
...@@ -96,16 +97,19 @@ module dct1d_chen_reorder_out#( ...@@ -96,16 +97,19 @@ module dct1d_chen_reorder_out#(
if (we_r) reord_buf_ram[waddr] <= din; if (we_r) reord_buf_ram[waddr] <= din;
if ((per_type == 2) && (cntr_in == 1)) raddr <= {~cntr_in[3], 3'b0}; /// if ((per_type == 2) && (cntr_in == 1)) raddr <= {~cntr_in[3], 3'b0};
if ((per_type == 2) && (cntr_in[2:0] == 1)) raddr <= {~cntr_in[3], 3'b0};
else if ((raddr[2:0] != 0) || (per_type !=0)) raddr <= raddr + 1; else if ((raddr[2:0] != 0) || (per_type !=0)) raddr <= raddr + 1;
if (en_out_r) dout_r <= reord_buf_ram[raddr]; if (en_out_r) dout_r <= reord_buf_ram[raddr];
start_out_r <= (per_type == 2) && (cntr_in == 1); /// start_out_r <= (per_type == 2) && (cntr_in == 1);
start_out_r <= (per_type == 2) && (cntr_in[2:0] == 1);
if (rst ||(per_type == 0) ) en_out_r <= 0; if (rst ||(per_type == 0) ) en_out_r <= 0;
// else if (cntr_in == 1) en_out_r <= (per_type == 2) || !per_type[2]; // else if (cntr_in == 1) en_out_r <= (per_type == 2) || !per_type[2];
else if ((cntr_in == 1) && (per_type == 2)) en_out_r <= 1; /// else if ((cntr_in == 1) && (per_type == 2)) en_out_r <= 1;
else if ((cntr_in[2:0] == 1) && (per_type == 2)) en_out_r <= 1;
else if (stop_out && !en) en_out_r <= 0; else if (stop_out && !en) en_out_r <= 0;
//stop_out //stop_out
......
py393/x393_jpeg.py
View file @ 6ed7aef1
...@@ -768,7 +768,27 @@ class X393Jpeg(object): ...@@ -768,7 +768,27 @@ class X393Jpeg(object):
""" """
@return absolute path of the directory one above current script one @return absolute path of the directory one above current script one
""" """
return os.path.abspath(os.path.join(os.path.dirname(__file__), '../')) return os.path.abspath(os.path.join(os.path.dirname(__file__), '../'))
def jpeg_sim_multi(self,
num_rpt=1,
irq_mask = 0xf0,
irq_after=100,
irq_timeout = 100000,
file_path = "img@.jpeg"):
"""
Wait for ready, acquire and save next image, use img
@param num_rpt - numer of times to acquire next ready image
@param irq_mask - IRQ mask, 0xf0 - all 4 channels
@param irq_after- nanoseconds to wait after IRQ befor4e reading pointers
@param irq_timeout - time (in nanoseconds) to wait for interrupts
@param file_path - camera file system path (starts with "/") or relative to web server root,
@ is replaced with timestamp, -<chn> added before "."
"""
for _ in range (num_rpt):
self.x393_mem.wait_irq(irq_mask= irq_mask, wait_ns = irq_timeout)
self.x393_mem.wait_irq(irq_mask= 0, wait_ns = irq_after)
self.jpeg_write(file_path, "next")
def jpeg_write(self, def jpeg_write(self,
file_path = "img.jpeg", file_path = "img.jpeg",
channel = 0, channel = 0,
...@@ -1105,11 +1125,15 @@ compressor_control all None None None None None 2 ...@@ -1105,11 +1125,15 @@ compressor_control all None None None None None 2
compressor_interrupt_control all clr compressor_interrupt_control all clr
compressor_interrupt_control all en compressor_interrupt_control all en
compressor_control all 3 compressor_control all 3
jpeg_sim_multi 8
jpeg_sim_multi 8
wait_irq 0xf0 100000 wait_irq 0xf0 100000
wait_irq 0x0 100 wait_irq 0x0 100
jpeg_write "img@.jpeg" next jpeg_write "img@.jpeg" next
jpeg_write "/home/eyesis/git/x393-neon/www/img.jpeg" next jpeg_write "/home/eyesis/git/x393-neon/www/img.jpeg" next
x393 (localhost:7777) +107.289s--> compressor_control all None None None None None 2 x393 (localhost:7777) +107.289s--> compressor_control all None None None None None 2
......
py393/x393_mem.py
View file @ 6ed7aef1
...@@ -148,7 +148,7 @@ class X393Mem(object): ...@@ -148,7 +148,7 @@ class X393Mem(object):
X393_CLIENT.flush() X393_CLIENT.flush()
def wait_irq(self,irq_mask= 0, wait_ns = 1000): def wait_irq(self,irq_mask= 0, wait_ns = 1000):
""" """
Wait silation certain time, interruptible Wait simulation certain time (in ns), interruptible
@param irq_mask - mask to be AND-ed with interrupt vector @param irq_mask - mask to be AND-ed with interrupt vector
@param wait_ns - timeout in nanoseconds @param wait_ns - timeout in nanoseconds
""" """
......
simulation_modules/simul_axi_hp_rd.v
View file @ 6ed7aef1
...@@ -111,15 +111,6 @@ module simul_axi_hp_rd #( ...@@ -111,15 +111,6 @@ module simul_axi_hp_rd #(
wire [3:0] rd_qos_in; wire [3:0] rd_qos_in;
wire [3:0] rd_qos_out; wire [3:0] rd_qos_out;
/*
wire aw_nempty;
wire w_nempty;
wire enough_data; // enough data to start a new burst
wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
reg [31:0] write_address;
wire fifo_wd_rd; // read data fifo
wire last_confirmed_write;
*/
wire [5:0] arid_out; // verify it matches wid_out when outputting data wire [5:0] arid_out; // verify it matches wid_out when outputting data
wire [1:0] arburst_out; wire [1:0] arburst_out;
...@@ -141,7 +132,12 @@ module simul_axi_hp_rd #( ...@@ -141,7 +132,12 @@ module simul_axi_hp_rd #(
reg [3:0] read_left; reg [3:0] read_left;
reg [1:0] rburst; reg [1:0] rburst;
reg [3:0] rlen; reg [3:0] rlen;
`ifndef AXI_4K_LIMIT_DISABLE
wire [11:3] next_rd_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit) wire [11:3] next_rd_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
`else
wire [31:3] next_rd_address;
`endif
reg [31:0] read_address; reg [31:0] read_address;
wire last_confirmed_read; wire last_confirmed_read;
...@@ -205,11 +201,20 @@ module simul_axi_hp_rd #( ...@@ -205,11 +201,20 @@ module simul_axi_hp_rd #(
assign last_read = (read_left==0); assign last_read = (read_left==0);
assign last_confirmed_read = (read_left==0) && sim_rd_valid && sim_rd_ready; assign last_confirmed_read = (read_left==0) && sim_rd_valid && sim_rd_ready;
// AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer) // AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer)
// in 64 bit mode - low 3 bits are preserved, next 9 are incremented // in 64 bit mode - low 3 bits are preserved, next 9 are incremented
`ifndef AXI_4K_LIMIT_DISABLE
assign next_rd_address[11:3] = assign next_rd_address[11:3] =
rburst[1]? rburst[1]?
(rburst[0]? {9'bx}:((read_address[11:3] + 1) & {5'h1f, ~rlen[3:0]})): (rburst[0]? {9'bx}:((read_address[11:3] + 1) & {5'h1f, ~rlen[3:0]})):
(rburst[0]? (read_address[11:3]+1):(read_address[11:3])); (rburst[0]? (read_address[11:3]+1):(read_address[11:3]));
`else
assign next_rd_address[31:3] =
rburst[1]?
(rburst[0]? {29'bx}:((read_address[31:3] + 1) & {25'h1f, ~rlen[3:0]})):
(rburst[0]? (read_address[31:3]+1):(read_address[31:3]));
`endif
assign sim_rd_address = read_address; assign sim_rd_address = read_address;
assign sim_rid = arid_out; assign sim_rid = arid_out;
// Current model policy is not to initiate a new burst (read from simulation port) if it may overflow FIFO // Current model policy is not to initiate a new burst (read from simulation port) if it may overflow FIFO
...@@ -272,8 +277,11 @@ module simul_axi_hp_rd #( ...@@ -272,8 +277,11 @@ module simul_axi_hp_rd #(
if (rst) read_address <= 32'bx; if (rst) read_address <= 32'bx;
else if (start_read_burst_w) read_address <= araddr_out; // precedence over inc else if (start_read_burst_w) read_address <= araddr_out; // precedence over inc
`ifndef AXI_4K_LIMIT_DISABLE
else if (sim_rd_valid && sim_rd_ready) read_address <= {read_address[31:12],next_rd_address[11:3],read_address[2:0]}; else if (sim_rd_valid && sim_rd_ready) read_address <= {read_address[31:12],next_rd_address[11:3],read_address[2:0]};
`else
else if (sim_rd_valid && sim_rd_ready) read_address <= { next_rd_address[31:3],read_address[2:0]};
`endif
end end
......
simulation_modules/simul_axi_hp_wr.v
View file @ 6ed7aef1
...@@ -130,7 +130,11 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored ...@@ -130,7 +130,11 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
wire aw_nempty; wire aw_nempty;
wire w_nempty; wire w_nempty;
wire enough_data; // enough data to start a new burst wire enough_data; // enough data to start a new burst
`ifndef AXI_4K_LIMIT_DISABLE
wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit) wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
`else
wire [31:3] next_wr_address;
`endif
reg [31:0] write_address; reg [31:0] write_address;
reg [5:0] awid_r; // awid registered with write_address reg [5:0] awid_r; // awid registered with write_address
wire fifo_wd_rd; // read data fifo wire fifo_wd_rd; // read data fifo
...@@ -248,11 +252,19 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored ...@@ -248,11 +252,19 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
(aw_nempty && enough_data) || (write_in_progress && !last_confirmed_write); (aw_nempty && enough_data) || (write_in_progress && !last_confirmed_write);
// AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer) // AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer)
// in 64 bit mode - low 3 bits are preserved, next 9 are incremented // in 64 bit mode - low 3 bits are preserved, next 9 are incremented
// Seems that Zynq is OK to cross 4K boundary
`ifndef AXI_4K_LIMIT_DISABLE
assign next_wr_address[11:3] = assign next_wr_address[11:3] =
wburst[1]? wburst[1]?
(wburst[0]? {9'bx}:((write_address[11:3] + 1) & {5'h1f, ~wlen[3:0]})): (wburst[0]? {9'bx}:((write_address[11:3] + 1) & {5'h1f, ~wlen[3:0]})):
(wburst[0]? (write_address[11:3]+1):(write_address[11:3])); (wburst[0]? (write_address[11:3]+1):(write_address[11:3]));
`else
assign next_wr_address[31:3] =
wburst[1]?
(wburst[0]? {29'bx}:((write_address[31:3] + 1) & {25'h1f, ~wlen[3:0]})):
(wburst[0]? (write_address[31:3]+1):(write_address[31:3]));
`endif
assign sim_wr_data= wdata_out; assign sim_wr_data= wdata_out;
assign sim_wid= wid_out; assign sim_wid= wid_out;
assign sim_wr_stb=wstrb_out; assign sim_wr_stb=wstrb_out;
...@@ -305,8 +317,11 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored ...@@ -305,8 +317,11 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
if (rst) write_address <= 32'bx; if (rst) write_address <= 32'bx;
else if (start_write_burst_w) write_address <= awaddr_out; // precedence over inc else if (start_write_burst_w) write_address <= awaddr_out; // precedence over inc
`ifndef AXI_4K_LIMIT_DISABLE
else if (fifo_wd_rd) write_address <= {write_address[31:12],next_wr_address[11:3],write_address[2:0]}; else if (fifo_wd_rd) write_address <= {write_address[31:12],next_wr_address[11:3],write_address[2:0]};
`else
else if (fifo_wd_rd) write_address <= { next_wr_address[31:3],write_address[2:0]};
`endif
if (rst) awid_r <= 6'bx; if (rst) awid_r <= 6'bx;
else if (start_write_burst_w) awid_r <= awid_out; // precedence over inc else if (start_write_burst_w) awid_r <= awid_out; // precedence over inc
......
system_defines.vh
View file @ 6ed7aef1
...@@ -41,7 +41,12 @@ ...@@ -41,7 +41,12 @@
`ifndef SYSTEM_DEFINES `ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES `define SYSTEM_DEFINES
// TODO: Later compare instantiate/infer // TODO: Later compare instantiate/infer
`define INSTANTIATE_DSP48E1 `define INSTANTIATE_DSP48E1 // not yet tesetd/debugged otherwise
// https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
`define DEBUG_COMPRESSOR_SCRAMBLE
`define DEBUG_DCT1D // undefine after debugging is over `define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT // `define USE_OLD_DCT
......
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