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Commit 6a2bdfd7 authored by Andrey Filippov's avatar Andrey Filippov
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testing cocotb simulation, converting more simulation features

parent 98b0786f
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Showing with 892 additions and 314 deletions
cocotb/socket_command.py
View file @ 6a2bdfd7
...@@ -68,7 +68,7 @@ class SocketCommand(): ...@@ -68,7 +68,7 @@ class SocketCommand():
self.arguments=None self.arguments=None
class x393Client(): class x393Client():
def __init__(self, port=7777, host='localhost'): def __init__(self, host='localhost', port=7777):
self.PORT = port self.PORT = port
self.HOST = host # Symbolic name meaning all available interfaces self.HOST = host # Symbolic name meaning all available interfaces
self.cmd= SocketCommand() self.cmd= SocketCommand()
...@@ -87,11 +87,12 @@ class x393Client(): ...@@ -87,11 +87,12 @@ class x393Client():
print("stop->",self.communicate(self.cmd.toJSON())) print("stop->",self.communicate(self.cmd.toJSON()))
def write(self, address, data): def write(self, address, data):
self.cmd.setWrite([address,data]) self.cmd.setWrite([address,data])
print("write->",self.communicate(self.cmd.toJSON())) rslt = self.communicate(self.cmd.toJSON())
print("write->",rslt)
def read(self, address): def read(self, address):
self.cmd.setRead(address) self.cmd.setRead(address)
print("read->args",self.cmd.getArgs()) # print("read->args",self.cmd.getArgs())
rslt = self.communicate(self.cmd.toJSON()) rslt = self.communicate(self.cmd.toJSON())
print("read->",rslt) #print("read->",rslt)
return json.loads(rslt) return json.loads(rslt)
cocotb/x393_cocotb_02.sav
View file @ 6a2bdfd7
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Jul 4 03:19:05 2016 [*] Wed Jul 6 17:53:54 2016
[*] [*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160703211758949.fst" [dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160706092756207.fst"
[dumpfile_mtime] "Mon Jul 4 03:18:33 2016" [dumpfile_mtime] "Wed Jul 6 16:46:27 2016"
[dumpfile_size] 639043 [dumpfile_size] 26909872
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav" [savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
[timestart] 10924700 [timestart] 0
[size] 1836 1171 [size] 1836 1171
[pos] 1920 0 [pos] 1920 0
*-16.699684 11530000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-24.853212 32750000 32750000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 204 [treeopen] x393_dut.
[treeopen] x393_dut.simul_axi_master_wdata_i.
[sst_width] 357
[signals_width] 238 [signals_width] 238
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 344 [sst_vpaned_height] 484
@821 @820
x393_dut.TEST_TITLE[639:0] x393_dut.TEST_TITLE[639:0]
@c00200
-maxi0
@28 @28
x393_dut.dutm0_aclk x393_dut.dutm0_aclk
@22 @22
...@@ -86,6 +90,8 @@ x393_dut.dutm0_wid_w[11:0] ...@@ -86,6 +90,8 @@ x393_dut.dutm0_wid_w[11:0]
x393_dut.dutm0_wlast x393_dut.dutm0_wlast
x393_dut.dutm0_wlast_w x393_dut.dutm0_wlast_w
x393_dut.dutm0_wready x393_dut.dutm0_wready
@200
-
@22 @22
x393_dut.dutm0_wstb[3:0] x393_dut.dutm0_wstb[3:0]
x393_dut.dutm0_wstb_w[3:0] x393_dut.dutm0_wstb_w[3:0]
...@@ -95,5 +101,81 @@ x393_dut.dutm0_wvalid_w ...@@ -95,5 +101,81 @@ x393_dut.dutm0_wvalid_w
@22 @22
x393_dut.dutm0_xtra_blag[3:0] x393_dut.dutm0_xtra_blag[3:0]
x393_dut.dutm0_xtra_rdlag[3:0] x393_dut.dutm0_xtra_rdlag[3:0]
@1401200
-maxi0
@800200
-SENSOR1
@28
x393_dut.simul_sensor12bits_i.MCLK
@22
x393_dut.simul_sensor12bits_i.D[11:0]
@28
x393_dut.simul_sensor12bits_i.HACT
x393_dut.simul_sensor12bits_i.MRST
@29
x393_dut.simul_sensor12bits_i.ARST
@28
x393_dut.simul_sensor12bits_i.NMRST
x393_dut.simul_sensor12bits_i.stopped
x393_dut.simul_sensor12bits_i.DCLK
@200
-
@1000200
-SENSOR1
@800200
-axi_master_wdata
@28
x393_dut.simul_axi_master_wdata_i.clk
x393_dut.simul_axi_master_wdata_i.ready
x393_dut.simul_axi_master_wdata_i.reset
x393_dut.simul_axi_master_wdata_i.set_cmd
@22
x393_dut.simul_axi_master_wdata_i.wdata[31:0]
x393_dut.simul_axi_master_wdata_i.wdata_in[31:0]
x393_dut.simul_axi_master_wdata_i.wdata_out[31:0]
x393_dut.simul_axi_master_wdata_i.wid[11:0]
x393_dut.simul_axi_master_wdata_i.wid_in[11:0]
x393_dut.simul_axi_master_wdata_i.wid_out[11:0]
@28
x393_dut.simul_axi_master_wdata_i.wlast
x393_dut.simul_axi_master_wdata_i.wlast_in
x393_dut.simul_axi_master_wdata_i.wlast_out
x393_dut.simul_axi_master_wdata_i.wready
@22
x393_dut.simul_axi_master_wdata_i.wstrb[3:0]
x393_dut.simul_axi_master_wdata_i.wstrb_in[3:0]
x393_dut.simul_axi_master_wdata_i.wstrb_out[3:0]
@28
x393_dut.simul_axi_master_wdata_i.wvalid
x393_dut.simul_axi_master_wdata_i.wvalid_out
@200
-
@800200
-simul_axi_fifo
@8028
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.clk
@8022
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.data_in[48:0]
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.data_out[48:0]
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.in_address
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.in_count
@8028
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.input_ready
@8022
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.latency_delay[3:0]
@8028
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.latency_delay_r[2:0]
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.load
@8022
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.out_address
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.out_count
@8028
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.out_inc
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.ready
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.reset
x393_dut.simul_axi_master_wdata_i.simul_axi_fifo_i.valid
@1000200
-simul_axi_fifo
-axi_master_wdata
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
cocotb/x393_cocotb_server.py
View file @ 6a2bdfd7
...@@ -38,15 +38,30 @@ import logging ...@@ -38,15 +38,30 @@ import logging
class X393_cocotb_server(object): class X393_cocotb_server(object):
writeIDMask = (1 <<12) -1 writeIDMask = (1 <<12) -1
readIDMask = (1 <<12) -1 readIDMask = (1 <<12) -1
def __init__(self, dut, port, host): # , debug=False): started=False
def __init__(self, dut, port, host, mempath="memfile", autoflush=True): # , debug=False):
debug = os.getenv('COCOTB_DEBUG') # None/1 debug = os.getenv('COCOTB_DEBUG') # None/1
self.cmd= SocketCommand() self.cmd= SocketCommand()
self.dut = dut self.dut = dut
#initialize MAXIGP0 interface (main control/status registers, TODO: add MAXIGP1 for SATA)
self.maxigp0 = MAXIGPMaster(entity=dut, name="dutm0", clock=dut.dutm0_aclk, rdlag=0, blag=0) self.maxigp0 = MAXIGPMaster(entity=dut, name="dutm0", clock=dut.dutm0_aclk, rdlag=0, blag=0)
self.writeID=0 self.writeID=0
self.readID=0 self.readID=0
#initialize Zynq register access, has methods write_reg(a,d) and read_reg(a)
self.ps_sbus = PSBus(entity=dut, name="ps_sbus", clock=dut.ps_sbus_clk)
#Bus masters (communicated over mempath file
#Membridge to FPGA
self.saxihp0r = SAXIRdSim(entity=dut, name="saxihp0", clock=dut.axi_hclk, mempath = mempath, memhigh=0x40000000, data_bytes=8)
#Membridge from FPGA
self.saxihp0w = SAXIWrSim(entity=dut, name="saxihp0", clock=dut.axi_hclk, mempath = mempath, memhigh=0x40000000, data_bytes=8,
autoflush = autoflush, blatency=5)
#Compressors from FPGA
self.saxihp1w = SAXIWrSim(entity=dut, name="saxihp1", clock=dut.axi_hclk, mempath = mempath, memhigh=0x40000000, data_bytes=8,
autoflush = autoflush, blatency=5)
#histograms from FPGA
self.saxigp0 = SAXIWrSim(entity=dut, name="saxigp0", clock=dut.saxigp0, mempath = mempath, memhigh=0x40000000, data_bytes=4,
autoflush = autoflush, blatency=5)
level = logging.DEBUG if debug else logging.WARNING level = logging.DEBUG if debug else logging.WARNING
self.maxigp0.log.setLevel(level) self.maxigp0.log.setLevel(level)
...@@ -54,6 +69,7 @@ class X393_cocotb_server(object): ...@@ -54,6 +69,7 @@ class X393_cocotb_server(object):
self.PORT = port self.PORT = port
self.HOST = host # Symbolic name meaning all available interfaces self.HOST = host # Symbolic name meaning all available interfaces
self.socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM) self.socket_conn = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
self.socket_conn.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) # Otherwise restarting program will need 2 minutes
try: try:
self.socket_conn.bind((self.HOST, self.PORT)) self.socket_conn.bind((self.HOST, self.PORT))
self.dut._log.debug('Socket bind complete, HOST=%s, PORT=%d'%(self.HOST,self.PORT)) self.dut._log.debug('Socket bind complete, HOST=%s, PORT=%d'%(self.HOST,self.PORT))
...@@ -61,6 +77,9 @@ class X393_cocotb_server(object): ...@@ -61,6 +77,9 @@ class X393_cocotb_server(object):
self.dut._log.info ('Socket now listening to a single request on port %d: send command, receive response, close'%(self.PORT)) self.dut._log.info ('Socket now listening to a single request on port %d: send command, receive response, close'%(self.PORT))
except socket.error as msg: except socket.error as msg:
self.logErrorTerminate('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1])) self.logErrorTerminate('Bind failed. Error Code : %s Message %s'%( str(msg[0]),msg[1]))
def logErrorTerminate(self, msg): def logErrorTerminate(self, msg):
self.dut._log.error(msg) self.dut._log.error(msg)
...@@ -75,20 +94,22 @@ class X393_cocotb_server(object): ...@@ -75,20 +94,22 @@ class X393_cocotb_server(object):
self.dut._log.debug ("Connected with %s"%(soc_addr[0] + ':' + str(soc_addr[1]))) self.dut._log.debug ("Connected with %s"%(soc_addr[0] + ':' + str(soc_addr[1])))
#Sending message to connected client #Sending message to connected client
line = self.soc_conn.recv(4096) # or make it unlimited? line = self.soc_conn.recv(4096) # or make it unlimited?
self.dut._log.info("Received from socket: %s"%(line)) self.dut._log.debug("Received from socket: %s"%(line))
except: except:
self.logErrorTerminate("Socket seems to have died :-(") self.logErrorTerminate("Socket seems to have died :-(")
self.dut._log.info("1.Received from socket: %s"%(line)) self.dut._log.debug("1.Received from socket: %s"%(line))
yield self.executeCommand(line) yield self.executeCommand(line)
self.dut._log.debug("3.Received from socket: %s"%(line)) self.dut._log.debug("3.Received from socket: %s"%(line))
@cocotb.coroutine @cocotb.coroutine
def executeCommand(self,line): def executeCommand(self,line):
self.dut._log.info("1.executeCommand: %s"%(line)) self.dut._log.debug("1.executeCommand: %s"%(line))
if not line: if not line:
raise ReturnValue(None) raise ReturnValue(None)
self.dut._log.info("2.executeCommand: %s"%(line)) self.dut._log.debug("2.executeCommand: %s"%(line))
self.cmd.fromJSON(line) self.cmd.fromJSON(line)
#TODO: add interrupt related commands (including wait IRQ with timeout
if self.cmd.getStart(): if self.cmd.getStart():
self.dut._log.info('Received START, waiting reset to be over') self.dut._log.info('Received START, waiting reset to be over')
yield Timer(10000) yield Timer(10000)
...@@ -98,12 +119,18 @@ class X393_cocotb_server(object): ...@@ -98,12 +119,18 @@ class X393_cocotb_server(object):
while self.dut.reset_out.value: while self.dut.reset_out.value:
yield Timer(10000) yield Timer(10000)
# Launch all bus masters (no need to join ever, preserving just in case
self.self.saxihp0r_thread = cocotb.fork(saxihp0r.saxi_rd_run)
self.self.saxihp0w_thread = cocotb.fork(saxihp0w.saxi_wr_run)
self.self.saxihp1w_thread = cocotb.fork(saxihp1w.saxi_wr_run)
self.self.saxihp2w_thread = cocotb.fork(saxihp2w.saxi_wr_run)
self.soc_conn.send(self.cmd.toJSON(0)+"\n") self.soc_conn.send(self.cmd.toJSON(0)+"\n")
self.dut._log.debug('Sent 0 to the socket') self.dut._log.debug('Sent 0 to the socket')
started=True
elif self.cmd.getStop(): elif self.cmd.getStop():
self.dut._log.debug('Received STOP, closing...') self.dut._log.info('Received STOP, closing...')
self.soc_conn.send(self.cmd.toJSON(0)+"\n") self.soc_conn.send(self.cmd.toJSON(0)+"\n")
self.soc_conn.close() self.soc_conn.close()
yield Timer(10000) # small pause for the wave output yield Timer(10000) # small pause for the wave output
...@@ -111,36 +138,60 @@ class X393_cocotb_server(object): ...@@ -111,36 +138,60 @@ class X393_cocotb_server(object):
self.socket_conn.shutdown(socket.SHUT_RDWR) self.socket_conn.shutdown(socket.SHUT_RDWR)
self.socket_conn.close() self.socket_conn.close()
cocotb.regression.tear_down() cocotb.regression.tear_down()
started=False
raise TestSuccess('Terminating as received STOP command') raise TestSuccess('Terminating as received STOP command')
#For now write - one at a time, TODO: a) consolidate, b) decode address (some will be just a disk file) #For now write - one at a time, TODO: a) consolidate, b) decode address (some will be just a disk file)
elif self.cmd.getWrite(): elif self.cmd.getWrite():
ad = self.cmd.getWrite() ad = self.cmd.getWrite()
self.dut._log.info('Received WRITE, 0x%0x: %s'%(ad[0],str(ad[1]))) self.dut._log.info('Received WRITE, 0x%0x: %s'%(ad[0],str(ad[1])))
rslt = yield self.maxigp0.axi_write(address = ad[0], if ad[0] < 0x40000000:
value = ad[1], pass
byte_enable = None, elif(ad[0] >= 0x40000000) and (ad[0] < 0x80000000):
id = self.writeID, rslt = yield self.maxigp0.axi_write(address = ad[0],
dsize = 2, value = ad[1],
burst = 1, byte_enable = None,
address_latency = 0, id = self.writeID,
data_latency = 0) dsize = 2,
self.dut._log.info('maxigp0.axi_write yielded %s'%(str(rslt))) burst = 1,
self.writeID = (self.writeID+1) & self.writeIDMask address_latency = 0,
data_latency = 0)
self.dut._log.info('maxigp0.axi_write yielded %s'%(str(rslt)))
self.writeID = (self.writeID+1) & self.writeIDMask
elif ad[0] >= 0xc0000000:
self.ps_sbus.write_reg(ad[0],ad[1][0])
rslt = 0
else:
self.dut._log.info('Write address 0x%08x is outside of maxgp0, not yet supported'%(ad[0]))
rslt = 0
self.soc_conn.send(self.cmd.toJSON(rslt)+"\n") self.soc_conn.send(self.cmd.toJSON(rslt)+"\n")
self.dut._log.debug('Sent rslt to the socket') self.dut._log.debug('Sent rslt to the socket')
elif self.cmd.getRead(): elif self.cmd.getRead():
a = self.cmd.getRead() a = self.cmd.getRead()
dval = yield self.maxigp0.axi_read(address = a, if a < 0x40000000:
id = self.readID, pass
dlen = 1, if(a >= 0x40000000) and (a < 0x80000000):
dsize = 2, dval = yield self.maxigp0.axi_read(address = a,
address_latency = 0, id = self.readID,
data_latency = 0 ) dlen = 1,
self.dut._log.info("axi_read returned => " +str(dval)) dsize = 2,
self.readID = (self.readID+1) & self.readIDMask address_latency = 0,
data_latency = 0 )
self.dut._log.info("axi_read returned => " +str(dval))
self.readID = (self.readID+1) & self.readIDMask
elif ad[0] >= 0xc0000000:
dval = yield self.ps_sbus.read_reg(ad[0])
else:
self.dut._log.info('Read address 0x%08x is outside of maxgp0, not yet supported'%(a))
dval = [0]
self.soc_conn.send(self.cmd.toJSON(dval)+"\n") self.soc_conn.send(self.cmd.toJSON(dval)+"\n")
self.dut._log.debug('Sent dval to the socket') self.dut._log.debug('Sent dval to the socket')
def flush_all(self):
self.self.saxihp0w.flush()
self.self.saxihp1w.flush()
self.self.saxihp2w.flush()
def convert_string(txt): def convert_string(txt):
number=0 number=0
for c in txt: for c in txt:
...@@ -154,7 +205,7 @@ def run_test(dut, port=7777): ...@@ -154,7 +205,7 @@ def run_test(dut, port=7777):
while True: while True:
try: try:
rslt= yield tb.receiveCommandFromSocket() rslt= yield tb.receiveCommandFromSocket()
dut._log.info("rslt = %s"%(str(rslt))) dut._log.debug("rslt = %s"%(str(rslt)))
except ReturnValue as rv: except ReturnValue as rv:
line = rv.retval; line = rv.retval;
dut._log.info("rv = %s"%(str(rv))) dut._log.info("rv = %s"%(str(rv)))
......
cocotb/x393_dut.v
View file @ 6a2bdfd7
...@@ -91,6 +91,62 @@ module x393_dut#( ...@@ -91,6 +91,62 @@ module x393_dut#(
output dutm0_bready,// internally generated as a slow response to dutm0_bvalid. Cn be moved to Python and made input here output dutm0_bready,// internally generated as a slow response to dutm0_bvalid. Cn be moved to Python and made input here
output [11:0] dutm0_bid, output [11:0] dutm0_bid,
output [1:0] dutm0_bresp, output [1:0] dutm0_bresp,
// SAXIHP* R/W control register access (internal address decoders)
output ps_sbus_clk, // =hclk
input [31:0] ps_sbus_addr,
input ps_sbus_wr,
input ps_sbus_rd,
input [31:0] ps_sbus_din,
output [31:0] ps_sbus_dout,
output axi_hclk, // Clock for AXI interfaces
output saxi0_aclk, //== hclk
// Membridge FPGA -> CPU
output [31:0] saxihp0_wr_address,
output [ 5:0] saxihp0_wid,
output saxihp0_wr_valid,
input saxihp0_wr_ready,
output [63:0] saxihp0_wr_data,
output [7:0] saxihp0_wr_stb,
input [3:0] saxihp0_bresp_latency,
output [2:0] saxihp0_wr_cap,
output [3:0] saxihp0_wr_qos,
// Membridge CPU -> FPGA
output [31:0] saxihp0_rd_address,
output [ 5:0] saxihp0_rid,
input saxihp0_rd_valid,
output saxihp0_rd_ready,
input [63:0] saxihp0_rd_data,
input [1:0] saxihp0_rd_resp,
output [2:0] saxihp0_rd_cap,
output [3:0] saxihp0_rd_qos,
// Compressed images FPGA -> CPU
output [31:0] saxihp1_wr_address,
output [ 5:0] saxihp1_wid,
output saxihp1_wr_valid,
input saxihp1_wr_ready,
output [63:0] saxihp1_wr_data,
output [7:0] saxihp1_wr_stb,
input [3:0] saxihp1_bresp_latency,
output [2:0] saxihp1_wr_cap,
output [3:0] saxihp1_wr_qos,
// Histograms FPGA -> CPU
output [31:0] saxigp0_wr_address,
output [ 5:0] saxigp0_wid,
output saxigp0_wr_valid,
input saxigp0_wr_ready,
output [31:0] saxigp0_wr_data,
output [3:0] saxigp0_wr_stb,
output [1:0] saxigp0_wr_size,
input [3:0] saxigp0_bresp_latency,
output [3:0] saxigp0_wr_qos,
output [NUM_INTERRUPTS-1:0] irq_r, // {x393_i.sata_irq, x393_i.cmprs_irq[3:0], x393_i.frseq_irq[3:0]};
// SATA and SATA clock I/O // SATA and SATA clock I/O
input [3:0] dutm0_xtra_rdlag, // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid) input [3:0] dutm0_xtra_rdlag, // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
...@@ -108,6 +164,13 @@ module x393_dut#( ...@@ -108,6 +164,13 @@ module x393_dut#(
); );
assign irq_r = {x393_i.sata_irq, x393_i.cmprs_irq[3:0], x393_i.frseq_irq[3:0]};
assign axi_hclk = x393_i.ps7_i.SAXIHP0ACLK; // 150 MHz
assign saxi0_aclk = x393_i.ps7_i.SAXIGP0ACLK; // == hclk, 150MHz
assign ps_sbus_clk = x393_i.ps7_i.SAXIHP0ACLK; // == hclk
// Temporary = to be moved to Python? // Temporary = to be moved to Python?
// MAXIGP0 AXI interface // MAXIGP0 AXI interface
...@@ -170,7 +233,7 @@ module x393_dut#( ...@@ -170,7 +233,7 @@ module x393_dut#(
assign dutm0_rlast= maxigp0rlast; assign dutm0_rlast= maxigp0rlast;
reg [11:0] LAST_ARID; // last issued ARID // reg [11:0] LAST_ARID; // last issued ARID
// SuppressWarnings VEditor : assigned in $readmem() system task // SuppressWarnings VEditor : assigned in $readmem() system task
wire [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR_W; wire [SIMUL_AXI_READ_WIDTH-1:0] SIMUL_AXI_ADDR_W;
...@@ -188,8 +251,6 @@ module x393_dut#( ...@@ -188,8 +251,6 @@ module x393_dut#(
reg WAITING_STATUS; // tasks are waiting for status reg WAITING_STATUS; // tasks are waiting for status
// SuppressWarnings VEditor all - these variables are just for viewing, not used anywhere else // SuppressWarnings VEditor all - these variables are just for viewing, not used anywhere else
reg DEBUG1, DEBUG2, DEBUG3; reg DEBUG1, DEBUG2, DEBUG3;
reg [11:0] GLOBAL_WRITE_ID=0;
reg [11:0] GLOBAL_READ_ID=0;
// reg [7:0] target_phase=0; // to compare/wait for phase shifter ready // reg [7:0] target_phase=0; // to compare/wait for phase shifter ready
// End of Temporary = to be moved to Python? // End of Temporary = to be moved to Python?
...@@ -307,7 +368,6 @@ module x393_dut#( ...@@ -307,7 +368,6 @@ module x393_dut#(
`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh `include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
`endif `endif
parameter NUM_INTERRUPTS = 9;
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used `include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
// ========================== parameters from x353 =================================== // ========================== parameters from x353 ===================================
...@@ -329,11 +389,9 @@ parameter NUM_INTERRUPTS = 9; ...@@ -329,11 +389,9 @@ parameter NUM_INTERRUPTS = 9;
parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 8; // 1; //8; parameter BLANK_ROWS_AFTER= 8; // 1; //8;
`endif `endif
parameter WOI_HEIGHT= 32;
parameter TRIG_LINES= 8; parameter TRIG_LINES= 8;
parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used
`ifdef PF `ifdef PF
parameter PF_HEIGHT=8; parameter PF_HEIGHT=8;
parameter FULL_HEIGHT=WOI_HEIGHT; parameter FULL_HEIGHT=WOI_HEIGHT;
...@@ -343,7 +401,6 @@ parameter NUM_INTERRUPTS = 9; ...@@ -343,7 +401,6 @@ parameter NUM_INTERRUPTS = 9;
parameter FULL_HEIGHT=WOI_HEIGHT+4; parameter FULL_HEIGHT=WOI_HEIGHT+4;
parameter PF_STRIPES=0; // SuppressThisWarning VEditor - not used parameter PF_STRIPES=0; // SuppressThisWarning VEditor - not used
`endif `endif
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK; parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK;
parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
...@@ -645,117 +702,20 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -645,117 +702,20 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire ffclk1n; // input wire ffclk1n; // input
// axi_hp simulation signals
wire HCLK;
wire [31:0] afi_sim_rd_address; // output[31:0]
wire [ 5:0] afi_sim_rid; // output[5:0] SuppressThisWarning VEditor - not used - just view
// reg afi_sim_rd_valid; // input
wire afi_sim_rd_valid; // input
wire afi_sim_rd_ready; // output
// reg [63:0] afi_sim_rd_data; // input[63:0]
wire [63:0] afi_sim_rd_data; // input[63:0]
wire [ 2:0] afi_sim_rd_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_rd_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
wire [ 1:0] afi_sim_rd_resp; // input[1:0]
// reg [ 1:0] afi_sim_rd_resp; // input[1:0]
wire [31:0] afi_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 5:0] afi_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
wire afi_sim_wr_valid; // output
wire afi_sim_wr_ready; // input
// reg afi_sim_wr_ready; // input
wire [63:0] afi_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
wire [ 7:0] afi_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_bresp_latency; // input[3:0]
// reg [ 3:0] afi_sim_bresp_latency; // input[3:0]
wire [ 2:0] afi_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
assign HCLK = x393_i.ps7_i.SAXIHP0ACLK; // shortcut name
wire [31:0] afi1_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 5:0] afi1_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
wire afi1_sim_wr_valid; // output
wire afi1_sim_wr_ready; // input
// reg afi1_sim_wr_ready; // input
wire [63:0] afi1_sim_wr_data; // output[63:0] SuppressThisWarning VEditor - not used - just view
wire [ 7:0] afi1_sim_wr_stb; // output[7:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi1_sim_bresp_latency; // input[3:0]
// reg [ 3:0] afi1_sim_bresp_latency; // input[3:0]
wire [ 2:0] afi1_sim_wr_cap; // output[2:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] afi1_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
wire [31:0] sim_cmprs0_addr = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h0))?afi1_sim_wr_address:32'bz; // SuppressThisWarning VEditor - not used - just view
wire [31:0] sim_cmprs1_addr = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h1))?afi1_sim_wr_address:32'bz; // SuppressThisWarning VEditor - not used - just view
wire [31:0] sim_cmprs2_addr = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h2))?afi1_sim_wr_address:32'bz; // SuppressThisWarning VEditor - not used - just view
wire [31:0] sim_cmprs3_addr = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h3))?afi1_sim_wr_address:32'bz; // SuppressThisWarning VEditor - not used - just view
wire [63:0] sim_cmprs0_data = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h0))?afi1_sim_wr_data:64'bz; // SuppressThisWarning VEditor - not used - just view
wire [63:0] sim_cmprs1_data = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h1))?afi1_sim_wr_data:64'bz; // SuppressThisWarning VEditor - not used - just view
wire [63:0] sim_cmprs2_data = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h2))?afi1_sim_wr_data:64'bz; // SuppressThisWarning VEditor - not used - just view
wire [63:0] sim_cmprs3_data = (afi1_sim_wr_valid && afi1_sim_wr_ready && (afi1_sim_wid[1:0] == 2'h3))?afi1_sim_wr_data:64'bz; // SuppressThisWarning VEditor - not used - just view
//x393_i.ps7_i.SAXIHP1ACLK
always @ (posedge x393_i.ps7_i.SAXIHP1ACLK) if (afi1_sim_wr_valid && afi1_sim_wr_ready) begin
if (afi1_sim_wid[1:0] == 2'h0) $display("---sim_cmprs0: %x:%x", afi1_sim_wr_address, afi1_sim_wr_data);
if (afi1_sim_wid[1:0] == 2'h1) $display("---sim_cmprs1: %x:%x", afi1_sim_wr_address, afi1_sim_wr_data);
if (afi1_sim_wid[1:0] == 2'h2) $display("---sim_cmprs2: %x:%x", afi1_sim_wr_address, afi1_sim_wr_data);
if (afi1_sim_wid[1:0] == 2'h3) $display("---sim_cmprs3: %x:%x", afi1_sim_wr_address, afi1_sim_wr_data);
end
// afi loopback (membridge)
assign #1 afi_sim_rd_data= afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1, 2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;
assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
assign #1 afi_sim_wr_ready = afi_sim_wr_valid;
assign #1 afi_sim_bresp_latency=4'h5;
// afi1 (compressor) loopback
assign #1 afi1_sim_wr_ready = afi1_sim_wr_valid;
assign #1 afi1_sim_bresp_latency=4'h5;
// SAXI_GP0 - histograms to system memory
wire SAXI_GP0_CLK;
wire [31:0] saxi_gp0_sim_wr_address; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 5:0] saxi_gp0_sim_wid; // output[5:0] SuppressThisWarning VEditor - not used - just view
wire saxi_gp0_sim_wr_valid; // output
wire saxi_gp0_sim_wr_ready; // input
wire [31:0] saxi_gp0_sim_wr_data; // output[31:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] saxi_gp0_sim_wr_stb; // output[3:0] SuppressThisWarning VEditor - not used - just view
wire [ 1:0] saxi_gp0_sim_wr_size; // output[1:0] SuppressThisWarning VEditor - not used - just view
wire [ 3:0] saxi_gp0_sim_bresp_latency; // input[3:0]
wire [ 3:0] saxi_gp0_sim_wr_qos; // output[3:0] SuppressThisWarning VEditor - not used - just view
assign SAXI_GP0_CLK = x393_i.ps7_i.SAXIGP0ACLK;
assign #1 saxi_gp0_sim_wr_ready = saxi_gp0_sim_wr_valid;
assign #1 saxi_gp0_sim_bresp_latency=4'h5;
// axi_hp register access // axi_hp register access
// PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits // PS memory mapped registers to read/write over a separate simulation bus running at HCLK, no waits
reg [31:0] PS_REG_ADDR; wire [31:0] ps_reg_dout0w;
reg PS_REG_WR; wire [31:0] ps_reg_dout0r;
reg PS_REG_RD; wire [31:0] ps_reg_dout1w;
reg PS_REG_WR1; // wire [31:0] ps_reg_dout2w; // Unused
reg PS_REG_RD1; wire ps_reg_dvalid0w;
reg [31:0] PS_REG_DIN; wire ps_reg_dvalid0r;
wire [31:0] PS_REG_DOUT; wire ps_reg_dvalid1w;
reg [31:0] PS_RDATA; // SuppressThisWarning VEditor - not used - just view // wire ps_reg_dvalid2w; // Unused
wire [31:0] PS_REG_DOUT1; assign ps_sbus_dout = {32{ps_reg_dvalid0w}} & ps_reg_dout0w &
initial begin {32{ps_reg_dvalid0r}} & ps_reg_dout0r &
PS_REG_ADDR <= 'bx; {32{ps_reg_dvalid1w}} & ps_reg_dout1w;
PS_REG_WR <= 0; // & {32{ps_reg_dvalid2w}} & ps_reg_dout2w;
PS_REG_RD <= 0;
PS_REG_WR1 <= 0;
PS_REG_RD1 <= 0;
PS_REG_DIN <= 'bx;
PS_RDATA <= 'bx;
end
always @ (posedge HCLK) begin
if (PS_REG_RD) PS_RDATA <= PS_REG_DOUT;
else if (PS_REG_RD1) PS_RDATA <= PS_REG_DOUT1;
end
// reg [639:0] TEST_TITLE="abcdef"; //S uppressThisWarning VEditor May use again later // reg [639:0] TEST_TITLE="abcdef"; //S uppressThisWarning VEditor May use again later
// Simulation signals // Simulation signals
...@@ -782,13 +742,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -782,13 +742,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire [3:0] IRQ_CMPRS_S = IRQ_S[7:4]; wire [3:0] IRQ_CMPRS_S = IRQ_S[7:4];
wire IRQ_SATA_S = IRQ_S[8];// SuppressThisWarning VEditor - not used wire IRQ_SATA_S = IRQ_S[8];// SuppressThisWarning VEditor - not used
// Simulation modules interconnection
// integer NUM_WORDS_READ;
integer NUM_WORDS_EXPECTED;
// reg [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
// reg [31:0] DEBUG_DATA; //S uppressThisWarning VEditor : just for simulation viewing
// integer DEBUG_ADDRESS; //S uppressThisWarning VEditor : just for simulation viewing
assign reset_out = RST || x393_i.arst; assign reset_out = RST || x393_i.arst;
x393 #( x393 #(
...@@ -1242,19 +1195,21 @@ simul_axi_hp_rd #( ...@@ -1242,19 +1195,21 @@ simul_axi_hp_rd #(
.rcount (x393_i.ps7_i.SAXIHP0RCOUNT), // output[7:0] .rcount (x393_i.ps7_i.SAXIHP0RCOUNT), // output[7:0]
.racount (x393_i.ps7_i.SAXIHP0RACOUNT), // output[2:0] .racount (x393_i.ps7_i.SAXIHP0RACOUNT), // output[2:0]
.rdissuecap1en (x393_i.ps7_i.SAXIHP0RDISSUECAP1EN), // input .rdissuecap1en (x393_i.ps7_i.SAXIHP0RDISSUECAP1EN), // input
.sim_rd_address (afi_sim_rd_address), // output[31:0] .sim_rd_address (saxihp0_rd_address), // output[31:0]
.sim_rid (afi_sim_rid), // output[5:0] .sim_rid (saxihp0_rid), // output[5:0]
.sim_rd_valid (afi_sim_rd_valid), // input .sim_rd_valid (saxihp0_rd_valid), // input
.sim_rd_ready (afi_sim_rd_ready), // output .sim_rd_ready (saxihp0_rd_ready), // output
.sim_rd_data (afi_sim_rd_data), // input[63:0] .sim_rd_data (saxihp0_rd_data), // input[63:0]
.sim_rd_cap (afi_sim_rd_cap), // output[2:0] .sim_rd_cap (saxihp0_rd_cap), // output[2:0]
.sim_rd_qos (afi_sim_rd_qos), // output[3:0] .sim_rd_qos (saxihp0_rd_qos), // output[3:0]
.sim_rd_resp (afi_sim_rd_resp), // input[1:0] .sim_rd_resp (saxihp0_rd_resp), // input[1:0]
.reg_addr (PS_REG_ADDR), // input[31:0] .reg_addr (ps_sbus_addr), // input[31:0]
.reg_wr (PS_REG_WR), // input .reg_wr (ps_sbus_wr), // input
.reg_rd (PS_REG_RD), // input .reg_rd (ps_sbus_rd), // input
.reg_din (PS_REG_DIN), // input[31:0] .reg_din (ps_sbus_din), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0] .reg_dout (ps_reg_dout0r), // output[31:0]
.reg_dvalid (ps_reg_dvalid0r)
); );
simul_axi_hp_wr #( simul_axi_hp_wr #(
...@@ -1287,20 +1242,21 @@ simul_axi_hp_wr #( ...@@ -1287,20 +1242,21 @@ simul_axi_hp_wr #(
.wcount (x393_i.ps7_i.SAXIHP0WCOUNT), // output[7:0] .wcount (x393_i.ps7_i.SAXIHP0WCOUNT), // output[7:0]
.wacount (x393_i.ps7_i.SAXIHP0WACOUNT), // output[5:0] .wacount (x393_i.ps7_i.SAXIHP0WACOUNT), // output[5:0]
.wrissuecap1en (x393_i.ps7_i.SAXIHP0WRISSUECAP1EN), // input .wrissuecap1en (x393_i.ps7_i.SAXIHP0WRISSUECAP1EN), // input
.sim_wr_address (afi_sim_wr_address), // output[31:0] .sim_wr_address (saxihp0_wr_address), // output[31:0]
.sim_wid (afi_sim_wid), // output[5:0] .sim_wid (saxihp0_wid), // output[5:0]
.sim_wr_valid (afi_sim_wr_valid), // output .sim_wr_valid (saxihp0_wr_valid), // output
.sim_wr_ready (afi_sim_wr_ready), // input .sim_wr_ready (saxihp0_wr_ready), // input
.sim_wr_data (afi_sim_wr_data), // output[63:0] .sim_wr_data (saxihp0_wr_data), // output[63:0]
.sim_wr_stb (afi_sim_wr_stb), // output[7:0] .sim_wr_stb (saxihp0_wr_stb), // output[7:0]
.sim_bresp_latency(afi_sim_bresp_latency), // input[3:0] .sim_bresp_latency(saxihp0_bresp_latency), // input[3:0]
.sim_wr_cap (afi_sim_wr_cap), // output[2:0] .sim_wr_cap (saxihp0_wr_cap), // output[2:0]
.sim_wr_qos (afi_sim_wr_qos), // output[3:0] .sim_wr_qos (saxihp0_wr_qos), // output[3:0]
.reg_addr (PS_REG_ADDR), // input[31:0] .reg_addr (ps_sbus_addr), // input[31:0]
.reg_wr (PS_REG_WR), // input .reg_wr (ps_sbus_wr), // input
.reg_rd (PS_REG_RD), // input .reg_rd (ps_sbus_rd), // input
.reg_din (PS_REG_DIN), // input[31:0] .reg_din (ps_sbus_din), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0] .reg_dout (ps_reg_dout0w), // output[31:0]
.reg_dvalid (ps_reg_dvalid0w) // output
); );
// afi1 - from compressor // afi1 - from compressor
simul_axi_hp_wr #( simul_axi_hp_wr #(
...@@ -1333,26 +1289,27 @@ simul_axi_hp_wr #( ...@@ -1333,26 +1289,27 @@ simul_axi_hp_wr #(
.wcount (x393_i.ps7_i.SAXIHP1WCOUNT), // output[7:0] .wcount (x393_i.ps7_i.SAXIHP1WCOUNT), // output[7:0]
.wacount (x393_i.ps7_i.SAXIHP1WACOUNT), // output[5:0] .wacount (x393_i.ps7_i.SAXIHP1WACOUNT), // output[5:0]
.wrissuecap1en (x393_i.ps7_i.SAXIHP1WRISSUECAP1EN), // input .wrissuecap1en (x393_i.ps7_i.SAXIHP1WRISSUECAP1EN), // input
.sim_wr_address (afi1_sim_wr_address), // output[31:0] .sim_wr_address (saxihp1_wr_address), // output[31:0]
.sim_wid (afi1_sim_wid), // output[5:0] .sim_wid (saxihp1_wid), // output[5:0]
.sim_wr_valid (afi1_sim_wr_valid), // output .sim_wr_valid (saxihp1_wr_valid), // output
.sim_wr_ready (afi1_sim_wr_ready), // input .sim_wr_ready (saxihp1_wr_ready), // input
.sim_wr_data (afi1_sim_wr_data), // output[63:0] .sim_wr_data (saxihp1_wr_data), // output[63:0]
.sim_wr_stb (afi1_sim_wr_stb), // output[7:0] .sim_wr_stb (saxihp1_wr_stb), // output[7:0]
.sim_bresp_latency(afi1_sim_bresp_latency), // input[3:0] .sim_bresp_latency(saxihp1_bresp_latency), // input[3:0]
.sim_wr_cap (afi1_sim_wr_cap), // output[2:0] .sim_wr_cap (saxihp1_wr_cap), // output[2:0]
.sim_wr_qos (afi1_sim_wr_qos), // output[3:0] .sim_wr_qos (saxihp1_wr_qos), // output[3:0]
.reg_addr (PS_REG_ADDR), // input[31:0] .reg_addr (ps_sbus_addr), // input[31:0]
.reg_wr (PS_REG_WR1), // input .reg_wr (ps_sbus_wr), // input
.reg_rd (PS_REG_RD1), // input .reg_rd (ps_sbus_rd), // input
.reg_din (PS_REG_DIN), // input[31:0] .reg_din (ps_sbus_din), // input[31:0]
.reg_dout (PS_REG_DOUT1) // output[31:0] .reg_dout (ps_reg_dout1w), // output[31:0]
.reg_dvalid (ps_reg_dvalid1w) // output
); );
// SAXI_GP0 - histograms to system memory // SAXI_GP0 - histograms to system memory
simul_saxi_gp_wr simul_saxi_gp0_wr_i ( simul_saxi_gp_wr simul_saxi_gp0_wr_i (
.rst (RST), // input .rst (RST), // input
.aclk (SAXI_GP0_CLK), // input .aclk (saxi0_aclk), // input
.aresetn (), // output .aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIGP0AWADDR), // input[31:0] .awaddr (x393_i.ps7_i.SAXIGP0AWADDR), // input[31:0]
.awvalid (x393_i.ps7_i.SAXIGP0AWVALID), // input .awvalid (x393_i.ps7_i.SAXIGP0AWVALID), // input
...@@ -1375,15 +1332,15 @@ simul_axi_hp_wr #( ...@@ -1375,15 +1332,15 @@ simul_axi_hp_wr #(
.bready (x393_i.ps7_i.SAXIGP0BREADY), // input .bready (x393_i.ps7_i.SAXIGP0BREADY), // input
.bid (x393_i.ps7_i.SAXIGP0BID), // output[5:0] .bid (x393_i.ps7_i.SAXIGP0BID), // output[5:0]
.bresp (x393_i.ps7_i.SAXIGP0BRESP), // output[1:0] .bresp (x393_i.ps7_i.SAXIGP0BRESP), // output[1:0]
.sim_wr_address (saxi_gp0_sim_wr_address), // output[31:0] .sim_wr_address (saxigp0_wr_address), // output[31:0]
.sim_wid (saxi_gp0_sim_wid), // output[5:0] .sim_wid (saxigp0_wid), // output[5:0]
.sim_wr_valid (saxi_gp0_sim_wr_valid), // output .sim_wr_valid (saxigp0_wr_valid), // output
.sim_wr_ready (saxi_gp0_sim_wr_ready), // input .sim_wr_ready (saxigp0_wr_ready), // input
.sim_wr_data (saxi_gp0_sim_wr_data), // output[31:0] .sim_wr_data (saxigp0_wr_data), // output[31:0]
.sim_wr_stb (saxi_gp0_sim_wr_stb), // output[3:0] .sim_wr_stb (saxigp0_wr_stb), // output[3:0]
.sim_wr_size (saxi_gp0_sim_wr_size), // output[1:0] .sim_wr_size (saxigp0_wr_size), // output[1:0]
.sim_bresp_latency (saxi_gp0_sim_bresp_latency), // input[3:0] .sim_bresp_latency (saxigp0_bresp_latency), // input[3:0]
.sim_wr_qos (saxi_gp0_sim_wr_qos) // output[3:0] .sim_wr_qos (saxigp0_wr_qos) // output[3:0]
); );
...@@ -1723,13 +1680,17 @@ simul_axi_hp_wr #( ...@@ -1723,13 +1680,17 @@ simul_axi_hp_wr #(
RST_CLEAN = 1; RST_CLEAN = 1;
RST = 1'bx; RST = 1'bx;
$display("%t %s:%d RST=1'bx",$time,`__FILE__,`__LINE__);
#500; #500;
RST = 1'b1; RST = 1'b1;
$display("%t %s:%d RST=1'b1",$time,`__FILE__,`__LINE__);
#9000; // same as glbl #9000; // same as glbl
repeat (20) @(posedge CLK) ; repeat (20) @(posedge CLK) ;
RST =1'b0; RST =1'b0;
$display("%t %s:%d RST=1'b0",$time,`__FILE__,`__LINE__);
@(posedge CLK) ; @(posedge CLK) ;
RST_CLEAN = 0; RST_CLEAN = 0;
$display("%t %s:%d RST_CLEAN=1'b0",$time,`__FILE__,`__LINE__);
// IRQ-related // IRQ-related
IRQ_EN = 1; IRQ_EN = 1;
IRQ_M = 0; IRQ_M = 0;
...@@ -1737,9 +1698,11 @@ simul_axi_hp_wr #( ...@@ -1737,9 +1698,11 @@ simul_axi_hp_wr #(
IRQ_CMPRS_DONE = 0; IRQ_CMPRS_DONE = 0;
IRQ_SATA_DONE = 0; IRQ_SATA_DONE = 0;
#5000; #5000;
$finish; // Need to killall vvp
// $finish;
end end
//localparam file = `__FILE__;
//localparam line = `__LINE__;
assign x393_i.ps7_i.FCLKCLK= {4{CLK}}; assign x393_i.ps7_i.FCLKCLK= {4{CLK}};
assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST}; assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
......
cocotb/x393interfaces.py
View file @ 6a2bdfd7
...@@ -60,8 +60,11 @@ from cocotb.drivers import BusDriver ...@@ -60,8 +60,11 @@ from cocotb.drivers import BusDriver
from cocotb.result import ReturnValue from cocotb.result import ReturnValue
from cocotb.binary import BinaryValue from cocotb.binary import BinaryValue
import re
import binascii import binascii
import array import array
import struct
#channels #channels
AR_CHN="AR" AR_CHN="AR"
AW_CHN="AW" AW_CHN="AW"
...@@ -69,9 +72,283 @@ R_CHN="R" ...@@ -69,9 +72,283 @@ R_CHN="R"
W_CHN="W" W_CHN="W"
B_CHN="B" B_CHN="B"
def _float_signals(self,signals):
if not isinstance (signals,(list,tuple)):
signals = (signals,)
for signal in signals:
v = signal.value
v.binstr = "z" * len(signal)
signal <= v
class MAXIGPReadError(Exception): class MAXIGPReadError(Exception):
# print ("MAXIGPReadError") # print ("MAXIGPReadError")
pass pass
class PSBus(BusDriver):
"""
Small subset of Zynq registers, used to access SAXI_HP* registers
"""
_signals=[ # i/o from the DUT side
clk, # output
addr, # input [31:0]
wr, # input
rd, # input
din, # input [31:0]
dout] #output [31:0]
def __init__(self, entity, name, clock):
BusDriver.__init__(self, entity, name, clock)
self.busy_channel = Lock("%s_busy"%(name))
self.bus.wr.setimmediatevalue(0)
self.bus.rd.setimmediatevalue(0)
_float_signals((self.bus.addr, self.bus.din))
@cocotb.coroutine
def write_reg(self,addr,data):
yield self.busy_channel.acquire()
#Only wait if it is too late (<1/2 cycle)
if not int(self.clock):
yield RisingEdge(self.clock)
self.bus.addr <= addr
self.bus.din <= data
self.bus.wr <= 1
yield RisingEdge(self.clock)
self.bus.wr <= 0
_float_signals((self.bus.addr, self.bus.din))
self.busy_channel.release()
@cocotb.coroutine
def read_reg(self,addr):
yield self.busy_channel.acquire()
#Only wait if it is too late (<1/2 cycle)
if not int(self.clock):
yield RisingEdge(self.clock)
self.bus.addr <= addr
self.bus.rd <= 1
yield RisingEdge(self.clock)
try:
data = self.bus.dout.value.integer
except:
bv = self.bus.dout.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
data = bv.integer
self.bus.rd <= 0
_float_signals((self.bus.addr, ))
self.busy_channel.release()
raise ReturnValue(data)
class SAXIWrSim(BusDriver):
"""
Connects to host side of simul_axi_wr (just writes to system memory) (both GP and HP)
No locks are used, single instance should be connected to a particular port
"""
_signals=[ # i/o from the DUT side
# read address channel
"wr_address", # output[31:0]
"wid", # output[5:0]
"wr_valid", # output
"wr_ready", # input
"wr_data", # output[63:0]
"wr_stb", # output[7:0]
"bresp_latency"] # input[3:0] // just constant
# "wr_cap", # output[2:0]
# "wr_qos"] # output[3:0]
_fmt=None
_memfile = None
_data_bytes = 8
_address_lsb = 3
def __init__(self, entity, name, clock, mempath, memhigh=0x40000000, data_bytes=8, autoflush=True, blatency=5):
"""
@param entity Device under test
@param name port names prefix (DUT has I/O ports <name>_<signal>
@clock clock that drives this interface
@param mempath operation system path of the memory image (1GB now - 0..0x3fffffff)
@param memhigh memory high address
@param data_bytes data width, in bytes
@param autoflush flush file after each write
@param blatency number of cycles to delay write response (b) channel
"""
BusDriver.__init__(self, entity, name, clock)
self.log.debug ("SAXIWrSim.__init__(): super done")
self._memfile=open(mempath, 'w+')
#Extend to full size
self._memfile.seek(memhigh-1)
try:
self._memfile.read(1)
except:
self._memfile.seek(memhigh-1)
self._memfile.write(chr(0))
self._memfile.flush()
self.autoflush=autoflush
self.bus.wr_ready.setimmediatevalue(1) # always ready
self.bresp_latency = blatency
if data_bytes > 4:
self._data_bytes = 8
self._address_lsb = 3
self._fmt= "<Q"
elif data_bytes > 2:
self._data_bytes = 4
self._address_lsb = 2
self._fmt= "<L"
elif data_bytes > 1:
self._data_bytes = 2
self._address_lsb = 1
self._fmt= "<H"
else:
self._data_bytes = 1
self._address_lsb = 0
self._fmt= "<B"
def flush(self):
self._memfile.flush()
@cocotb.coroutine
def saxi_wr_run(self):
while True:
if not self.bus.wr_ready.value:
break #exit
while True:
yield ReadOnly()
if self.bus.wr_valid.value:
break
yield RisingEdge(self.clock)
# yield RisingEdge(self.clock)
#Here write data
try:
address = self.bus.wr_address.value.integer
except:
self.log.warning ("SAXIWrSim() tried to write to unknown memory address")
adress = None
yield RisingEdge(self.clock)
continue
if address & ((1 << self._address_lsb) - 1):
self.log.warning ("SAXIWrSim() Write memory address is not aligned to %d-byte words"%(self._data_bytes))
address = (address >> self._address_lsb) << self._address_lsb;
self._memfile.seek(address)
try:
data = self.bus.wr_data.value.integer
except:
self.log.warning ("SAXIWrSim() writing undefined data")
bv = self.bus.wr_data.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
data = bv.integer
sdata=struct.pack(self._fmt,data)
bv = self.bus.wr_data.value
bv.binstr= re.sub("[^0]","1",bv.binstr) # only 0 suppresses write to this byte
while len(bv.binstr) < self._data_bytes: # very unlikely
bv.binstr = "1"+bv.binstr
if bv.integer == self._data_bytes:
self._memfile.write(sdata)
else:
for i in range (self._data_bytes):
if bv.binstr[-1-i] != 0:
self._memfile.write(sdata[i])
else:
self._memfile.seek(1,1)
if self.autoflush:
self._memfile.flush()
self.log.debug ("SAXIWrSim() 0x%x -> 0x%x, mask = 0x%x"%(address,data,bv.integer))
yield RisingEdge(self.clock)
class SAXIRdSim(BusDriver):
"""
Connects to host side of simul_axi_rd (just writes to system memory) (both GP and HP)
No locks are used, single instance should be connected to a particular port
"""
_signals=[ # i/o from the DUT side
# read address channel
"rd_address", # output[31:0]
"rid", # output[5:0]
"rd_valid", # input
"rd_ready", # output
"rd_data", # input[63:0]
"rd_resp"] # input[1:0]
_fmt=None
_memfile = None
_data_bytes = 8
_address_lsb = 3
def __init__(self, entity, name, clock, mempath, memhigh=0x40000000, data_bytes=8):
"""
@param entity Device under test
@param name port names prefix (DUT has I/O ports <name>_<signal>
@clock clock that drives this interface
@param mempath operation system path of the memory image (1GB now - 0..0x3fffffff)
@param memhigh memory high address
@param data_bytes data width, in bytes
"""
BusDriver.__init__(self, entity, name, clock)
self.log.debug ("SAXIWrSim.__init__(): super done")
self._memfile=open(mempath, 'r+')
self.bus.rd_valid.setimmediatevalue(0)
if data_bytes > 4:
self._data_bytes = 8
self._address_lsb = 3
self._fmt= "<Q"
elif data_bytes > 2:
self._data_bytes = 4
self._address_lsb = 2
self._fmt= "<L"
elif data_bytes > 1:
self._data_bytes = 2
self._address_lsb = 1
self._fmt= "<H"
else:
self._data_bytes = 1
self._address_lsb = 0
self._fmt= "<B"
@cocotb.coroutine
def saxi_rd_run(self):
while True:
# if not self.bus.rd_valid.value:
# break #exit
while True:
yield FallingEdge(self.clock)
if self.bus.rd_ready.value:
break
self.bus.rd_valid <= 1
# yield RisingEdge(self.clock)
#Here write data
try:
address = self.bus.rd_address.value.integer
except:
self.log.warning ("SAXIRdSim() tried to write to unknown memory address")
adress = None
if address & ((1 << self._address_lsb) - 1):
self.log.warning ("SAXIRdSim() Write memory address is not aligned to %d-byte words"%(self._data_bytes))
address = (address >> self._address_lsb) << self._address_lsb;
self._memfile.seek(address)
rresp=0
try:
rs = self._memfile.read(self._data_bytes)
except:
self.log.warning ("SAXIRdSim() failed reading %d bytes form 0x%08x"%(self._data_bytes, address))
rs = None
if not rs is None:
try:
data = struct.unpack(self._fmt,rs)
except:
self.log.warning ("SAXIRdSim():Can not unpack memory data @ address 0x%08x"%(address))
data=None
if (not address is None) and (not data is None):
self.bus.rd_resp <= 0
self.bus.rd_data <= data
else:
self.bus.rd_resp <= 2 # error
_float_signals((self.bus.rd_data,))
self.bus.rd_valid <= 1
yield RisingEdge(self.clock)
self.bus.rd_valid <= 0
_float_signals((self.bus.rd_data,self.bus.rd_resp))
class MAXIGPMaster(BusDriver): class MAXIGPMaster(BusDriver):
""" """
Implements subset of AXI4 used in x393 project for Xilinx Zynq MAXIGP* Implements subset of AXI4 used in x393 project for Xilinx Zynq MAXIGP*
...@@ -158,13 +435,6 @@ class MAXIGPMaster(BusDriver): ...@@ -158,13 +435,6 @@ class MAXIGPMaster(BusDriver):
for chn in self._channels: for chn in self._channels:
self.log.debug ("MAXIGPMaster.__init__(): chn = %s"%(chn)) self.log.debug ("MAXIGPMaster.__init__(): chn = %s"%(chn))
self.busy_channels[chn]=Lock("%s_%s_busy"%(name,chn)) self.busy_channels[chn]=Lock("%s_%s_busy"%(name,chn))
def _float_signals(self,signals):
if not isinstance (signals,(list,tuple)):
signals = (signals,)
for signal in signals:
v = signal.value
v.binstr = "z" * len(signal)
signal <= v
@cocotb.coroutine @cocotb.coroutine
def _send_write_address(self, address, delay, id, dlen, dsize, burst): def _send_write_address(self, address, delay, id, dlen, dsize, burst):
...@@ -209,7 +479,7 @@ class MAXIGPMaster(BusDriver): ...@@ -209,7 +479,7 @@ class MAXIGPMaster(BusDriver):
yield RisingEdge(self.clock) yield RisingEdge(self.clock)
self.bus.awvalid <= 0 self.bus.awvalid <= 0
# FLoat all assigned bus signals but awvalid # FLoat all assigned bus signals but awvalid
self._float_signals((self.bus.awaddr,self.bus.awid, self.bus.awlen, self.bus.awsize,self.bus.awburst)) _float_signals((self.bus.awaddr,self.bus.awid, self.bus.awlen, self.bus.awsize,self.bus.awburst))
self.busy_channels[AW_CHN].release() self.busy_channels[AW_CHN].release()
self.log.debug ("MAXIGPMaster._send_write_address(): released lock %s"%(AW_CHN)) self.log.debug ("MAXIGPMaster._send_write_address(): released lock %s"%(AW_CHN))
...@@ -256,9 +526,9 @@ class MAXIGPMaster(BusDriver): ...@@ -256,9 +526,9 @@ class MAXIGPMaster(BusDriver):
yield RisingEdge(self.clock) yield RisingEdge(self.clock)
self.bus.arvalid <= 0 self.bus.arvalid <= 0
# FLoat all assigned bus signals but awvalid # FLoat all assigned bus signals but awvalid
self._float_signals((self.bus.araddr,self.bus.arid, self.bus.arlen, self.bus.arsize,self.bus.arburst)) _float_signals((self.bus.araddr,self.bus.arid, self.bus.arlen, self.bus.arsize,self.bus.arburst))
self.busy_channels[AR_CHN].release() self.busy_channels[AR_CHN].release()
self.log.debug ("MAXIGPMaster._send_read_address(): released lock %s"%(AW_CHN)) self.log.debug ("MAXIGPMaster._send_read_address(): released lock %s"%(AR_CHN))
@cocotb.coroutine @cocotb.coroutine
def _send_write_data(self, data, wrstb, delay, id, dsize): def _send_write_data(self, data, wrstb, delay, id, dsize):
...@@ -294,7 +564,7 @@ class MAXIGPMaster(BusDriver): ...@@ -294,7 +564,7 @@ class MAXIGPMaster(BusDriver):
yield RisingEdge(self.clock) yield RisingEdge(self.clock)
self.bus.wvalid <= 0 self.bus.wvalid <= 0
# FLoat all assigned bus signals but wvalid # FLoat all assigned bus signals but wvalid
self._float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast)) _float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast))
self.busy_channels[W_CHN].release() self.busy_channels[W_CHN].release()
self.log.debug ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN)) self.log.debug ("MAXIGPMaster._send_write_data(): released lock %s"%(W_CHN))
raise ReturnValue(dsize) raise ReturnValue(dsize)
...@@ -323,7 +593,12 @@ class MAXIGPMaster(BusDriver): ...@@ -323,7 +593,12 @@ class MAXIGPMaster(BusDriver):
while True: while True:
yield ReadOnly() yield ReadOnly()
if self.bus.rvalid.value: if self.bus.rvalid.value:
data.append(self.bus.rdata.value.integer) try:
data.append(self.bus.rdata.value.integer)
except:
bv = self.bus.rdata.value
bv.binstr = re.sub("[^1]","0",bv.binstr)
data.append(bv.integer)
rid = int(self.bus.rid.value) rid = int(self.bus.rid.value)
if rid != id: if rid != id:
self.log.error("Read data 0x%x ID mismatch - expected: 0x%x, got 0x%x"%(address+i,id, rid)) self.log.error("Read data 0x%x ID mismatch - expected: 0x%x, got 0x%x"%(address+i,id, rid))
...@@ -332,7 +607,7 @@ class MAXIGPMaster(BusDriver): ...@@ -332,7 +607,7 @@ class MAXIGPMaster(BusDriver):
yield RisingEdge(self.clock) yield RisingEdge(self.clock)
self.bus.rready <= 0 self.bus.rready <= 0
# FLoat all assigned bus signals but wvalid # FLoat all assigned bus signals but wvalid
# self._float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast)) # _float_signals((self.bus.wdata,self.bus.wstb,self.bus.wlast))
self.busy_channels[R_CHN].release() self.busy_channels[R_CHN].release()
self.log.debug ("MAXIGPMaster._get_read_data(): released lock %s"%(R_CHN)) self.log.debug ("MAXIGPMaster._get_read_data(): released lock %s"%(R_CHN))
raise ReturnValue(data) raise ReturnValue(data)
...@@ -355,7 +630,7 @@ class MAXIGPMaster(BusDriver): ...@@ -355,7 +630,7 @@ class MAXIGPMaster(BusDriver):
@param address_latency latency sending address in clock cycles @param address_latency latency sending address in clock cycles
@param data_latency latency sending data in clock cycles @param data_latency latency sending data in clock cycles
""" """
#Only wait if it is too late (<1/2 cycle) #Only wait if it is too late (<1/2 cycle)
if not int(self.clock): if not int(self.clock):
yield RisingEdge(self.clock) yield RisingEdge(self.clock)
......
includes/x393_simulation_parameters.vh
View file @ 6a2bdfd7
...@@ -36,6 +36,8 @@ ...@@ -36,6 +36,8 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
, // to continue previous parameter list , // to continue previous parameter list
parameter NUM_INTERRUPTS = 9,
parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2, parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4, parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1 parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
...@@ -113,6 +115,8 @@ ...@@ -113,6 +115,8 @@
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page) parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64, parameter WOI_WIDTH= 64,
parameter WOI_HEIGHT= 32,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2 parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 1000 parameter SENSOR_PRIORITY = 1000
py393/cocoargs 0 → 100644
View file @ 6a2bdfd7
-d TARGET_MODE=1
-f system_defines.vh
-f includes/x393_parameters.vh includes/x393_cur_params_target.vh includes/x393_localparams.vh includes/x393_simulation_parameters.vh
-l includes/x393_cur_params_target_gen.vh
-l includes/x393_cur_params_target_gen.vh
-p PICKLE="includes/x393_mcntrl.pickle"
-i
py393/test_mcntrl.py
View file @ 6a2bdfd7
...@@ -31,10 +31,13 @@ __version__ = "3.0+" ...@@ -31,10 +31,13 @@ __version__ = "3.0+"
__maintainer__ = "Andrey Filippov" __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com" __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
''' '''
./test_mcntrl.py -v -f../system_defines.vh -f ../includes/x393_parameters.vh ../includes/x393_localparams.vh -pNEWPAR=\'h3ff -c write_mem 0x377 25 -c read_mem 0x3ff -i -d aaa=bbb -d ccc=ddd ./test_mcntrl.py -v -f../system_defines.vh -f ../includes/x393_parameters.vh ../includes/x393_localparams.vh -pNEWPAR=\'h3ff -c write_mem 0x377 25 -c read_mem 0x3ff -i -d aaa=bbb -d ccc=ddd
''' '''
import readline
import sys import sys
import os import os
import inspect import inspect
...@@ -94,15 +97,7 @@ class CLIError(Exception): ...@@ -94,15 +97,7 @@ class CLIError(Exception):
return self.msg return self.msg
def __unicode__(self): def __unicode__(self):
return self.msg return self.msg
'''
for name in x393_mem.X393Mem.__dict__:
if hasattr((x393_mem.X393Mem.__dict__[name]), '__call__') and not (name[0]=='_'):
func_args=x393_mem.X393Mem.__dict__[name].func_code.co_varnames[1:x393_mem.X393Mem.__dict__[name].func_code.co_argcount]
# print (name+": "+str(x393_mem.X393Mem.__dict__[name]))
# print ("args="+str(func_args))
print (name+": "+str(func_args))
'''
def extractTasks(obj,inst): def extractTasks(obj,inst):
for name in obj.__dict__: for name in obj.__dict__:
if hasattr((obj.__dict__[name]), '__call__') and not (name[0]=='_'): if hasattr((obj.__dict__[name]), '__call__') and not (name[0]=='_'):
...@@ -221,7 +216,7 @@ USAGE ...@@ -221,7 +216,7 @@ USAGE
parser.add_argument("-p", "--parameter", dest="parameters", action="append", default=[], help="Define parameter(s) as name=value" , nargs='*' ) parser.add_argument("-p", "--parameter", dest="parameters", action="append", default=[], help="Define parameter(s) as name=value" , nargs='*' )
parser.add_argument("-c", "--command", dest="commands", action="append", default=[], help="execute command" , nargs='*') parser.add_argument("-c", "--command", dest="commands", action="append", default=[], help="execute command" , nargs='*')
parser.add_argument("-i", "--interactive", dest="interactive", action="store_true", help="enter interactive mode [default: %(default)s]") parser.add_argument("-i", "--interactive", dest="interactive", action="store_true", help="enter interactive mode [default: %(default)s]")
parser.add_argument("-s", "--simulated", dest="simulated", action="store_true", help="Simulated mode (no real hardware I/O) [default: %(default)s]") parser.add_argument("-s", "--simulated", dest="simulated", action="store", help="Simulated mode (no real hardware I/O) [default: %(default)s]")
parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]") parser.add_argument("-x", "--exceptions", dest="exceptions", action="count", help="Exit on more exceptions [default: %(default)s]")
parser.add_argument("-l", "--localparams", dest="localparams", action="store", default="", parser.add_argument("-l", "--localparams", dest="localparams", action="store", default="",
help="path were modified parameters are saved [default: %(default)s]", metavar="path") help="path were modified parameters are saved [default: %(default)s]", metavar="path")
...@@ -236,9 +231,11 @@ USAGE ...@@ -236,9 +231,11 @@ USAGE
QUIET = (1,0)[args.exceptions] QUIET = (1,0)[args.exceptions]
# print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET)) # print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
print("args.simulated = ",args.simulated)
print("args = ",args)
if not args.simulated: if not args.simulated:
if not os.path.exists("/dev/xdevcfg"): if not os.path.exists("/dev/xdevcfg"):
args.simulated=True args.simulated="simulated"
print("Program is forced to run in SIMULATED mode as '/dev/xdevcfg' does not exist (not a camera)") print("Program is forced to run in SIMULATED mode as '/dev/xdevcfg' does not exist (not a camera)")
#print("--- defines=%s"% str(args.defines)) #print("--- defines=%s"% str(args.defines))
#print("--- paths=%s"% str(args.paths)) #print("--- paths=%s"% str(args.paths))
...@@ -401,7 +398,7 @@ USAGE ...@@ -401,7 +398,7 @@ USAGE
rslt= execTask(cmdLine) rslt= execTask(cmdLine)
print (' Result: '+str(rslt)) print (' Result: '+str(rslt))
''' '''
#TODO: use readline #TODO: use readline
''' '''
if args.socket_port: if args.socket_port:
PORT = int(args.socket_port) # 8888 PORT = int(args.socket_port) # 8888
...@@ -424,8 +421,10 @@ USAGE ...@@ -424,8 +421,10 @@ USAGE
line ="" line =""
while True: while True:
soc_conn = None soc_conn = None
prompt = 'x393%s +%3.3fs--> '%(('','(simulated)')[args.simulated],(time.time()-tim)) prompt = 'x393 (%s) +%3.3fs--> '%(args.simulated,(time.time()-tim)) if args.simulated else 'x393 +%3.3fs--> '%(time.time()-tim)
#prompt = 'x393%s +%3.3fs--> '%(args.simulated,(time.time()-tim))
if socket_conn: if socket_conn:
print ("***socket_conn***")
print(prompt , end="") print(prompt , end="")
sys.stdout.flush() sys.stdout.flush()
if (args.socket_port): if (args.socket_port):
......
py393/vrlg.py
View file @ 6a2bdfd7
...@@ -180,7 +180,7 @@ NUM_CYCLES_20__TYPE = str ...@@ -180,7 +180,7 @@ NUM_CYCLES_20__TYPE = str
SENS_JTAG_PGMEN = int SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str NUM_CYCLES_03__TYPE = str
CMPRS_CBIT_RUN_BITS__TYPE = str CMPRS_CBIT_RUN_BITS__TYPE = str
LD_DLY_LANE1_IDELAY__TYPE = str SENSOR12BITS_TDDO1 = int
TILED_EXTRA_PAGES__RAW = str TILED_EXTRA_PAGES__RAW = str
CMPRS_NUM_AFI_CHN = int CMPRS_NUM_AFI_CHN = int
CAMSYNC_TRIG_SRC__RAW = str CAMSYNC_TRIG_SRC__RAW = str
...@@ -222,18 +222,22 @@ MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str ...@@ -222,18 +222,22 @@ MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
CLKFBOUT_MULT = int CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str RTC_STATUS_REG_ADDR__RAW = str
SENS_LENS_C_MASK__RAW = str SENS_LENS_C_MASK__RAW = str
SIMULATE_CMPRS_CMODE0__RAW = str
NUM_CYCLES_11__TYPE = str NUM_CYCLES_11__TYPE = str
DEBUG_ADDR__TYPE = str DEBUG_ADDR__TYPE = str
CMPRS_CBIT_QBANK_BITS__TYPE = str CMPRS_CBIT_QBANK_BITS__TYPE = str
SENS_GAMMA_MODE_TRIG = int SENS_GAMMA_MODE_TRIG = int
RTC_SET_USEC = int RTC_SET_USEC = int
RTC_BITC_PREDIV__TYPE = str RTC_BITC_PREDIV__TYPE = str
SIMULATE_CMPRS_CMODE0__TYPE = str
LD_DLY_CMDA = int LD_DLY_CMDA = int
DLY_SET__RAW = str DLY_SET__RAW = str
SENSI2C_CMD_TABLE = int SENSI2C_CMD_TABLE = int
MCNTRL_PS_ADDR__RAW = str MCNTRL_PS_ADDR__RAW = str
WOI_WIDTH__TYPE = str
NUM_FRAME_BITS__RAW = str NUM_FRAME_BITS__RAW = str
SENSI2C_CMD_ACIVE__RAW = str SENSI2C_CMD_ACIVE__RAW = str
HISTOGRAM_TOP__RAW = str
LOGGER_CONF_GPS__TYPE = str LOGGER_CONF_GPS__TYPE = str
HIST_SAXI_EN__RAW = str HIST_SAXI_EN__RAW = str
SENSOR_16BIT_BIT__RAW = str SENSOR_16BIT_BIT__RAW = str
...@@ -257,6 +261,7 @@ NUM_CYCLES_30 = int ...@@ -257,6 +261,7 @@ NUM_CYCLES_30 = int
HISPI_DELAY_CLK0__TYPE = str HISPI_DELAY_CLK0__TYPE = str
CMPRS_CBIT_QBANK__RAW = str CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str SENS_SYNC_MASK__TYPE = str
MEMCLK_PERIOD__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str MCONTR_BUF0_RD_ADDR__RAW = str
HISPI_MMCM1 = str HISPI_MMCM1 = str
SENS_PHASE_WIDTH = int SENS_PHASE_WIDTH = int
...@@ -279,6 +284,7 @@ DLY_LANE1_DQS_WLV_IDELAY__RAW = str ...@@ -279,6 +284,7 @@ DLY_LANE1_DQS_WLV_IDELAY__RAW = str
SENS_LENS_RADDR = int SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str PXD_IOSTANDARD = str
SENSOR12BITS_TMD__RAW = str
MAX_TILE_HEIGHT = int MAX_TILE_HEIGHT = int
BUF_CLK1X_PCLK = str BUF_CLK1X_PCLK = str
LOGGER_CONF_DBG_BITS = int LOGGER_CONF_DBG_BITS = int
...@@ -302,6 +308,7 @@ MAX_TILE_WIDTH__TYPE = str ...@@ -302,6 +308,7 @@ MAX_TILE_WIDTH__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int SENS_LENS_POST_SCALE_MASK = int
MEMCLK_PERIOD = float
BUF_IPCLK2X_SENS1__RAW = str BUF_IPCLK2X_SENS1__RAW = str
SENSOR_MODE_WIDTH__RAW = str SENSOR_MODE_WIDTH__RAW = str
SENS_LENS_FAT0_OUT_MASK = int SENS_LENS_FAT0_OUT_MASK = int
...@@ -323,12 +330,14 @@ RTC_STATUS_REG_ADDR = int ...@@ -323,12 +330,14 @@ RTC_STATUS_REG_ADDR = int
SENS_LENS_BY_MASK__TYPE = str SENS_LENS_BY_MASK__TYPE = str
CMPRS_CBIT_CMODE__RAW = str CMPRS_CBIT_CMODE__RAW = str
TILED_EXTRA_PAGES__TYPE = str TILED_EXTRA_PAGES__TYPE = str
AXI_RDADDR_LATENCY = int
AFI_MUX_BUF_LATENCY = int AFI_MUX_BUF_LATENCY = int
WINDOW_WIDTH = int WINDOW_WIDTH = int
CLK_CNTRL__RAW = str CLK_CNTRL__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS = int MCONTR_LINTILE_EXTRAPG_BITS = int
MCONTR_LINTILE_RST_FRAME__TYPE = str MCONTR_LINTILE_RST_FRAME__TYPE = str
LAST_BUF_FRAME__RAW = str HISTOGRAM_TOP = int
FCLK1_PERIOD = float
CMPRS_AFIMUX_RADDR1__RAW = str CMPRS_AFIMUX_RADDR1__RAW = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
CMPRS_CBIT_DCSUB_BITS__RAW = str CMPRS_CBIT_DCSUB_BITS__RAW = str
...@@ -345,11 +354,11 @@ LOGGER_CONF_MSG__RAW = str ...@@ -345,11 +354,11 @@ LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
LAST_FRAME_BITS__RAW = str LAST_FRAME_BITS__RAW = str
SENS_DIVCLK_DIVIDE = int SENS_DIVCLK_DIVIDE = int
NEWPAR = int
SENSI2C_CMD_SOFT_SDA__TYPE = str SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str SENS_LENS_COEFF__RAW = str
CMPRS_CONTROL_REG = int GPIO_MASK = int
GPIO_STATUS_REG_ADDR = int GPIO_STATUS_REG_ADDR = int
AXI_TASK_HOLD__RAW = str
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
CMPRS_AFIMUX_RADDR0__TYPE = str CMPRS_AFIMUX_RADDR0__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str MCNTRL_TILED_WINDOW_WH__RAW = str
...@@ -409,6 +418,7 @@ NUM_CYCLES_21 = int ...@@ -409,6 +418,7 @@ NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str CAMSYNC_TRIG_DELAY2__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str MULTICLK_BUF_DLYREF__RAW = str
FCLK0_PERIOD = float
CMDFRAMESEQ_REL__TYPE = str CMDFRAMESEQ_REL__TYPE = str
MAX_TILE_WIDTH__RAW = str MAX_TILE_WIDTH__RAW = str
PICKLE = str PICKLE = str
...@@ -434,6 +444,7 @@ MCONTR_LINTILE_SKIP_LATE__TYPE = str ...@@ -434,6 +444,7 @@ MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str DEBUG_ADDR__RAW = str
CONTROL_ADDR__RAW = str CONTROL_ADDR__RAW = str
TILED_STARTY__RAW = str TILED_STARTY__RAW = str
RTC_BITC_PREDIV = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str SENS_CTRL_QUADRANTS_EN__RAW = str
HISPI_DELAY_CLK1__TYPE = str HISPI_DELAY_CLK1__TYPE = str
...@@ -451,7 +462,7 @@ MULTICLK_DIV_SYNC__RAW = str ...@@ -451,7 +462,7 @@ MULTICLK_DIV_SYNC__RAW = str
CMPRS_CORING_MODE = int CMPRS_CORING_MODE = int
LOGGER_STATUS__TYPE = str LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str DFLT_REFRESH_PERIOD__TYPE = str
SENS_JTAG_TMS__TYPE = str FFCLK1_IOSTANDARD = str
MCNTRL_TILED_MASK = int MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str SENSIO_JTAG__RAW = str
...@@ -465,11 +476,12 @@ FRAME_HEIGHT_BITS__RAW = str ...@@ -465,11 +476,12 @@ FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int MCONTR_LINTILE_KEEP_OPEN = int
SENSI2C_TBL_NBRD_BITS__RAW = str SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long DLY_CMDA_ODELAY = long
SENS_LENS_C = int GPIO_PORTEN__RAW = str
MCONTR_ARBIT_ADDR_MASK = int MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int MCNTRL_SCANLINE_WINDOW_WH = int
WBUF_DLY_WLV__RAW = str WBUF_DLY_WLV__RAW = str
SIMULATE_CMPRS_CMODE3__RAW = str
TABLE_HUFFMAN_INDEX = int TABLE_HUFFMAN_INDEX = int
MCNTRL_TILED_FRAME_LAST = int MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str MCNTRL_TEST01_CHN2_MODE__RAW = str
...@@ -482,6 +494,7 @@ CAMSYNC_EN_BIT__TYPE = str ...@@ -482,6 +494,7 @@ CAMSYNC_EN_BIT__TYPE = str
LD_DLY_LANE0_IDELAY = int LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str NUM_CYCLES_24__TYPE = str
FCLK0_PERIOD__RAW = str
MCLK_PHASE__TYPE = str MCLK_PHASE__TYPE = str
SENSI2C_DRIVE__TYPE = str SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str SENS_CTRL_RST_MMCM__RAW = str
...@@ -494,11 +507,12 @@ MCNTRL_TILED_FRAME_FULL_WIDTH = int ...@@ -494,11 +507,12 @@ MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str SENS_LENS_POST_SCALE__TYPE = str
RTC_MHZ__RAW = str RTC_MHZ__RAW = str
FRAME_HEIGHT_BITS = int SENSOR_PRIORITY__RAW = str
HIST_SAXI_ADDR_MASK__TYPE = str HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int SENS_CTRL_LD_DLY = int
SENS_LENS_FAT0_IN_MASK__RAW = str SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str SENS_LENS_AY_MASK__RAW = str
SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str DFLT_DQS_PATTERN__RAW = str
...@@ -509,6 +523,7 @@ REF_JITTER1__TYPE = str ...@@ -509,6 +523,7 @@ REF_JITTER1__TYPE = str
FFCLK1_DIFF_TERM = str FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str FFCLK0_IOSTANDARD__TYPE = str
WOI_WIDTH__RAW = str
STATUS_MSB_RSHFT = int STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str CMPRS_CONTROL_REG__RAW = str
CLKIN_PERIOD__TYPE = str CLKIN_PERIOD__TYPE = str
...@@ -545,8 +560,9 @@ NUM_CYCLES_11 = int ...@@ -545,8 +560,9 @@ NUM_CYCLES_11 = int
SENS_GAMMA_ADDR_MASK = int SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str MEMCLK_IBUF_LOW_PWR__TYPE = str
HISTOGRAM_HEIGHT__TYPE = str
CMPRS_HIFREQ_REG_BASE__TYPE = str CMPRS_HIFREQ_REG_BASE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str FCLK0_PERIOD__TYPE = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
DQTRI_LAST__TYPE = str DQTRI_LAST__TYPE = str
MULTICLK_DIVCLK__TYPE = str MULTICLK_DIVCLK__TYPE = str
...@@ -567,7 +583,6 @@ NUM_CYCLES_16 = int ...@@ -567,7 +583,6 @@ NUM_CYCLES_16 = int
NUM_CYCLES_15 = int NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int CMPRS_CBIT_BAYER = int
GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str HISPI_DIFF_TERM__TYPE = str
...@@ -579,6 +594,7 @@ SENSI2C_TBL_SA__TYPE = str ...@@ -579,6 +594,7 @@ SENSI2C_TBL_SA__TYPE = str
BUF_IPCLK_SENS3__TYPE = str BUF_IPCLK_SENS3__TYPE = str
MCNTRL_TILED_MODE = int MCNTRL_TILED_MODE = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
HISTOGRAM_HEIGHT = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
LOGGER_CONF_SYN = int LOGGER_CONF_SYN = int
MCNTRL_TILED_CHN4_ADDR__RAW = str MCNTRL_TILED_CHN4_ADDR__RAW = str
...@@ -590,6 +606,10 @@ PICKLE__RAW = str ...@@ -590,6 +606,10 @@ PICKLE__RAW = str
DQSTRI_LAST__RAW = str DQSTRI_LAST__RAW = str
WRITELEV_OFFSET__TYPE = str WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int CMPRS_BASE_INC = int
SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE1 = int
MULT_SAXI_CNTRL_ADDR = int MULT_SAXI_CNTRL_ADDR = int
MULTICLK_BUF_SYNC__TYPE = str MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str HIST_SAXI_ADDR_REL__RAW = str
...@@ -615,13 +635,15 @@ CAMSYNC_EN_BIT = int ...@@ -615,13 +635,15 @@ CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str HISTOGRAM_RAM_MODE = str
SENS_REFCLK_FREQUENCY__TYPE = str SENS_REFCLK_FREQUENCY__TYPE = str
HISTOGRAM_TOP__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int DEBUG_ADDR = int
SIMULATE_CMPRS_CMODE2__TYPE = str
MULT_SAXI_ADV_WR__RAW = str MULT_SAXI_ADV_WR__RAW = str
LOGGER_PAGE_GPS = int LOGGER_PAGE_GPS = int
HIST_SAXI_MODE_ADDR_MASK = int HIST_SAXI_MODE_ADDR_MASK = int
WRITELEV_OFFSET = int CMPRS_AFIMUX_SA_LEN__RAW = str
LOGGER_CONF_MSG = int LOGGER_CONF_MSG = int
CMPRS_CSAT_CR__RAW = str CMPRS_CSAT_CR__RAW = str
CMPRS_CBIT_RUN = int CMPRS_CBIT_RUN = int
...@@ -636,9 +658,10 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str ...@@ -636,9 +658,10 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str
SENSI2C_TBL_SA__RAW = str SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str CMPRS_CBIT_CMODE_JP4__RAW = str
MULTICLK_BUF_AXIHP__RAW = str MULTICLK_BUF_AXIHP__RAW = str
DFLT_DQM_PATTERN__RAW = str CLK_STATUS__TYPE = str
GPIO_SET_STATUS__RAW = str GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int SENS_JTAG_TCK = int
CMPRS_COLOR20__TYPE = str
DEBUG_STATUS_REG_ADDR__TYPE = str DEBUG_STATUS_REG_ADDR__TYPE = str
REFRESH_OFFSET__TYPE = str REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str SENS_CTRL_ARST__RAW = str
...@@ -733,7 +756,7 @@ LOGGER_PERIOD__RAW = str ...@@ -733,7 +756,7 @@ LOGGER_PERIOD__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
SENS_LENS_AX_MASK = int SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str AXI_RD_ADDR_BITS__RAW = str
RTC_BITC_PREDIV = int AXI_WRADDR_LATENCY = int
SENS_SS_MOD_PERIOD__TYPE = str SENS_SS_MOD_PERIOD__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str SENS_JTAG_PGMEN__TYPE = str
...@@ -777,24 +800,26 @@ MCNTRL_SCANLINE_MASK = int ...@@ -777,24 +800,26 @@ MCNTRL_SCANLINE_MASK = int
MULTICLK_DIVCLK = int MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str MULT_SAXI_BSLOG3__TYPE = str
SENSOR12BITS_NGPL__RAW = str
CLKFBOUT_MULT__RAW = str CLKFBOUT_MULT__RAW = str
CMPRS_STATUS_REG_INC__RAW = str CMPRS_STATUS_REG_INC__RAW = str
SIMULATE_CMPRS_CMODE1__TYPE = str
HISTOGRAM_RADDR0__RAW = str HISTOGRAM_RADDR0__RAW = str
HISPI_KEEP_IRST = int HISPI_KEEP_IRST = int
STATUS_ADDR_MASK = int STATUS_ADDR_MASK = int
PXD_CAPACITANCE = str PXD_CAPACITANCE = str
SENS_LENS_AY = int SENS_LENS_AY = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str CMPRS_CBIT_CMODE_MONO6__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
HISTOGRAM_RAM_MODE__RAW = str HISTOGRAM_RAM_MODE__RAW = str
SENS_LENS_AX_MASK__RAW = str SENS_LENS_AX_MASK__RAW = str
SENSI2C_TBL_SA_BITS = int SENSI2C_TBL_SA_BITS = int
CMPRS_FRMT_MBCM1__TYPE = str CMPRS_FRMT_MBCM1__TYPE = str
SENSOR_HIST_EN_BITS__RAW = str CMPRS_TIMEOUT__TYPE = str
MULT_SAXI_ADV_WR = int MULT_SAXI_ADV_WR = int
NUM_CYCLES_10__TYPE = str NUM_CYCLES_10__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str MCONTR_LINTILE_EXTRAPG__RAW = str
SENS_LENS_FAT0_IN__RAW = str SENS_LENS_FAT0_IN__RAW = str
NEWPAR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
LOGGER_CONFIG__RAW = str LOGGER_CONFIG__RAW = str
LD_DLY_LANE0_ODELAY__RAW = str LD_DLY_LANE0_ODELAY__RAW = str
...@@ -810,6 +835,7 @@ MCONTR_BUF4_WR_ADDR = int ...@@ -810,6 +835,7 @@ MCONTR_BUF4_WR_ADDR = int
SENS_DIVCLK_DIVIDE__RAW = str SENS_DIVCLK_DIVIDE__RAW = str
SENSOR_BASE_INC__RAW = str SENSOR_BASE_INC__RAW = str
CMPRS_CBIT_DCSUB_BITS = int CMPRS_CBIT_DCSUB_BITS = int
HISTOGRAM_LEFT__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int MCONTR_TOP_16BIT_ADDR_MASK = int
PXD_IBUF_LOW_PWR__TYPE = str PXD_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_REPEAT__TYPE = str MCONTR_LINTILE_REPEAT__TYPE = str
...@@ -865,6 +891,7 @@ MCONTR_LINTILE_NRESET__TYPE = str ...@@ -865,6 +891,7 @@ MCONTR_LINTILE_NRESET__TYPE = str
PXD_CLK_DIV__RAW = str PXD_CLK_DIV__RAW = str
SENS_NUM_SUBCHN__RAW = str SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str CMPRS_CBIT_RUN_ENABLE__RAW = str
AXI_RDADDR_LATENCY__TYPE = str
BUF_IPCLK_SENS3__RAW = str BUF_IPCLK_SENS3__RAW = str
CLK_STATUS__RAW = str CLK_STATUS__RAW = str
MULTICLK_BUF_AXIHP = str MULTICLK_BUF_AXIHP = str
...@@ -874,10 +901,10 @@ SENS_CTRL_RST_MMCM = int ...@@ -874,10 +901,10 @@ SENS_CTRL_RST_MMCM = int
HISPI_DQS_BIAS__TYPE = str HISPI_DQS_BIAS__TYPE = str
MCONTR_CMD_WR_ADDR = int MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str SENSI2C_TBL_DLY_BITS__RAW = str
CMPRS_CSAT_CB__TYPE = str SENSOR12BITS_TDDO1__RAW = str
HISPI_MMCM0__TYPE = str HISPI_MMCM0__TYPE = str
TILE_WIDTH = int TILE_WIDTH = int
GPIO_MASK = int CMPRS_CONTROL_REG = int
DLY_LANE0_ODELAY = long DLY_LANE0_ODELAY = long
NUM_XFER_BITS = int NUM_XFER_BITS = int
HISPI_NUMLANES__RAW = str HISPI_NUMLANES__RAW = str
...@@ -886,6 +913,7 @@ DLY_DQS_ODELAY__TYPE = str ...@@ -886,6 +913,7 @@ DLY_DQS_ODELAY__TYPE = str
DLY_LANE0_ODELAY__RAW = str DLY_LANE0_ODELAY__RAW = str
MCONTR_BUF3_WR_ADDR__TYPE = str MCONTR_BUF3_WR_ADDR__TYPE = str
SCANLINE_STARTX__TYPE = str SCANLINE_STARTX__TYPE = str
CAMSYNC_MASTER_BIT__TYPE = str
WRITE_BLOCK_OFFSET = int WRITE_BLOCK_OFFSET = int
FRAME_FULL_WIDTH__RAW = str FRAME_FULL_WIDTH__RAW = str
LOGGER_CONF_EN__TYPE = str LOGGER_CONF_EN__TYPE = str
...@@ -900,7 +928,9 @@ CMPRS_CBIT_CMODE_BITS__TYPE = str ...@@ -900,7 +928,9 @@ CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str LOGGER_BIT_DURATION__TYPE = str
HISPI_MMCM1__RAW = str HISPI_MMCM1__RAW = str
TEST_INITIAL_BURST__TYPE = str TEST_INITIAL_BURST__TYPE = str
SENSOR12BITS_NVLO = int
NUM_CYCLES_19__RAW = str NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW = str
MCNTRL_PS_MASK__RAW = str MCNTRL_PS_MASK__RAW = str
CMPRS_CBIT_CMODE_JPEG20__TYPE = str CMPRS_CBIT_CMODE_JPEG20__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str HISPI_IBUF_LOW_PWR__TYPE = str
...@@ -913,6 +943,7 @@ CMPRS_TIMEOUT_BITS__TYPE = str ...@@ -913,6 +943,7 @@ CMPRS_TIMEOUT_BITS__TYPE = str
SENS_GAMMA_MODE_WIDTH__RAW = str SENS_GAMMA_MODE_WIDTH__RAW = str
PHASE_CLK2X_PCLK__TYPE = str PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str FFCLK1_DIFF_TERM__TYPE = str
WRITELEV_OFFSET = int
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
MULT_SAXI_ADV_RD__RAW = str MULT_SAXI_ADV_RD__RAW = str
SENS_SYNC_RADDR = int SENS_SYNC_RADDR = int
...@@ -943,6 +974,7 @@ CMPRS_MONO16__TYPE = str ...@@ -943,6 +974,7 @@ CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str SENSI2C_TBL_DLY__TYPE = str
MEMBRIDGE_SIZE64 = int MEMBRIDGE_SIZE64 = int
SENSOR_IMAGE_TYPE1__RAW = str
MCONTR_PHY_0BIT_CKE_EN__TYPE = str MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int CMPRS_FRMT_MBCM1_BITS = int
HISTOGRAM_RAM_MODE__TYPE = str HISTOGRAM_RAM_MODE__TYPE = str
...@@ -950,8 +982,9 @@ AFI_LO_ADDR64 = int ...@@ -950,8 +982,9 @@ AFI_LO_ADDR64 = int
NUM_CYCLES_07__TYPE = str NUM_CYCLES_07__TYPE = str
SENS_LENS_FAT0_IN = int SENS_LENS_FAT0_IN = int
CMPRS_FRMT_LMARG_BITS__TYPE = str CMPRS_FRMT_LMARG_BITS__TYPE = str
SENSOR12BITS_NGPL__TYPE = str
HISTOGRAM_RADDR1__TYPE = str HISTOGRAM_RADDR1__TYPE = str
CAMSYNC_MASTER_BIT__TYPE = str SIMUL_AXI_READ_WIDTH = int
HISTOGRAM_ADDR_MASK = int HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
...@@ -1009,6 +1042,7 @@ MCONTR_TOP_STATUS_REG_ADDR = int ...@@ -1009,6 +1042,7 @@ MCONTR_TOP_STATUS_REG_ADDR = int
SENSI2C_STATUS_REG_INC__RAW = str SENSI2C_STATUS_REG_INC__RAW = str
SDCLK_PHASE = float SDCLK_PHASE = float
SLEW_CMDA = str SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str TEST01_NEXT_PAGE__TYPE = str
...@@ -1025,12 +1059,13 @@ CAMSYNC_DELAY = int ...@@ -1025,12 +1059,13 @@ CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str BUF_IPCLK2X_SENS2__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str MCNTRL_TEST01_CHN1_MODE__RAW = str
MULTICLK_PHASE_AXIHP__RAW = str MULTICLK_PHASE_AXIHP__RAW = str
QUADRANTS_PXD_HACT_VACT = int
FFCLK0_IOSTANDARD__RAW = str FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str MULTICLK_DIV_XCLK__RAW = str
DFLT_DQS_TRI_ON_PATTERN__TYPE = str DFLT_DQS_TRI_ON_PATTERN__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__TYPE = str MCONTR_PHY_0BIT_DLY_RST__TYPE = str
TILED_KEEP_OPEN__RAW = str TILED_KEEP_OPEN__RAW = str
MULTICLK_BUF_XCLK__RAW = str AXI_WRADDR_LATENCY__TYPE = str
MULTICLK_BUF_XCLK__TYPE = str MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str MCONTR_TOP_0BIT_ADDR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str CLKFBOUT_PHASE_SENSOR__RAW = str
...@@ -1041,9 +1076,12 @@ MCNTRL_SCANLINE_FRAME_SIZE = int ...@@ -1041,9 +1076,12 @@ MCNTRL_SCANLINE_FRAME_SIZE = int
STATUS_DEPTH = int STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str CAMSYNC_EXTERNAL_BIT__RAW = str
HISTOGRAM_WIDTH = int
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str HISPI_IBUF_LOW_PWR__RAW = str
MCNTRL_PS_STATUS_REG_ADDR = int
SENSI2C_TBL_NBRD__TYPE = str SENSI2C_TBL_NBRD__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str MCONTR_PHY_0BIT_ADDR__TYPE = str
...@@ -1070,7 +1108,7 @@ CMPRS_CBIT_FOCUS_BITS = int ...@@ -1070,7 +1108,7 @@ CMPRS_CBIT_FOCUS_BITS = int
LOGGER_CONF_SYN__RAW = str LOGGER_CONF_SYN__RAW = str
CMPRS_COLOR20 = int CMPRS_COLOR20 = int
SENSI2C_CMD_TABLE__RAW = str SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str LAST_BUF_FRAME__RAW = str
ADDRESS_NUMBER__TYPE = str ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str WSEL__TYPE = str
CMPRS_AFIMUX_CYCBITS__RAW = str CMPRS_AFIMUX_CYCBITS__RAW = str
...@@ -1107,7 +1145,6 @@ CMPRS_STATUS_CNTRL__TYPE = str ...@@ -1107,7 +1145,6 @@ CMPRS_STATUS_CNTRL__TYPE = str
MCONTR_RD_MASK = int MCONTR_RD_MASK = int
CMPRS_COLOR_SATURATION = int CMPRS_COLOR_SATURATION = int
NUM_CYCLES_21__RAW = str NUM_CYCLES_21__RAW = str
NEWPAR__RAW = str
MULTICLK_PHASE_DLYREF__RAW = str MULTICLK_PHASE_DLYREF__RAW = str
SENSIO_DELAYS__RAW = str SENSIO_DELAYS__RAW = str
CMDFRAMESEQ_RUN_BIT = int CMDFRAMESEQ_RUN_BIT = int
...@@ -1128,6 +1165,7 @@ NUM_CYCLES_29__RAW = str ...@@ -1128,6 +1165,7 @@ NUM_CYCLES_29__RAW = str
GPIO_SET_STATUS__TYPE = str GPIO_SET_STATUS__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str SENSIO_STATUS_REG_REL__RAW = str
FFCLK0_CAPACITANCE__RAW = str FFCLK0_CAPACITANCE__RAW = str
SENSOR12BITS_TDDO1__TYPE = str
CMDFRAMESEQ_ABS = int CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str MULT_SAXI_ADDR__RAW = str
...@@ -1137,6 +1175,7 @@ MCNTRL_SCANLINE_MASK__RAW = str ...@@ -1137,6 +1175,7 @@ MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str MULT_SAXI_STATUS_REG__RAW = str
MCONTR_LINTILE_EN__RAW = str MCONTR_LINTILE_EN__RAW = str
SENSI2C_ADDR_MASK__TYPE = str SENSI2C_ADDR_MASK__TYPE = str
SENSOR12BITS_NVLO__RAW = str
CAMSYNC_EXTERNAL_BIT__TYPE = str CAMSYNC_EXTERNAL_BIT__TYPE = str
CMPRS_BASE_INC__RAW = str CMPRS_BASE_INC__RAW = str
SENS_SYNC_FBITS = int SENS_SYNC_FBITS = int
...@@ -1147,6 +1186,7 @@ MEMBRIDGE_CTRL__TYPE = str ...@@ -1147,6 +1186,7 @@ MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str LOGGER_CONF_GPS_BITS__RAW = str
SENSOR12BITS_TDDO__TYPE = str
MULTICLK_DIV_SYNC = int MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str CLK_DIV_PHASE__TYPE = str
...@@ -1156,6 +1196,7 @@ CLKFBOUT_USE_FINE_PS__RAW = str ...@@ -1156,6 +1196,7 @@ CLKFBOUT_USE_FINE_PS__RAW = str
CMPRS_FRMT_LMARG__RAW = str CMPRS_FRMT_LMARG__RAW = str
CMDFRAMESEQ_IRQ_BIT__RAW = str CMDFRAMESEQ_IRQ_BIT__RAW = str
LOGGER_BIT_DURATION = int LOGGER_BIT_DURATION = int
FCLK1_PERIOD__TYPE = str
CAMSYNC_MODE__TYPE = str CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str CHNBUF_READ_LATENCY__RAW = str
NUM_CYCLES_12__RAW = str NUM_CYCLES_12__RAW = str
...@@ -1173,6 +1214,7 @@ PXD_IBUF_LOW_PWR__RAW = str ...@@ -1173,6 +1214,7 @@ PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str CLK_CNTRL__TYPE = str
HISTOGRAM_WIDTH__RAW = str
GPIO_MASK__RAW = str GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str SENS_GAMMA_MODE_REPET__TYPE = str
...@@ -1193,6 +1235,7 @@ SENS_SYNC_FBITS__TYPE = str ...@@ -1193,6 +1235,7 @@ SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str HISPI_UNTUNED_SPLIT = str
MCONTR_TOP_0BIT_ADDR_MASK = int MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str HISPI_IBUF_DELAY_VALUE__TYPE = str
SENSOR12BITS_NGPL = int
CMDFRAMESEQ_REL = int CMDFRAMESEQ_REL = int
CAMSYNC_POST_MAGIC__TYPE = str CAMSYNC_POST_MAGIC__TYPE = str
NUM_CYCLES_29__TYPE = str NUM_CYCLES_29__TYPE = str
...@@ -1210,6 +1253,7 @@ MEMCLK_CAPACITANCE__TYPE = str ...@@ -1210,6 +1253,7 @@ MEMCLK_CAPACITANCE__TYPE = str
MCONTR_BUF0_WR_ADDR__RAW = str MCONTR_BUF0_WR_ADDR__RAW = str
SENS_GAMMA_MODE_WIDTH = int SENS_GAMMA_MODE_WIDTH = int
SENS_SS_MODE = str SENS_SS_MODE = str
SENSOR12BITS_TDDO = int
CAMSYNC_TRIG_DST = int CAMSYNC_TRIG_DST = int
DLY_LANE1_ODELAY__TYPE = str DLY_LANE1_ODELAY__TYPE = str
CMPRS_AFIMUX_WIDTH__TYPE = str CMPRS_AFIMUX_WIDTH__TYPE = str
...@@ -1225,6 +1269,7 @@ CMPRS_COLOR18 = int ...@@ -1225,6 +1269,7 @@ CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str MCNTRL_TILED_MASK__RAW = str
MULTICLK_DIV_AXIHP__RAW = str MULTICLK_DIV_AXIHP__RAW = str
SENSI2C_CMD_SOFT_SDA__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str MCNTRL_TILED_STATUS_CNTRL__RAW = str
...@@ -1260,6 +1305,7 @@ SENS_REF_JITTER1 = float ...@@ -1260,6 +1305,7 @@ SENS_REF_JITTER1 = float
SENS_REF_JITTER2 = float SENS_REF_JITTER2 = float
MCNTRL_TILED_FRAME_SIZE__RAW = str MCNTRL_TILED_FRAME_SIZE__RAW = str
MULT_SAXI_HALF_BRAM__RAW = str MULT_SAXI_HALF_BRAM__RAW = str
SIMUL_AXI_READ_WIDTH__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str DFLT_DQS_TRI_ON_PATTERN__RAW = str
SLEW_DQ = str SLEW_DQ = str
SENS_GAMMA_MODE_REPET__RAW = str SENS_GAMMA_MODE_REPET__RAW = str
...@@ -1269,6 +1315,7 @@ SLEW_DQS__TYPE = str ...@@ -1269,6 +1315,7 @@ SLEW_DQS__TYPE = str
SENSIO_ADDR_MASK = int SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int SCANLINE_STARTY = int
SCANLINE_STARTX = int SCANLINE_STARTX = int
SIMULATE_CMPRS_CMODE1__RAW = str
FFCLK0_DIFF_TERM__TYPE = str FFCLK0_DIFF_TERM__TYPE = str
HISPI_UNTUNED_SPLIT__TYPE = str HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str LD_DLY_CMDA__TYPE = str
...@@ -1280,7 +1327,9 @@ SENSI2C_IOSTANDARD__TYPE = str ...@@ -1280,7 +1327,9 @@ SENSI2C_IOSTANDARD__TYPE = str
REFCLK_FREQUENCY__TYPE = str REFCLK_FREQUENCY__TYPE = str
CLKOUT_DIV_PCLK2X__TYPE = str CLKOUT_DIV_PCLK2X__TYPE = str
MEMBRIDGE_CTRL = int MEMBRIDGE_CTRL = int
CMPRS_TIMEOUT__TYPE = str SENSOR_IMAGE_TYPE3__TYPE = str
HISTOGRAM_LEFT = int
MULT_SAXI_HALF_BRAM__TYPE = str
MCONTR_PHY_STATUS_CNTRL = int MCONTR_PHY_STATUS_CNTRL = int
SENSOR_GROUP_ADDR = int SENSOR_GROUP_ADDR = int
NUM_CYCLES_14 = int NUM_CYCLES_14 = int
...@@ -1309,6 +1358,7 @@ HISTOGRAM_RADDR1 = int ...@@ -1309,6 +1358,7 @@ HISTOGRAM_RADDR1 = int
HISTOGRAM_RADDR2 = int HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR3 = int HISTOGRAM_RADDR3 = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
HISTOGRAM_LEFT__TYPE = str
SENS_LENS_AY_MASK__TYPE = str SENS_LENS_AY_MASK__TYPE = str
SENS_CTRL_IGNORE_EMBED__RAW = str SENS_CTRL_IGNORE_EMBED__RAW = str
READ_BLOCK_OFFSET__TYPE = str READ_BLOCK_OFFSET__TYPE = str
...@@ -1320,10 +1370,12 @@ MCNTRL_TEST01_CHN2_MODE = int ...@@ -1320,10 +1370,12 @@ MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str CMPRS_NUM_AFI_CHN__RAW = str
SENSOR_IMAGE_TYPE3 = str
MULTICLK_DIV_AXIHP__TYPE = str MULTICLK_DIV_AXIHP__TYPE = str
HISPI_DELAY_CLK2__TYPE = str HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int MULT_SAXI_ADV_RD = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str WSEL__RAW = str
SENSOR_PRIORITY = int
DLY_PHASE__TYPE = str DLY_PHASE__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_STATUS_REG_ADDR__TYPE = str MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
...@@ -1347,7 +1399,9 @@ WBUF_DLY_DFLT = int ...@@ -1347,7 +1399,9 @@ WBUF_DLY_DFLT = int
SENS_JTAG_PROG = int SENS_JTAG_PROG = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
FFCLK0_IOSTANDARD = str FFCLK0_IOSTANDARD = str
AXI_TASK_HOLD__TYPE = str
SENS_GAMMA_ADDR_MASK__RAW = str SENS_GAMMA_ADDR_MASK__RAW = str
SENSOR_IMAGE_TYPE3__RAW = str
DLY_LANE1_IDELAY__TYPE = str DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str DEBUG_MASK__RAW = str
...@@ -1369,12 +1423,15 @@ DLY_CMDA = long ...@@ -1369,12 +1423,15 @@ DLY_CMDA = long
SENS_GAMMA_MODE_BAYER = int SENS_GAMMA_MODE_BAYER = int
LAST_BUF_FRAME__TYPE = str LAST_BUF_FRAME__TYPE = str
CMPRS_HIFREQ_REG_BASE = int CMPRS_HIFREQ_REG_BASE = int
FCLK1_PERIOD__RAW = str
MCONTR_ARBIT_ADDR = int MCONTR_ARBIT_ADDR = int
MEMBRIDGE_CTRL__RAW = str MEMBRIDGE_CTRL__RAW = str
CMPRS_CBIT_RUN_RST__RAW = str CMPRS_CBIT_RUN_RST__RAW = str
TABLE_QUANTIZATION_INDEX = int TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str NUM_CYCLES_04__TYPE = str
WSEL__RAW = str SENSOR_IMAGE_TYPE2 = str
SENSOR_IMAGE_TYPE1 = str
SENSOR_IMAGE_TYPE0 = str
SENS_CTRL_IGNORE_EMBED = int SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int MCNTRL_TILED_PENDING_CNTR_BITS = int
...@@ -1387,9 +1444,11 @@ CAMSYNC_TRIG_DELAY1__TYPE = str ...@@ -1387,9 +1444,11 @@ CAMSYNC_TRIG_DELAY1__TYPE = str
HIGH_PERFORMANCE_MODE = str HIGH_PERFORMANCE_MODE = str
DQTRI_LAST__RAW = str DQTRI_LAST__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
SIMULATE_CMPRS_CMODE3__TYPE = str
DFLT_DQM_PATTERN = int DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int SENSI2C_CMD_RUN = int
AXI_WRDATA_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
NUM_CYCLES_04 = int NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str SENS_LENS_C__TYPE = str
...@@ -1449,6 +1508,7 @@ INITIALIZE_OFFSET__TYPE = str ...@@ -1449,6 +1508,7 @@ INITIALIZE_OFFSET__TYPE = str
SENSOR_FIFO_DELAY__TYPE = str SENSOR_FIFO_DELAY__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str LOGGER_CONF_IMU_BITS__TYPE = str
IDELAY_VALUE__TYPE = str IDELAY_VALUE__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str CMPRS_CBIT_CMODE_JP4DC__TYPE = str
PICKLE__TYPE = str PICKLE__TYPE = str
SENSI2C_TBL_NBWR__RAW = str SENSI2C_TBL_NBWR__RAW = str
...@@ -1466,6 +1526,7 @@ SENSI2C_CTRL = int ...@@ -1466,6 +1526,7 @@ SENSI2C_CTRL = int
SENS_SYNC_MULT = int SENS_SYNC_MULT = int
CLK_ADDR__RAW = str CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str SENSIO_CTRL__RAW = str
HISTOGRAM_WIDTH__TYPE = str
MCNTRL_TILED_TILE_WHS = int MCNTRL_TILED_TILE_WHS = int
NUM_CYCLES_03__RAW = str NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int MULT_SAXI_HALF_BRAM = int
...@@ -1482,12 +1543,14 @@ MCONTR_TOP_0BIT_ADDR = int ...@@ -1482,12 +1543,14 @@ MCONTR_TOP_0BIT_ADDR = int
NUM_CYCLES_05__RAW = str NUM_CYCLES_05__RAW = str
MEMBRIDGE_MODE = int MEMBRIDGE_MODE = int
MCNTRL_TILED_FRAME_LAST__TYPE = str MCNTRL_TILED_FRAME_LAST__TYPE = str
QUADRANTS_PXD_HACT_VACT__RAW = str
MCONTR_CMPRS_STATUS_INC__RAW = str MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int CMPRS_CBIT_CMODE_JP4DIFFHDR = int
TABLE_CORING_INDEX__RAW = str TABLE_CORING_INDEX__RAW = str
SENSI2C_CMD_RESET__TYPE = str SENSI2C_CMD_RESET__TYPE = str
MCONTR_ARBIT_ADDR__TYPE = str MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str CAMSYNC_TRIG_DELAY1__RAW = str
AXI_TASK_HOLD = float
ADDRESS_NUMBER = int ADDRESS_NUMBER = int
SENS_SYNC_LATE__TYPE = str SENS_SYNC_LATE__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
...@@ -1536,6 +1599,8 @@ CMPRS_CBIT_BAYER_BITS = int ...@@ -1536,6 +1599,8 @@ CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str PXD_SLEW__RAW = str
MULT_SAXI_STATUS_REG = int MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str CLKIN_PERIOD_SENSOR__TYPE = str
QUADRANTS_PXD_HACT_VACT__TYPE = str
SENSOR_PRIORITY__TYPE = str
SENS_LENS_BY__RAW = str SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str MCNTRL_PS_CMD__TYPE = str
SENS_SYNC_MASK__RAW = str SENS_SYNC_MASK__RAW = str
...@@ -1578,11 +1643,11 @@ GPIO_SLEW__RAW = str ...@@ -1578,11 +1643,11 @@ GPIO_SLEW__RAW = str
MULTICLK_PHASE_DLYREF__TYPE = str MULTICLK_PHASE_DLYREF__TYPE = str
TEST01_START_FRAME__RAW = str TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str CMDFRAMESEQ_ABS__RAW = str
CMPRS_AFIMUX_SA_LEN__RAW = str FRAME_WIDTH_ROUND_BITS__TYPE = str
BUF_IPCLK2X_SENS0__RAW = str BUF_IPCLK2X_SENS0__RAW = str
MCONTR_BUF4_WR_ADDR__RAW = str MCONTR_BUF4_WR_ADDR__RAW = str
CLK_STATUS__TYPE = str DFLT_DQM_PATTERN__RAW = str
CMPRS_COLOR20__TYPE = str CMPRS_CSAT_CB__TYPE = str
T_REFI__TYPE = str T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str MCONTR_CMD_WR_ADDR__TYPE = str
SENSI2C_CMD_SOFT_SCL__TYPE = str SENSI2C_CMD_SOFT_SCL__TYPE = str
...@@ -1594,6 +1659,7 @@ MCNTRL_TEST01_MASK = int ...@@ -1594,6 +1659,7 @@ MCNTRL_TEST01_MASK = int
TEST01_NEXT_PAGE__RAW = str TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str HIST_SAXI_MODE_ADDR_MASK__RAW = str
FFCLK1_IBUF_LOW_PWR__TYPE = str FFCLK1_IBUF_LOW_PWR__TYPE = str
SENSOR12BITS_NVLO__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str MCONTR_LINTILE_EXTRAPG__TYPE = str
NUM_CYCLES_06__TYPE = str NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str SCANLINE_STARTX__RAW = str
...@@ -1610,8 +1676,9 @@ WRITELEV_OFFSET__RAW = str ...@@ -1610,8 +1676,9 @@ WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int READ_PATTERN_OFFSET = int
CLK_PHASE__TYPE = str CLK_PHASE__TYPE = str
SENSOR_16BIT_BIT = int SENSOR_16BIT_BIT = int
MCNTRL_PS_STATUS_REG_ADDR = int SENSIO_DELAYS__TYPE = str
SENS_CTRL_EXT_CLK__RAW = str SENS_CTRL_EXT_CLK__RAW = str
WOI_HEIGHT = int
LOGGER_PAGE_GPS__TYPE = str LOGGER_PAGE_GPS__TYPE = str
T_REFI = int T_REFI = int
HIST_CONFIRM_WRITE__TYPE = str HIST_CONFIRM_WRITE__TYPE = str
...@@ -1651,6 +1718,7 @@ HIGH_PERFORMANCE_MODE__RAW = str ...@@ -1651,6 +1718,7 @@ HIGH_PERFORMANCE_MODE__RAW = str
DFLT_DQM_PATTERN__TYPE = str DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str STATUS_ADDR__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int MCONTR_PHY_0BIT_CMDA_EN = int
WOI_WIDTH = int
CMPRS_AFIMUX_WIDTH__RAW = str CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str BUF_CLK1X_PCLK2X = str
MCNTRL_TEST01_CHN4_MODE = int MCNTRL_TEST01_CHN4_MODE = int
...@@ -1666,6 +1734,7 @@ INITIALIZE_OFFSET__RAW = str ...@@ -1666,6 +1734,7 @@ INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str CMPRS_AFIMUX_RST__RAW = str
SENSOR12BITS_TDDO__RAW = str
CAMSYNC_TRIG_DST__RAW = str CAMSYNC_TRIG_DST__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str CAMSYNC_TRIG_DELAY3__TYPE = str
...@@ -1673,6 +1742,7 @@ FRAME_START_ADDRESS__RAW = str ...@@ -1673,6 +1742,7 @@ FRAME_START_ADDRESS__RAW = str
IPCLK_PHASE = float IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int SENSI2C_CTRL_RADDR = int
HIST_SAXI_MODE_ADDR_REL__RAW = str HIST_SAXI_MODE_ADDR_REL__RAW = str
AXI_WRDATA_LATENCY = int
SENS_CTRL_QUADRANTS_EN = int SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str MULTICLK_PHASE_FB__TYPE = str
...@@ -1690,11 +1760,12 @@ MEMCLK_IOSTANDARD = str ...@@ -1690,11 +1760,12 @@ MEMCLK_IOSTANDARD = str
DLY_LANE1_ODELAY__RAW = str DLY_LANE1_ODELAY__RAW = str
SENSI2C_IBUF_LOW_PWR__RAW = str SENSI2C_IBUF_LOW_PWR__RAW = str
SENSI2C_STATUS_REG_REL = int SENSI2C_STATUS_REG_REL = int
MULT_SAXI_HALF_BRAM__TYPE = str AXI_RDADDR_LATENCY__RAW = str
SENSOR_CTRL_ADDR_MASK = int SENSOR_CTRL_ADDR_MASK = int
NUM_CYCLES_16__TYPE = str NUM_CYCLES_16__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str MEMBRIDGE_LO_ADDR64__TYPE = str
CMDFRAMESEQ_MASK__RAW = str CMDFRAMESEQ_MASK__RAW = str
SENSOR12BITS_TMD__TYPE = str
SENS_CTRL_LD_DLY__TYPE = str SENS_CTRL_LD_DLY__TYPE = str
MCONTR_TOP_16BIT_ADDR__TYPE = str MCONTR_TOP_16BIT_ADDR__TYPE = str
PXD_SLEW = str PXD_SLEW = str
...@@ -1753,8 +1824,10 @@ LOGGER_STATUS_MASK = int ...@@ -1753,8 +1824,10 @@ LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str HISPI_CAPACITANCE = str
HISTOGRAM_START_PAGE__RAW = str
CONTROL_ADDR_MASK = int CONTROL_ADDR_MASK = int
LOGGER_PERIOD = int LOGGER_PERIOD = int
MEMCLK_PERIOD__RAW = str
MCONTR_BUF0_WR_ADDR = int MCONTR_BUF0_WR_ADDR = int
MCNTRL_PS_STATUS_REG_ADDR__RAW = str MCNTRL_PS_STATUS_REG_ADDR__RAW = str
LOGGER_STATUS_MASK__RAW = str LOGGER_STATUS_MASK__RAW = str
...@@ -1777,6 +1850,7 @@ SENS_REF_JITTER2__RAW = str ...@@ -1777,6 +1850,7 @@ SENS_REF_JITTER2__RAW = str
SCANLINE_EXTRA_PAGES__RAW = str SCANLINE_EXTRA_PAGES__RAW = str
CMDSEQMUX_STATUS__RAW = str CMDSEQMUX_STATUS__RAW = str
MCONTR_PHY_0BIT_SDRST_ACT__RAW = str MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
SENSOR_IMAGE_TYPE0__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
DIVCLK_DIVIDE_PCLK = int DIVCLK_DIVIDE_PCLK = int
MCNTRL_PS_MASK = int MCNTRL_PS_MASK = int
...@@ -1806,6 +1880,7 @@ SENS_LENS_SCALES__TYPE = str ...@@ -1806,6 +1880,7 @@ SENS_LENS_SCALES__TYPE = str
SENS_LENS_COEFF__TYPE = str SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str LOGGER_STATUS__RAW = str
SENS_JTAG_TMS__RAW = str SENS_JTAG_TMS__RAW = str
FRAME_WIDTH_ROUND_BITS__RAW = str
FFCLK0_IBUF_LOW_PWR__RAW = str FFCLK0_IBUF_LOW_PWR__RAW = str
SENS_CTRL_MRST = int SENS_CTRL_MRST = int
MCNTRL_SCANLINE_FRAME_LAST__TYPE = str MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
...@@ -1813,6 +1888,7 @@ MCONTR_SENS_STATUS_BASE__RAW = str ...@@ -1813,6 +1888,7 @@ MCONTR_SENS_STATUS_BASE__RAW = str
MCNTRL_TEST01_CHN3_MODE__TYPE = str MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCONTR_BUF2_RD_ADDR__TYPE = str MCONTR_BUF2_RD_ADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str SENS_SYNC_RADDR__RAW = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
CLKFBOUT_PHASE_SENSOR__TYPE = str CLKFBOUT_PHASE_SENSOR__TYPE = str
SENSOR_HIST_NRST_BITS__TYPE = str SENSOR_HIST_NRST_BITS__TYPE = str
...@@ -1821,12 +1897,14 @@ RTC_STATUS_REG_ADDR__TYPE = str ...@@ -1821,12 +1897,14 @@ RTC_STATUS_REG_ADDR__TYPE = str
SENS_JTAG_TCK__TYPE = str SENS_JTAG_TCK__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
SENS_LENS_COEFF = int SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str MULTICLK_PHASE_XCLK__RAW = str
LOGGER_BIT_DURATION__RAW = str LOGGER_BIT_DURATION__RAW = str
MCONTR_WR_MASK__TYPE = str MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str SENS_LENS_C__RAW = str
CMDFRAMESEQ_ADDR_BASE__TYPE = str CMDFRAMESEQ_ADDR_BASE__TYPE = str
AXI_WRDATA_LATENCY__TYPE = str
SENS_GAMMA_HEIGHT01 = int SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
...@@ -1845,6 +1923,7 @@ CMPRS_INTERRUPTS = int ...@@ -1845,6 +1923,7 @@ CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int CMDSEQMUX_MASK = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MEMCLK_CAPACITANCE__RAW = str MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int DQTRI_FIRST = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
...@@ -1852,6 +1931,7 @@ CAMSYNC_TRIG_DELAY0 = int ...@@ -1852,6 +1931,7 @@ CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY1 = int CAMSYNC_TRIG_DELAY1 = int
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
CAMSYNC_TRIG_DELAY3 = int CAMSYNC_TRIG_DELAY3 = int
SIMUL_AXI_READ_WIDTH__RAW = str
MCONTR_SENS_STATUS_INC = int MCONTR_SENS_STATUS_INC = int
CAMSYNC_TRIGGERED_BIT__TYPE = str CAMSYNC_TRIGGERED_BIT__TYPE = str
SENS_GAMMA_MODE_TRIG__TYPE = str SENS_GAMMA_MODE_TRIG__TYPE = str
...@@ -1876,6 +1956,7 @@ TABLE_CORING_INDEX__TYPE = str ...@@ -1876,6 +1956,7 @@ TABLE_CORING_INDEX__TYPE = str
HISTOGRAM_RADDR1__RAW = str HISTOGRAM_RADDR1__RAW = str
SENSI2C_CMD_TAND__TYPE = str SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
SENS_BANDWIDTH = str
MCNTRL_SCANLINE_MODE__RAW = str MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str LOGGER_BIT_HALF_PERIOD__TYPE = str
FRAME_START_ADDRESS_INC__RAW = str FRAME_START_ADDRESS_INC__RAW = str
...@@ -1926,6 +2007,8 @@ SENS_PHASE_WIDTH__RAW = str ...@@ -1926,6 +2007,8 @@ SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str FFCLK0_IBUF_LOW_PWR = str
DFLT_DQ_TRI_ON_PATTERN__TYPE = str DFLT_DQ_TRI_ON_PATTERN__TYPE = str
FRAME_WIDTH_ROUND_BITS = int
LD_DLY_LANE1_IDELAY__TYPE = str
CMPRS_AFIMUX_MODE__TYPE = str CMPRS_AFIMUX_MODE__TYPE = str
DQTRI_FIRST__TYPE = str DQTRI_FIRST__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
...@@ -1983,7 +2066,7 @@ DLY_DQ_ODELAY__RAW = str ...@@ -1983,7 +2066,7 @@ DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str CMDFRAMESEQ_MASK__TYPE = str
FFCLK1_IOSTANDARD = str SENS_JTAG_TMS__TYPE = str
CLK_PHASE__RAW = str CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str GPIO_MASK__TYPE = str
...@@ -2006,6 +2089,7 @@ CMPRS_JP4 = int ...@@ -2006,6 +2089,7 @@ CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str MULTICLK_BUF_XCLK = str
HISTOGRAM_START_PAGE__TYPE = str
MCNTRL_SCANLINE_MODE = int MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = long DLY_LANE0_IDELAY = long
MCNTRL_PS_CMD = int MCNTRL_PS_CMD = int
...@@ -2033,6 +2117,7 @@ SENS_LENS_AY__RAW = str ...@@ -2033,6 +2117,7 @@ SENS_LENS_AY__RAW = str
SS_EN = str SS_EN = str
SENSI2C_CMD_TAND__RAW = str SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str WINDOW_HEIGHT__TYPE = str
SENSOR_IMAGE_TYPE2__TYPE = str
IBUF_LOW_PWR__TYPE = str IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float CLK_DIV_PHASE = float
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
...@@ -2045,7 +2130,7 @@ NUM_CYCLES_11__RAW = str ...@@ -2045,7 +2130,7 @@ NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str SENSI2C_DRIVE__RAW = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSI2C_CMD_SOFT_SDA__RAW = str SENS_LENS_C = int
SENSOR_CTRL_ADDR_MASK__RAW = str SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int NUM_CYCLES_LOW_BIT = int
...@@ -2093,6 +2178,7 @@ DFLT_WBUF_DELAY = int ...@@ -2093,6 +2178,7 @@ DFLT_WBUF_DELAY = int
CONTROL_RBACK_ADDR_MASK__RAW = str CONTROL_RBACK_ADDR_MASK__RAW = str
AXI_WR_ADDR_BITS__TYPE = str AXI_WR_ADDR_BITS__TYPE = str
RTC_SET_STATUS = int RTC_SET_STATUS = int
SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR__TYPE = str MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int FRAME_FULL_WIDTH = int
...@@ -2144,13 +2230,14 @@ MCONTR_LINTILE_REPEAT__RAW = str ...@@ -2144,13 +2230,14 @@ MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str CMPRS_INTERRUPTS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
WOI_HEIGHT__TYPE = str
STATUS_SEQ_SHFT__TYPE = str STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int MCONTR_CMPRS_BASE = int
DEBUG_SET_STATUS__TYPE = str DEBUG_SET_STATUS__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str HISTOGRAM_START_PAGE = int
RTC_SEC_USEC_ADDR__RAW = str RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int MCNTRL_PS_ADDR = int
SENS_BANDWIDTH = str HISTOGRAM_HEIGHT__RAW = str
MEMCLK_IBUF_LOW_PWR = str MEMCLK_IBUF_LOW_PWR = str
HISPI_DELAY_CLK3__RAW = str HISPI_DELAY_CLK3__RAW = str
CAMSYNC_TRIG_DST__TYPE = str CAMSYNC_TRIG_DST__TYPE = str
...@@ -2171,6 +2258,7 @@ SENSI2C_REL_RADDR__RAW = str ...@@ -2171,6 +2258,7 @@ SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str SENSI2C_REL_RADDR__TYPE = str
AXI_WRADDR_LATENCY__RAW = str
GPIO_DRIVE = int GPIO_DRIVE = int
HISPI_MSB_FIRST__RAW = str HISPI_MSB_FIRST__RAW = str
SENS_LENS_SCALES = int SENS_LENS_SCALES = int
...@@ -2190,12 +2278,14 @@ HISPI_DELAY_CLK2__RAW = str ...@@ -2190,12 +2278,14 @@ HISPI_DELAY_CLK2__RAW = str
SS_MOD_PERIOD__TYPE = str SS_MOD_PERIOD__TYPE = str
TILE_HEIGHT = int TILE_HEIGHT = int
MULT_SAXI_MASK__RAW = str MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str NUM_CYCLES_10__RAW = str
SENS_LENS_FAT0_OUT__TYPE = str SENS_LENS_FAT0_OUT__TYPE = str
DEBUG_SHIFT_DATA__RAW = str DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int SENS_NUM_SUBCHN = int
FRAME_HEIGHT_BITS = int
MCONTR_BUF0_WR_ADDR__TYPE = str MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str CMPRS_COLOR18__RAW = str
......
py393/x393_axi_control_status.py
View file @ 6a2bdfd7
...@@ -364,7 +364,10 @@ class X393AxiControlStatus(object): ...@@ -364,7 +364,10 @@ class X393AxiControlStatus(object):
print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8))) print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8)))
print ("MEMBRIDGE_STATUS_REG: %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8))) print ("MEMBRIDGE_STATUS_REG: %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8)))
items_per_line = 8 items_per_line = 8
for i in range (256): r = range(256)
if self.DRY_MODE:
r=(0,1,2,3,4,5,6,7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff)
for i in r:
if not i % items_per_line: if not i % items_per_line:
print ("\n0x%02x: "%(i), end = "") print ("\n0x%02x: "%(i), end = "")
d=hx(self.read_status(i),8) d=hx(self.read_status(i),8)
......
py393/x393_mem.py
View file @ 6a2bdfd7
...@@ -32,6 +32,15 @@ import mmap ...@@ -32,6 +32,15 @@ import mmap
#import sys #import sys
import struct import struct
import os import os
import sys
import traceback
sys.path.append(os.path.abspath(os.path.dirname(sys.argv[0])+'/../cocotb'))
from socket_command import x393Client
DBG_CNTR=0
X393_CLIENT = None
class X393Mem(object): class X393Mem(object):
''' '''
classdocs classdocs
...@@ -47,16 +56,40 @@ class X393Mem(object): ...@@ -47,16 +56,40 @@ class X393Mem(object):
# 2.7.11 does not need subtraction(and reports error if negative) # 2.7.11 does not need subtraction(and reports error if negative)
def __init__(self, debug_mode=1,dry_mode=False, maxi_port=0): def __init__(self, debug_mode=1,dry_mode=False, maxi_port=0):
if maxi_port: global DBG_CNTR
self.MAXI_BASE=self.MAXI1_BASE global X393_CLIENT
else: """
self.MAXI_BASE=self.MAXI0_BASE; print('dry_mode = ',dry_mode,', DBG_CNTR=',DBG_CNTR)
self.DEBUG_MODE=debug_mode traceback.print_stack()
"""
if not dry_mode: if not dry_mode:
if not os.path.exists("/dev/xdevcfg"): if not os.path.exists("/dev/xdevcfg"):
dry_mode=True dry_mode=True
print("Program is forced to run in SIMULATED mode as '/dev/xdevcfg' does not exist (not a camera)") print("Program is forced to run in SIMULATED mode as '/dev/xdevcfg' does not exist (not a camera)")
self.DRY_MODE=dry_mode self.DRY_MODE=dry_mode
if (dry_mode) and (X393_CLIENT is None):
print("Creating X393_CLIENT")
try:
X393_CLIENT= x393Client(host=dry_mode.split(":")[0], port=int(dry_mode.split(":")[1]))
print("Created X393_CLIENT")
except:
X393_CLIENT= True
print("Failed to create X393_CLIENT")
if not X393_CLIENT is True:
print("Starting X393_CLIENT")
try:
X393_CLIENT.start()
except:
print ("Failed to communicate to the server. Is it started? Swithching to dry tun mode")
X393_CLIENT = True
DBG_CNTR+=1
if maxi_port:
self.MAXI_BASE=self.MAXI1_BASE
else:
self.MAXI_BASE=self.MAXI0_BASE;
self.DEBUG_MODE=debug_mode
def maxi_base(self, maxi_port=None): def maxi_base(self, maxi_port=None):
if not maxi_port is None: if not maxi_port is None:
if maxi_port: if maxi_port:
...@@ -86,7 +119,20 @@ class X393Mem(object): ...@@ -86,7 +119,20 @@ class X393Mem(object):
return mmap.mmap(f.fileno(), self.PAGE_SIZE, offset = page_addr - (1<<32)) return mmap.mmap(f.fileno(), self.PAGE_SIZE, offset = page_addr - (1<<32))
else: else:
return mmap.mmap(f.fileno(), self.PAGE_SIZE, offset = page_addr) return mmap.mmap(f.fileno(), self.PAGE_SIZE, offset = page_addr)
def finish(self):
"""
Finish simulation, if server is opened
"""
global X393_CLIENT
if X393_CLIENT is None:
print ("Not running in simulated mode")
return
elif X393_CLIENT is True:
print ("Not running as a client to x393 simulation server")
return
else:
X393_CLIENT.stop()
X393_CLIENT = True # just simulated mode
def write_mem (self,addr, data,quiet=1): def write_mem (self,addr, data,quiet=1):
""" """
...@@ -95,9 +141,17 @@ class X393Mem(object): ...@@ -95,9 +141,17 @@ class X393Mem(object):
@param data - 32-bit data to write @param data - 32-bit data to write
@param quiet - reduce output @param quiet - reduce output
""" """
if self.DRY_MODE: if X393_CLIENT is True:
# if self.DRY_MODE:
print ("simulated: write_mem(0x%x,0x%x)"%(addr,data)) print ("simulated: write_mem(0x%x,0x%x)"%(addr,data))
return return
elif not X393_CLIENT is None:
if quiet < 1:
print ("remote: write_mem(0x%x,0x%x)"%(addr,data))
X393_CLIENT.write(addr, [data])
if quiet < 2:
print ("remote: write_mem done" )
return
with open("/dev/mem", "r+b") as f: with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1)) page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr page_offs=addr-page_addr
...@@ -108,7 +162,7 @@ class X393Mem(object): ...@@ -108,7 +162,7 @@ class X393Mem(object):
packedData=struct.pack(self.ENDIAN+"L",data) packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0] d=struct.unpack(self.ENDIAN+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData mm[page_offs:page_offs+4]=packedData
if quiet <1: if quiet <2:
print ("0x%08x <== 0x%08x (%d)"%(addr,d,d)) print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
''' '''
if MONITOR_EMIO and VEBOSE: if MONITOR_EMIO and VEBOSE:
...@@ -125,7 +179,19 @@ class X393Mem(object): ...@@ -125,7 +179,19 @@ class X393Mem(object):
Read 32-bit word from physical memory Read 32-bit word from physical memory
@param addr physical byte address @param addr physical byte address
@param quiet - reduce output @param quiet - reduce output
''' '''
if X393_CLIENT is True:
# if self.DRY_MODE:
print ("simulated: read_mem(0x%x)"%(addr))
return addr # just some data
elif not X393_CLIENT is None:
if quiet < 1:
print ("remote: read_mem(0x%x)"%(addr))
data= X393_CLIENT.read(addr)
if quiet < 1:
print ("remote: read_mem done: 0x%08x"%(data[0]))
return data[0]
if self.DRY_MODE: if self.DRY_MODE:
print ("simulated: read_mem(0x%x)"%(addr)) print ("simulated: read_mem(0x%x)"%(addr))
return addr # just some data return addr # just some data
......
py393/x393_sens_cmprs.py
View file @ 6a2bdfd7
...@@ -124,9 +124,10 @@ SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24. ...@@ -124,9 +124,10 @@ SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}} # x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3}, SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}} x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}}
#SENSOR_DEFAULTS_SIMULATION= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}}
class X393SensCmprs(object): class X393SensCmprs(object):
DRY_MODE = True # True DRY_MODE = True # True
DEBUG_MODE = 1 DEBUG_MODE = 1
...@@ -147,8 +148,25 @@ class X393SensCmprs(object): ...@@ -147,8 +148,25 @@ class X393SensCmprs(object):
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None): def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
# global BUFFER_ADDRESS, BUFFER_LEN # global BUFFER_ADDRESS, BUFFER_LEN
global BUFFER_ADDRESS, BUFFER_LEN, COMMAND_ADDRESS, DATAIN_ADDRESS, DATAOUT_ADDRESS global BUFFER_ADDRESS, BUFFER_LEN, COMMAND_ADDRESS, DATAIN_ADDRESS, DATAOUT_ADDRESS
global BUFFER_ADDRESS_H2D, BUFFER_LEN_H2D, BUFFER_ADDRESS_D2H, BUFFER_LEN_D2H, BUFFER_ADDRESS_BIDIR, BUFFER_LEN_BIDIR global BUFFER_ADDRESS_H2D, BUFFER_LEN_H2D, BUFFER_ADDRESS_D2H, BUFFER_LEN_D2H, BUFFER_ADDRESS_BIDIR, BUFFER_LEN_BIDIR
# global SENSOR_DEFAULTS_SIMULATION
print ("X393SensCmprs.__init__: dry_mode=",dry_mode)
try:
if ":" in dry_mode:
print ("X393SensCmprs.__init__: setting SENSOR_DEFAULTS")
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["left"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["left"]= 0
print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS)
except:
print ("No simulation server is used, just running in dry mode")
self.DEBUG_MODE= debug_mode self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode) self.x393_mem= X393Mem(debug_mode,dry_mode)
...@@ -2112,11 +2130,16 @@ class X393SensCmprs(object): ...@@ -2112,11 +2130,16 @@ class X393SensCmprs(object):
elif direction.upper()[0] in "B": elif direction.upper()[0] in "B":
return "_bidir" return "_bidir"
def sync_for_cpu(self, direction, saddr=None, leng=None): def sync_for_cpu(self, direction, saddr=None, leng=None):
if self.DRY_MODE:
print ("Simulating sync_for_cpu(),",self.get_mem_buf_args(saddr, leng)," -> ",MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction))
return
with open (MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction),"w") as f: with open (MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, leng),file=f) print (self.get_mem_buf_args(saddr, leng),file=f)
def sync_for_device(self, direction, saddr=None, leng=None): def sync_for_device(self, direction, saddr=None, leng=None):
if self.DRY_MODE:
print ("Simulating sync_for_device(),",self.get_mem_buf_args(saddr, leng)," -> ",MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction))
return
with open (MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction),"w") as f: with open (MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, leng),file=f) print (self.get_mem_buf_args(saddr, leng),file=f)
""" """
...@@ -2175,7 +2198,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3 ...@@ -2175,7 +2198,7 @@ jpeg_write "img.jpeg" 0 100 None False 0 "/www/pages/" 3
""" """
# Setup for compression of teh simulated data # Setup for compression of the simulated data
def setup_simulated_mode(self, def setup_simulated_mode(self,
data_file = None, data_file = None,
chn = 0, chn = 0,
......
py393/x393_sensor.py
View file @ 6a2bdfd7
...@@ -70,7 +70,7 @@ class X393Sensor(object): ...@@ -70,7 +70,7 @@ class X393Sensor(object):
Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
@return "PAR12" or "HISPI" @return "PAR12" or "HISPI"
""" """
if self.DRY_MODE: if self.DRY_MODE is True:
return SENSOR_INTERFACE_PARALLEL return SENSOR_INTERFACE_PARALLEL
return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI" return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
......
simulation_modules/sim_soc_interrupts.v
View file @ 6a2bdfd7
...@@ -36,7 +36,7 @@ module sim_soc_interrupts #( ...@@ -36,7 +36,7 @@ module sim_soc_interrupts #(
input [NUM_INTERRUPTS-1:0] irq_done, // end of ISR, turn off inta bit, re-enable arbitration input [NUM_INTERRUPTS-1:0] irq_done, // end of ISR, turn off inta bit, re-enable arbitration
output [NUM_INTERRUPTS-1:0] irqs, // synchronized by clock masked interrupts output [NUM_INTERRUPTS-1:0] irqs, // synchronized by clock masked interrupts
output [NUM_INTERRUPTS-1:0] inta, // interrupt acknowledge output [NUM_INTERRUPTS-1:0] inta, // interrupt acknowledge
output main_go // enable main therad to proceed output main_go // enable main thread to proceed
); );
reg [NUM_INTERRUPTS-1:0] inta_r; reg [NUM_INTERRUPTS-1:0] inta_r;
......
simulation_modules/simul_axi_fifo_out.v
View file @ 6a2bdfd7
...@@ -64,34 +64,37 @@ module simul_axi_fifo ...@@ -64,34 +64,37 @@ module simul_axi_fifo
integer out_count; integer out_count;
reg [LATENCY:0] latency_delay_r; reg [LATENCY:0] latency_delay_r;
wire [LATENCY+1:0] latency_delay={latency_delay_r,load};
wire out_inc=latency_delay[LATENCY]; wire out_inc=latency_delay[LATENCY];
wire input_ready_w = in_count<DEPTH;
wire load_and_ready = load & input_ready_w; // Masked load with input_ready 07/06/2016
wire [LATENCY+1:0] latency_delay={latency_delay_r,load_and_ready};
assign data_out= fifo[out_address]; assign data_out= fifo[out_address];
assign valid= out_count!=0; assign valid= out_count!=0;
assign input_ready= in_count<DEPTH;
assign input_ready= input_ready_w;
// assign out_inc={ // assign out_inc={
always @ (posedge clk or posedge reset) begin always @ (posedge clk or posedge reset) begin
if (reset) latency_delay_r <= 0; if (reset) latency_delay_r <= 0;
else latency_delay_r <= latency_delay[LATENCY:0]; else latency_delay_r <= latency_delay[LATENCY:0];
if (reset) in_address <= 0; if (reset) in_address <= 0;
else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1; else if (load_and_ready) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
if (reset) out_address <= 0; if (reset) out_address <= 0;
else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1; else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
if (reset) in_count <= 0; if (reset) in_count <= 0;
else if (!(valid && ready) && load) in_count <= in_count+1; else if (!(valid && ready) && load_and_ready) in_count <= in_count+1;
else if (valid && ready && !load) in_count <= in_count-1; else if (valid && ready && !load_and_ready) in_count <= in_count-1;
if (reset) out_count <= 0; if (reset) out_count <= 0;
else if (!(valid && ready) && out_inc) out_count <= out_count+1; else if (!(valid && ready) && out_inc) out_count <= out_count+1;
else if (valid && ready && !out_inc) out_count <= out_count-1; else if (valid && ready && !out_inc) out_count <= out_count-1;
end end
always @ (posedge clk) begin always @ (posedge clk) begin
if (load) fifo[in_address] <= data_in; if (load_and_ready) fifo[in_address] <= data_in;
end end
endmodule endmodule
\ No newline at end of file
simulation_modules/simul_axi_hp_rd.v
View file @ 6a2bdfd7
...@@ -81,7 +81,8 @@ module simul_axi_hp_rd #( ...@@ -81,7 +81,8 @@ module simul_axi_hp_rd #(
input reg_wr, input reg_wr,
input reg_rd, input reg_rd,
input [31:0] reg_din, input [31:0] reg_din,
output [31:0] reg_dout output [31:0] reg_dout,
output reg_dvalid // register output data valid
); );
localparam AFI_BASECTRL= 32'hf8008000+ (HP_PORT << 12); localparam AFI_BASECTRL= 32'hf8008000+ (HP_PORT << 12);
localparam AFI_RDCHAN_CTRL= AFI_BASECTRL + 'h00; localparam AFI_RDCHAN_CTRL= AFI_BASECTRL + 'h00;
...@@ -162,7 +163,10 @@ module simul_axi_hp_rd #( ...@@ -162,7 +163,10 @@ module simul_axi_hp_rd #(
{25'b0,rdIssueCap1,1'b0,rdIssueCap0}: {25'b0,rdIssueCap1,1'b0,rdIssueCap0}:
( (reg_rd && (reg_addr==AFI_RDQOS))? ( (reg_rd && (reg_addr==AFI_RDQOS))?
{28'b0,rdStaticQos}:32'bz))); {28'b0,rdStaticQos}:32'bz)));
assign reg_dvalid = (reg_rd && ((reg_addr==AFI_RDDATAFIFO_LEVEL) ||
(reg_addr==AFI_RDCHAN_CTRL) ||
(reg_addr==AFI_RDCHAN_ISSUINGCAP) ||
(reg_addr==AFI_RDQOS))) ? 1 : 0;
always @ (posedge aclk or posedge rst) begin always @ (posedge aclk or posedge rst) begin
if (rst) begin if (rst) begin
rdQosHeadOfCmdQEn <= 0; rdQosHeadOfCmdQEn <= 0;
......
simulation_modules/simul_axi_hp_wr.v
View file @ 6a2bdfd7
...@@ -87,7 +87,8 @@ module simul_axi_hp_wr#( ...@@ -87,7 +87,8 @@ module simul_axi_hp_wr#(
input reg_wr, input reg_wr,
input reg_rd, input reg_rd,
input [31:0] reg_din, input [31:0] reg_din,
output [31:0] reg_dout output [31:0] reg_dout,
output reg_dvalid
); );
// localparam ADDRESS_BITS=32; // localparam ADDRESS_BITS=32;
localparam AFI_BASECTRL= 32'hf8008000+ (HP_PORT << 12); localparam AFI_BASECTRL= 32'hf8008000+ (HP_PORT << 12);
...@@ -179,6 +180,10 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored ...@@ -179,6 +180,10 @@ UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored
{25'b0,wrIssueCap1,1'b0,wrIssueCap0}: {25'b0,wrIssueCap1,1'b0,wrIssueCap0}:
( (reg_rd && (reg_addr==AFI_WRQOS))? ( (reg_rd && (reg_addr==AFI_WRQOS))?
{28'b0,staticQos}:32'bz))); {28'b0,staticQos}:32'bz)));
assign reg_dvalid = (reg_rd && ((reg_addr==AFI_WRDATAFIFO_LEVEL) ||
(reg_addr==AFI_WRCHAN_CTRL) ||
(reg_addr==AFI_WRCHAN_ISSUINGCAP) ||
(reg_addr==AFI_WRQOS))) ? 1 : 0;
always @ (posedge aclk or posedge rst) begin always @ (posedge aclk or posedge rst) begin
if (rst) begin if (rst) begin
......
simulation_modules/simul_axi_master_wdata.v
View file @ 6a2bdfd7
...@@ -82,14 +82,13 @@ simul_axi_fifo ...@@ -82,14 +82,13 @@ simul_axi_fifo
.LATENCY(LATENCY), // minimal delay between inout and output ( 0 - next cycle) .LATENCY(LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(DEPTH) // maximal number of commands in FIFO .DEPTH(DEPTH) // maximal number of commands in FIFO
) simul_axi_fifo_i ( ) simul_axi_fifo_i (
.clk(clk), // input clk, .clk (clk), // input clk,
.reset(reset), // input reset, .reset (reset), // input reset,
.data_in({wid_in, wdata_in, wstrb_in, wlast_in}), // input [WIDTH-1:0] data_in, .data_in ({wid_in, wdata_in, wstrb_in, wlast_in}), // input [WIDTH-1:0] data_in,
.load(set_cmd), // input load, .load (set_cmd), // input load,
.input_ready(ready), // output input_ready, .input_ready (ready), // output input_ready,
.data_out({wid_out, wdata_out, wstrb_out, wlast_out}), // output [WIDTH-1:0] data_out, .data_out ({wid_out, wdata_out, wstrb_out, wlast_out}), // output [WIDTH-1:0] data_out,
.valid(wvalid_out), // output valid, .valid (wvalid_out), // output valid,
.ready(wready)); // input ready); .ready (wready)); // input ready);
endmodule endmodule
x393_testbench03.tf
View file @ 6a2bdfd7
...@@ -155,7 +155,7 @@ parameter NUM_INTERRUPTS = 9; ...@@ -155,7 +155,7 @@ parameter NUM_INTERRUPTS = 9;
parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 8; // 1; //8; parameter BLANK_ROWS_AFTER= 8; // 1; //8;
`endif `endif
parameter WOI_HEIGHT= 32; // parameter WOI_HEIGHT= 32;
parameter TRIG_LINES= 8; parameter TRIG_LINES= 8;
parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used
...@@ -2303,7 +2303,8 @@ simul_axi_hp_rd #( ...@@ -2303,7 +2303,8 @@ simul_axi_hp_rd #(
.reg_wr (PS_REG_WR), // input .reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input .reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0] .reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0] .reg_dout (PS_REG_DOUT), // output[31:0]
.reg_dvalid ()
); );
simul_axi_hp_wr #( simul_axi_hp_wr #(
...@@ -2349,7 +2350,8 @@ simul_axi_hp_wr #( ...@@ -2349,7 +2350,8 @@ simul_axi_hp_wr #(
.reg_wr (PS_REG_WR), // input .reg_wr (PS_REG_WR), // input
.reg_rd (PS_REG_RD), // input .reg_rd (PS_REG_RD), // input
.reg_din (PS_REG_DIN), // input[31:0] .reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT) // output[31:0] .reg_dout (PS_REG_DOUT), // output[31:0]
.reg_dvalid ()
); );
// afi1 - from compressor // afi1 - from compressor
simul_axi_hp_wr #( simul_axi_hp_wr #(
...@@ -2395,7 +2397,8 @@ simul_axi_hp_wr #( ...@@ -2395,7 +2397,8 @@ simul_axi_hp_wr #(
.reg_wr (PS_REG_WR1), // input .reg_wr (PS_REG_WR1), // input
.reg_rd (PS_REG_RD1), // input .reg_rd (PS_REG_RD1), // input
.reg_din (PS_REG_DIN), // input[31:0] .reg_din (PS_REG_DIN), // input[31:0]
.reg_dout (PS_REG_DOUT1) // output[31:0] .reg_dout (PS_REG_DOUT1), // output[31:0]
.reg_dvalid ()
); );
// SAXI_GP0 - histograms to system memory // SAXI_GP0 - histograms to system memory
......
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