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Commit 69b1d30b authored by Andrey Filippov's avatar Andrey Filippov
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Ready to start with the real serial sensor, all done so far can be used with parallel ones too

parents 0a729a6a 9c457ded
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.gitignore
View file @ 69b1d30b
......@@ -10,9 +10,11 @@ x393.prj
*DEBUG_VDT*
*.kate-swp
*.old
*.new
*.bad
*.pyc
*.pickle
py393/dbg
py393/dbg*
includes/x393_cur_params_sim.vh
includes/x393_cur_params_target_*.vh
......
.project
View file @ 69b1d30b
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,7 +107,7 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
......
.settings/com.elphel.vdt.VivadoRoute.prefs
View file @ 69b1d30b
VivadoRoute_122_SkipSnapshotRoute=true
VivadoRoute_123_SkipSnapshotRoute=true
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->
VivadoRoute_125_directive_route=MoreGlobalIterations
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 69b1d30b
......@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true
......
compressor_jp/bit_stuffer_27_32.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: bit_stuffer_27_32
* Date:2015-10-23
* Author: andrey
* Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_27_32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* bit_stuffer_27_32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module bit_stuffer_27_32#(
parameter DIN_LEN = 27
)(
input xclk, // pixel clock, sync to incoming data
input rst, // @xclk
input [DIN_LEN-1:0] din, // input data, MSB aligned
input [4:0] dlen, // input data width
input ds, // input data valid
input flush_in, // flush remaining data - should be after last ds. Also prepares for the next block
output [31:0] d_out, // outpt 32-bit data
output reg [1:0] bytes_out, // (0 means 4) valid with dv
output reg dv, // output data valid
output reg flush_out // delayed flush in matching the data latency
);
localparam DATA1_LEN = DIN_LEN + 32 - 8;
localparam DATA2_LEN = DIN_LEN + 32 - 2;
localparam DATA3_LEN = DIN_LEN + 32 - 1;
reg [DATA1_LEN-1:0] data1; // first stage of the barrel shifter
reg [DATA2_LEN-1:0] data2; // second stage of the barrel shifter
reg [DATA3_LEN-1:0] data3; // second stage of the barrel shifter/ output register
reg [5:0] early_length; // number of bits in the last word (mod 32)
reg [5:0] dlen1; // use for the stage 2, MSB - carry out
reg [5:0] dlen2; // use for the stege 3
reg [31:0] dmask2_rom; // data mask (sync with data2) - 1 use new data, 0 - use old data. Use small ROM?
reg [1:0] stage; // delayed ds or flush
reg [1:0] ds_stage;
reg [2:0] flush_stage;
wire [4:0] pre_bits_out_w = dlen2[4:0] + 5'h7;
assign d_out = data3[DATA3_LEN-1 -: 32];
always @ (posedge xclk) begin
if (rst) stage <= 0;
else stage <= {stage[0], ds | flush_in};
if (rst) ds_stage <= 0;
else ds_stage <= {ds_stage[0], ds};
if (rst) flush_stage <= 0;
else flush_stage <= {flush_stage[1:0], flush_in};
if (rst || flush_in) early_length <= 0;
else if (ds) early_length <= early_length[4:0] + dlen; // early_length[5] is not used in calculations, it is just carry out
if (rst) dlen1 <= 0;
else if (ds) dlen1 <= early_length; // previous value
if (rst) dlen2 <= 0;
else if (stage[0]) dlen2 <= dlen1; // previous value (position)
// barrel shifter stage 1 (0/8/16/24)
if (rst) data1 <= 'bx;
else if (ds) case (early_length[4:3])
2'h0: data1 <= { din, 24'b0};
2'h1: data1 <= { 8'b0,din, 16'b0};
2'h2: data1 <= {16'b0,din, 8'b0};
2'h3: data1 <= {24'b0,din };
endcase
// barrel shifter stage 2 (0/2/4/6)
if (rst) data2 <= 'bx;
else if (stage[0]) case (dlen1[2:1])
2'h0: data2 <= { data1, 6'b0};
2'h1: data2 <= { 2'b0,data1, 4'b0};
2'h2: data2 <= { 4'b0,data1, 2'b0};
2'h3: data2 <= { 6'b0,data1 };
endcase
if (rst) dmask2_rom <= 'bx;
else if (stage[0]) case (dlen1[4:0])
5'h00: dmask2_rom <= 32'hffffffff;
5'h01: dmask2_rom <= 32'h7fffffff;
5'h02: dmask2_rom <= 32'h3fffffff;
5'h03: dmask2_rom <= 32'h1fffffff;
5'h04: dmask2_rom <= 32'h0fffffff;
5'h05: dmask2_rom <= 32'h07ffffff;
5'h06: dmask2_rom <= 32'h03ffffff;
5'h07: dmask2_rom <= 32'h01ffffff;
5'h08: dmask2_rom <= 32'h00ffffff;
5'h09: dmask2_rom <= 32'h007fffff;
5'h0a: dmask2_rom <= 32'h003fffff;
5'h0b: dmask2_rom <= 32'h001fffff;
5'h0c: dmask2_rom <= 32'h000fffff;
5'h0d: dmask2_rom <= 32'h0007ffff;
5'h0e: dmask2_rom <= 32'h0003ffff;
5'h0f: dmask2_rom <= 32'h0001ffff;
5'h10: dmask2_rom <= 32'h0000ffff;
5'h11: dmask2_rom <= 32'h00007fff;
5'h12: dmask2_rom <= 32'h00003fff;
5'h13: dmask2_rom <= 32'h00001fff;
5'h14: dmask2_rom <= 32'h00000fff;
5'h15: dmask2_rom <= 32'h000007ff;
5'h16: dmask2_rom <= 32'h000003ff;
5'h17: dmask2_rom <= 32'h000001ff;
5'h18: dmask2_rom <= 32'h000000ff;
5'h19: dmask2_rom <= 32'h0000007f;
5'h1a: dmask2_rom <= 32'h0000003f;
5'h1b: dmask2_rom <= 32'h0000001f;
5'h1c: dmask2_rom <= 32'h0000000f;
5'h1d: dmask2_rom <= 32'h00000007;
5'h1e: dmask2_rom <= 32'h00000003;
5'h1f: dmask2_rom <= 32'h00000001;
endcase
// barrel shifter stage 3 (0/1), combined with output/hold register
if (rst) data3 <= 'bx;
else if (ds_stage[1]) begin
data3[DATA3_LEN-1 -: 32] <= (~dmask2_rom & (dlen2[5] ? {data3[DATA3_LEN-1-32 : 0],6'b0}: data3[DATA3_LEN-1 -: 32])) |
( dmask2_rom & (dlen2[0] ? {1'b0,data2[DATA2_LEN-1 -: 31]} : data2[DATA2_LEN-1 -: 32]));
data3[DATA3_LEN-1-32: 0] <= dlen2[0] ? data2[DATA2_LEN-31-1 : 0] : {data2[DATA2_LEN-32-1 : 0], 1'b0};
end
// dv <= (ds_stage[1] && dlen2[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
// dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
// dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
// no difference in number of cells
// if (rst ) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
// else if (ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
if (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
else if (flush_stage[1]) bytes_out <= pre_bits_out_w[4:3];
flush_out <= flush_stage[2];
end
endmodule
compressor_jp/bit_stuffer_escape.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: bit_stuffer_escape
* Date:2015-10-24
* Author: andrey
* Description: Escapes each 0xff with 0x00, 32-bit input and output
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_escape.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* bit_stuffer_escape.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module bit_stuffer_escape(
input xclk, // pixel clock, sync to incoming data
input rst, // @xclk
input [31:0] din, // input data, MSB aligned
input [1:0] bytes_in, // number of bytes, valid @ ds (0 means 4)
input in_stb, // input data/bytes_in strobe
input flush_in, // end of input data
output reg [31:0] d_out, // output 32-bit data
output reg [1:0] bytes_out, // valid @dv(only), 0 means 4 bytes
output reg dv, // output data valid
output reg flush_out // delayed flush in matching the data latency
);
wire [3:0] in_ff = {&din[31:24],&din[23:16],&din[15:8],&din[7:0]};
wire [3:0] fifo_nempty;
wire [3:0] fifo_ff;
wire [3:0] fifo_re;
wire [31:0] fifo_pre_out;
// mask output for flushing
wire [31:0] fifo_out = fifo_pre_out & {{8{fifo_nempty[3]}},{8{fifo_nempty[2]}},{8{fifo_nempty[1]}},{8{fifo_nempty[0]}}};
reg [3:0] flush_pend;
reg [3:0] bytes_in_mask_w;
always @* case (bytes_in)
2'h0 : bytes_in_mask_w <= 4'b1111;
2'h1 : bytes_in_mask_w <= 4'b1000;
2'h2 : bytes_in_mask_w <= 4'b1100;
2'h3 : bytes_in_mask_w <= 4'b1110;
endcase
generate
genvar i;
for (i = 0; i < 4; i = i+1) begin: byte_fifo_block
fifo_same_clock #(
.DATA_WIDTH(9),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (1'b0), // input
.clk (xclk), // input
.sync_rst (rst), // input
.we (in_stb && bytes_in_mask_w[i]), // input
.re (fifo_re[i]), // input
.data_in ({in_ff[i],din[8*i +: 8]}), // input[15:0]
.data_out ({fifo_ff[i],fifo_pre_out[8*i +: 8]}), // output[15:0]
.nempty (fifo_nempty[i]), // output
.half_full () // output reg
);
end
endgenerate
reg cry_ff; // 0xff was the last byte in the previous word
reg [1:0] fifo_byte_pntr; // byte pointer in fifo output, starting from MSB (0)
wire [3:0] fifo_ff_barrel_w = fifo_byte_pntr[1]?
(fifo_byte_pntr[0]?{fifo_ff[0],fifo_ff[3:1]}:{fifo_ff[1:0],fifo_ff[3:2]}):
(fifo_byte_pntr[0]?{fifo_ff[2:0],fifo_ff[3]}:fifo_ff[3:0]);
wire [3:0] fifo_nempty_barrel_w = fifo_byte_pntr[1]?
(fifo_byte_pntr[0]?{fifo_nempty[0],fifo_nempty[3:1]}:{fifo_nempty[1:0],fifo_nempty[3:2]}):
(fifo_byte_pntr[0]?{fifo_nempty[2:0],fifo_nempty[3]}:fifo_nempty[3:0]);
wire [31:0] fifo_out_barrel_w = fifo_byte_pntr[1]?
(fifo_byte_pntr[0]?{fifo_out[7:0], fifo_out[31: 8]}:{fifo_out[15:0],fifo_out[31:16]}):
(fifo_byte_pntr[0]?{fifo_out[23:0],fifo_out[31:24]}:fifo_out[31:0]);
// folowing registers are combinatorial signals
reg sel3_w; // select source for byte3 (MSB) from the barrel-shifted:0, it's own, 1 - zero (escape)
reg [1:0] sel2_w; // select source for byte2 from the barrel-shifted: 0, it's own, 1 - next higher byte, 3 - zero (escape)
reg [1:0] sel1_w; // select source for byte1 from the barrel-shifted: 0, it's own, 1 - next higher byte, 3 - zero (escape)
reg [1:0] sel0_w; // select source for byte0 (LSB) from the barrel-shifted: 0, it's own, 1 - next higher byte, 2 - two bytes higher,
// 3 - zero (escape)
reg cry_ff_w; // next value for cry_ff
reg [3:0] bytes_rdy_w; // data is available to generate an output word
wire rdy_w = &bytes_rdy_w;
reg [1:0] num_zeros_w; // number of escape zeros in the output word
reg [3:0] fifo_re_mask_w; // which fifo to read, bitmask (to be AND-ed with &bytes_rdy_w[3:0]}
always @* casex ({cry_ff,fifo_ff_barrel_w})
5'b0xxxx: sel3_w <= 0;
default: sel3_w <= 1;
endcase
always @* casex ({cry_ff,fifo_ff_barrel_w})
5'b00xxx: sel2_w <= 0;
5'b1xxxx: sel2_w <= 1;
default: sel2_w <= 3;
endcase
always @* casex ({cry_ff,fifo_ff_barrel_w})
5'b000xx: sel1_w <= 0;
5'b01xxx: sel1_w <= 1;
5'b10xxx: sel1_w <= 1;
default: sel1_w <= 3;
endcase
always @* casex ({cry_ff,fifo_ff_barrel_w})
5'b0000x: sel0_w <= 0;
5'b001xx: sel0_w <= 1;
5'b010xx: sel0_w <= 1;
5'b100xx: sel0_w <= 1;
5'b11xxx: sel0_w <= 2;
default: sel0_w <= 3;
endcase
always @* casex ({cry_ff,fifo_ff_barrel_w})
5'b00001: cry_ff_w <= 1;
5'b0011x: cry_ff_w <= 1;
5'b0101x: cry_ff_w <= 1;
5'b1001x: cry_ff_w <= 1;
5'b111xx: cry_ff_w <= 1;
default: cry_ff_w <= 0;
endcase
always @* case (sel3_w)
1'b0 : bytes_rdy_w[3] <= fifo_nempty_barrel_w[3];
1'b1 : bytes_rdy_w[3] <= 1;
endcase
always @* case (sel2_w)
2'b00 : bytes_rdy_w[2] <= fifo_nempty_barrel_w[2];
2'b01 : bytes_rdy_w[2] <= fifo_nempty_barrel_w[3];
2'b11 : bytes_rdy_w[2] <= 1;
default : bytes_rdy_w[2] <= 'bx;
endcase
always @* case (sel1_w)
2'b00 : bytes_rdy_w[1] <= fifo_nempty_barrel_w[1];
2'b01 : bytes_rdy_w[1] <= fifo_nempty_barrel_w[2];
2'b11 : bytes_rdy_w[1] <= 1;
default : bytes_rdy_w[1] <= 'bx;
endcase
always @* case (sel0_w)
2'b00 : bytes_rdy_w[0] <= fifo_nempty_barrel_w[0];
2'b01 : bytes_rdy_w[0] <= fifo_nempty_barrel_w[1];
2'b10 : bytes_rdy_w[0] <= fifo_nempty_barrel_w[2];
2'b11 : bytes_rdy_w[0] <= 1;
endcase
always @* casex ({cry_ff,fifo_ff_barrel_w})
5'b0001x: num_zeros_w <= 1;
5'b001xx: num_zeros_w <= 1;
5'b010xx: num_zeros_w <= 1;
5'b011xx: num_zeros_w <= 2;
5'b100xx: num_zeros_w <= 1;
5'b101xx: num_zeros_w <= 2;
5'b110xx: num_zeros_w <= 2;
default: num_zeros_w <= 0;
endcase
always @* casex ({num_zeros_w,fifo_byte_pntr})
4'b00xx: fifo_re_mask_w <= 4'b1111;
4'b0100: fifo_re_mask_w <= 4'b1110;
4'b0101: fifo_re_mask_w <= 4'b0111;
4'b0110: fifo_re_mask_w <= 4'b1011;
4'b0111: fifo_re_mask_w <= 4'b1101;
4'b1000: fifo_re_mask_w <= 4'b1100;
4'b1001: fifo_re_mask_w <= 4'b0110;
4'b1010: fifo_re_mask_w <= 4'b0011;
4'b1011: fifo_re_mask_w <= 4'b1001;
default: fifo_re_mask_w <= 'bx; // impossible num_zeros_w
endcase
// assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
assign fifo_re = fifo_nempty & (({4{rdy_w}} & fifo_re_mask_w) | {4{flush_pend[2]}});// when flushing read whatever is left
always @(posedge xclk) begin
if (rst || flush_pend[2]) cry_ff <= 0;
else if (rdy_w) cry_ff <= cry_ff_w;
if (rst || flush_pend[2]) fifo_byte_pntr <= 0; // flush reads all the remaining data from FIFO, byte pointer should be reset too
else if (rdy_w) fifo_byte_pntr <= fifo_byte_pntr - num_zeros_w;
dv <= rdy_w || (flush_pend[2] && (cry_ff || (|fifo_nempty)));
if (rdy_w || (flush_pend[2] && (cry_ff || (|fifo_nempty)))) begin
case (sel3_w)
1'b0 : d_out[31:24] <= fifo_out_barrel_w[31:24];
1'b1 : d_out[31:24] <= 8'b0;
endcase
case (sel2_w)
2'b00 : d_out[23:16] <= fifo_out_barrel_w[23:16];
2'b01 : d_out[23:16] <= fifo_out_barrel_w[31:24];
2'b11 : d_out[23:16] <= 8'b0;
default : d_out[23:16] <= 'bx;
endcase
case (sel1_w)
2'b00 : d_out[15: 8] <= fifo_out_barrel_w[15: 8];
2'b01 : d_out[15: 8] <= fifo_out_barrel_w[23:16];
2'b11 : d_out[15: 8] <= 8'b0;
default : d_out[15: 8] <= 'bx;
endcase
case (sel0_w)
2'b00 : d_out[ 7: 0] <= fifo_out_barrel_w[ 7: 0];
2'b01 : d_out[ 7: 0] <= fifo_out_barrel_w[15: 8];
2'b10 : d_out[ 7: 0] <= fifo_out_barrel_w[23:16];
2'b11 : d_out[ 7: 0] <= 8'b0;
default : d_out[ 7: 0] <= 'bx;
endcase
end
if (rst) flush_pend[0] <= 0;
else if (flush_in) flush_pend[0] <= 1;
else if (flush_pend[1]) flush_pend[0] <= 0;
if (rst) flush_pend[1] <= 0;
else flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;
if (rst) flush_pend[3:2] <= 0;
else flush_pend[3:2] <= {flush_pend[2:1]};
if (rst) flush_out <= 0;
else flush_out <= flush_pend[3];
if (rst) bytes_out <= 'bx;
else if ( rdy_w || flush_pend[2]) casex(bytes_rdy_w[3:0])
4'b10xx : bytes_out <= 1;
4'b110x : bytes_out <= 2;
4'b1110 : bytes_out <= 3;
default : bytes_out <= 0; // all 4 bytes
endcase
end
endmodule
compressor_jp/bit_stuffer_metadata.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: bit_stuffer_metadata
* Date:2015-10-25
* Author: andrey
* Description:
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_metadata.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* bit_stuffer_metadata.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module bit_stuffer_metadata(
input mclk,
input mrst, // @posedge mclk, sync reset
input xclk,
input xrst, // @posedge xclk, sync reset
input last_block, // use it to copy timestamp from fifo
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
input [31:0] din, // input data, MSB aligned
input [1:0] bytes_in, // number of bytes, valid @ ds (0 means 4)
input in_stb, // input data/bytes_in strobe
input flush, // end of input data
input abort, // @ any, extracts 0->1 and flushes
// outputs @ negedge clk
output reg [31:0] data_out, // [31:0] output data
output reg data_out_valid,// output data valid
output reg done, // reset by !en, goes high after some delay after flushing
output reg running // from registering timestamp until done
`ifdef DEBUG_RING
, output reg [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
reg [7:0] time_ram0[0:3]; // 0 - seconds, 1 - microseconds MSB in the output 32-bit word, byt LSB of the sec/usec
reg [7:0] time_ram1[0:3];
reg [7:0] time_ram2[0:3];
reg [7:0] time_ram3[0:3];
reg [3:0] ts_in=8;
reg last_block_d; // last_block delayed by one clock
reg color_first_r;
reg [2:0] abort_r;
reg force_flush;
// reg color_first_r; // registered with the same clock as color_first to extract leading edge
// stb_time[2] - single-cycle pulse after color_first goes low
// reg [19:0] imgsz32; // current image size in multiples of 32-bytes
reg [21:0] imgsz4; // current image size in multiples of 4-bytes
reg last_stb_4; // last stb_in was 4 bytes
reg trailer;
reg meta_out;
reg [1:0] meta_word;
reg zeros_out; // output of 32 bytes (8 words) of zeros
wire trailer_done = (imgsz4[2:0] == 7) && zeros_out;
wire meta_last = (imgsz4[2:0] == 7) && meta_out;
// re-clock enable to this clock
wire ts_rstb= last_block && !last_block_d; // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire [7:0] ts_dout; // timestamp data, byte at a time
wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4);
wire stb_start = !color_first && color_first_r;
wire stb = in_stb & !trailer && !force_flush;
always @ (posedge xclk) begin
if (xrst ||trailer_done) imgsz4 <= 0;
else if (stb || trailer) imgsz4 <= imgsz4 + 1;
if (stb) last_stb_4 <= (bytes_in == 0);
last_block_d <= last_block;
color_first_r <= color_first;
if (xrst) ts_in <= 8;
else if (ts_rstb) ts_in <= 0;
else if (!ts_in[3]) ts_in <= ts_in + 1;
if ((!ts_in[3] && (ts_in[1:0] == 0)) || write_size) time_ram0[ts_in[3:2]] <= ts_in[3]? ({imgsz4[5:0],flush?2'b0:bytes_in}):ts_dout; //ts_in[3:2] == 2'b10 when write_size
if ((!ts_in[3] && (ts_in[1:0] == 1)) || write_size) time_ram1[ts_in[3:2]] <= ts_in[3]? (imgsz4[13:6]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 2)) || write_size) time_ram2[ts_in[3:2]] <= ts_in[3]? (imgsz4[21:14]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 3)) || write_size) time_ram3[ts_in[3:2]] <= ts_in[3]? (8'hff):ts_dout;
if (xrst) trailer <= 0;
else if (flush || force_flush) trailer <= 1;
else if (trailer_done) trailer <= 0;
if (xrst) meta_out <= 0;
else if (trailer && (imgsz4[2:0] == 4) &&!zeros_out) meta_out <= 1;
else if (meta_last) meta_out <= 0;
if (!meta_out) meta_word <= 0;
else meta_word <= meta_word + 1;
if (xrst) zeros_out <= 0;
else if (meta_last) zeros_out <= 1;
else if (trailer_done) zeros_out <= 0;
data_out <= ({32{stb}} & din) | ({32{meta_out}} & {time_ram0[meta_word],time_ram1[meta_word],time_ram2[meta_word],time_ram3[meta_word]});
data_out_valid <= stb || trailer;
if (xrst || trailer) running <= 0;
else if (stb_start) running <= 1;
done <= trailer_done;
// re-clock abort, extract leading edge
abort_r <= {abort_r[0] & ~abort_r[1], abort_r[0], abort & ~trailer};
if (xrst || trailer) force_flush <= 0;
else if (abort_r) force_flush <= 1;
end
// just for testing
`ifdef DEBUG_RING
assign dbg_ = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
dbg_etrax_dma <= imgsz4[3:0];
end
`endif
//color_first && color_first_r
timestamp_fifo timestamp_fifo_i (
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_pre_stb), // input
.din (ts_data), // input[7:0]
.aclk (xclk), //fradv_clk), // input
.arst (xrst), //fradv_clk), // input
.advance (stb_start), // triggers at the 0->1
.rclk (xclk), // input
.rrst (xrst), //fradv_clk), // input
.rstb (ts_rstb), // input
.dout (ts_dout) // output[7:0] reg
);
endmodule
compressor_jp/cmprs_out_fifo32.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: cmprs_out_fifo32
* Date:2015-06-25
* Author: Andrey Filippov
* Description: Compressor output FIFO, modified to use 32-bit input and xclk
*
* Copyright (c) 2015 Elphel, Inc.
* cmprs_out_fifo32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_out_fifo32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmprs_out_fifo32(
// input rst, // mostly for simulation
// wclk domain
input wclk, // source clock (1x pixel clock)
input wrst, // @posedge wclk, sync reset
input we,
input [31:0] wdata,
input wa_rst, // reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
input wlast, // written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
output eof_written_wclk, // eof_written - reclocked to wclk
// rclk domain
input rclk,
input rrst, // @posedge rclk, sync reset
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
reg regen;
reg [ 8:0] raddr;
reg [ 7:0] count32;
reg [ 7:0] lcount32; // counting chunks left in the same frame
reg [ 9:0] waddr;
wire written32b; // written 32 bytes, re-clocked to read clock domain (single-cycle)
wire wlast_rclk;
reg flush_fifo_r;
assign flush_fifo = flush_fifo_r;
assign fifo_count = count32;
assign eof = wlast_rclk;
always @ (posedge wclk) begin
if (wrst) waddr <= 0;
else if (wa_rst) waddr <= waddr & 10'h3f8; // reset 3 LSBs only
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk) begin
regen <= ren;
if (rst_fifo) raddr <= {waddr[9:3],2'b0};
else if (ren) raddr <= raddr + 1;
if (rst_fifo) count32 <= 0;
else if ( written32b && !(ren && (&raddr[1:0]))) count32 <= count32 + 1;
else if (!written32b && (ren && (&raddr[1:0]))) count32 <= count32 - 1;
if (rst_fifo) lcount32 <= 0;
else if (wlast_rclk) lcount32 <= count32;
else if ((lcount32 !=0) && ren && (&raddr[1:0])) lcount32 <= lcount32 - 1;
if (rst_fifo) flush_fifo_r <= 0;
else if (wlast_rclk) flush_fifo_r <= 1;
else if ((count32[7:1] == 0) && ( !count32[0] || ren)) flush_fifo_r <= 0;
end
// wclk -> rclk
pulse_cross_clock written32b_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[2:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(6)
) fifo_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
.ren (ren), // input
.regen (regen), // input
.data_out (rdata), // output[63:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr (waddr), // input[10:0]
.we (we), // input
.web (8'hff), // input[7:0]
.data_in (wdata) // input[15:0]
);
endmodule
compressor_jp/compressor393.v
View file @ 69b1d30b
......@@ -119,9 +119,10 @@ module compressor393 # (
`endif
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge hclk, sync reset
......@@ -388,7 +389,9 @@ module compressor393 # (
) jp_channel_i (
// .rst (rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
......
compressor_jp/csconvert18a.v
View file @ 69b1d30b
......@@ -249,7 +249,7 @@ module csconvert18a(
wire ystrt,nxtline;
reg [7:0] yaddr_r; // address for the external buffer memory to write 16x16x8bit Y data
reg ywe_r; // wrire enable of Y data
reg ywe_r; // write enable of Y data
reg [6:0] caddr_r; // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
reg cwe_r; // write enable for CbCr data
reg odd_pix; // odd pixel (assumes even number of pixels in a line
......@@ -267,10 +267,10 @@ module csconvert18a(
assign n000 = n000_r;
assign n255 = n255_r;
assign signed_y = signed_y_r; // - now signed char, -128(black) to +127 (white)
assign yaddr = yaddr_r;
assign ywe = ywe_r;
assign caddr = caddr_r;
assign cwe = cwe_r;
assign yaddr = yaddr_r2;
assign ywe = ywe_r2;
assign caddr = caddr_r2;
assign cwe = cwe_r2;
dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]), .dout(strt_dly[1]));
......@@ -532,20 +532,29 @@ Y[1,1]=(0x96*P[1,1]+ 0x1d*((P[1,0]+P[1,2])/2 + 0x4d*((P[0,1] +
reg [7:0] y;
// reg [7:0] y0; // bypass in monochrome mode
wire [7:0] y0 = pdc;
// wire [7:0] y0 = pdc;
reg [7:0] y0_r;
// wire [7:0] y0; // bypass in monochrome mode
reg [15:0] y1,y2,y3;
wire [15:0] y_sum =y1+y2+y3;
// TODO: insert register to ease mm1..3 -> y (OK to delay all outputs).
// TODO: reduce width of y1,y2,y3 and correctly round
// wire [15:0] y_sum =y1+y2+y3;
reg [15:0] y_sum_r;
// always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent
always @ (posedge CLK) y1 <= mm1;
always @ (posedge CLK) y2 <= mm2;
always @ (posedge CLK) y3 <= mm3;
// wire [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
wire [7:0] pre_y= mono ? y0_r : (y_sum_r[15:8]+y_sum_r[7]);
// making y output signed -128..+127
wire [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
always @ (posedge CLK) y[7:0] <= pre_y[7:0];
always @ (posedge CLK) signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
always @ (posedge CLK) begin
y1 <= mm1;
y2 <= mm2;
y3 <= mm3;
y0_r <= pdc;
y_sum_r <= y1+y2+y3;
y[7:0] <= pre_y[7:0];
signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
end
// Try easier and hope better algorithm of color extractions that should perform better on gradients.
......@@ -575,18 +584,30 @@ reg sub_y; // output accumulator/subtractor. 0 - load new data,
wire cwe0; // preliminary cwe_r (to be modulated by odd/even pixels)
reg cstrt; //ystrt dealyed by 1
reg cnxt; // nxtline delayed by 1
reg pre_sel_cbcrmult1;
// delaying, for now uing "old" ywe,cwe, yaddr,caddr - registering them on the output
always @ (posedge CLK) begin
if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
else sel_cbcrmult1 <= ~sel_cbcrmult1;
// if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
// else sel_cbcrmult1 <= ~sel_cbcrmult1;
if (~(ywe_r || ystrt || nxtline)) pre_sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
else pre_sel_cbcrmult1 <= ~pre_sel_cbcrmult1;
sel_cbcrmult1 <=pre_sel_cbcrmult1;
sub_y <= ~sel_cbcrmult1;
cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
// cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
cbcrmult1 <= sel_cbcrmult1?y[7:0]:y0_r[7:0]; // delayed by 1 clock
if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);
end
assign cbcrmult2=use_cr?m_cr:m_cb; // maybe will need a register? (use_cr will still be good as it is valid early)
assign cbcrmulto=cbcrmult1*cbcrmult2;
assign cbcrmult2 = use_cr?m_cr:m_cb; // maybe will need a register? (use_cr will still be good as it is valid early)
//assign cbcrmulto = cbcrmult1*cbcrmult2;
assign cbcrmulto = cbcrmult1*cbcrmult2_r;
reg [9:0] cbcrmult2_r; // will be one cycle later than cbcrmult2, but is still OK. Will be absorbed into the DSP block
// will preserve extra bit, but do not need to add half of the truncated MSB - on average there will be no shift after subtraction
always @ (posedge CLK) begin
cbcrmult2_r <= cbcrmult2;
cbcrmultr[10:0] <= cbcrmulto[17:7];
cbcr[10:0] <= sub_y? (cbcr[10:0]-cbcrmultr[10:0]+ 1'b1):cbcrmultr[10:0];
end
......@@ -598,23 +619,38 @@ end
dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
//SRL16 i_cwe0 (.D(ywe_r ), .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
always @ (posedge CLK) begin
always @ (posedge CLK) begin
cstrt <= ystrt;
cnxt <= nxtline;
cwe_r <= cwe0 && sub_y;
// cwe_r <= cwe0 && sub_y;
cwe_r <= cwe0 && !sel_cbcrmult1;
caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
if (cstrt) caddr_r[6] <= ~bayer_phase[1];
else if (cnxt) caddr_r[6] <= ~caddr_r[6];
if (cstrt) caddr_r[5:3] <=3'b0;
else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
end
end
// extra signals delayed by 1 clock
reg ywe_r2, cwe_r2;
reg [6:0] caddr_r2;
reg [7:0] yaddr_r2;
always @ (posedge CLK) begin
ywe_r2 <= ywe_r;
cwe_r2 <= cwe_r;
yaddr_r2 <= yaddr_r;
caddr_r2 <= caddr_r;
end
always @ (posedge CLK) begin
y_eq_0 <= (y0[7:0] == 8'h0);
y_eq_255 <= (y0[7:0] == 8'hff);
y_eq_0 <= (y0_r[7:0] == 8'h0);
y_eq_255 <= (y0_r[7:0] == 8'hff);
if (strt) n000_r[7:0] <= 8'h0;
else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r) n000_r[7:0] <= n000_r[7:0]+1;
else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r2) n000_r[7:0] <= n000_r[7:0]+1;
if (strt) n255_r[7:0] <= 8'h0;
else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r) n255_r[7:0] <= n255_r[7:0]+1;
else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r2) n255_r[7:0] <= n255_r[7:0]+1;
end
......
compressor_jp/focus_sharp393.v
View file @ 69b1d30b
......@@ -27,7 +27,8 @@
*/
`include "system_defines.vh"
`timescale 1ns/1ps
//TODO: Modify to work with other modes (now only on color)
// TODO: Modify to work with other modes (now only on color)
// NOTE: when removing clk2x, temporarily use clk here, just keep mode ==0 (disabled)
module focus_sharp393(
input clk, // pixel clock, posedge
input clk2x, // 2x pixel clock
......
compressor_jp/huffman393.v
View file @ 69b1d30b
......@@ -2,9 +2,9 @@
** -----------------------------------------------------------------------------**
** huffman333.v
**
** Huffman encoder for JPEG compressorrdy
** Huffman encoder for JPEG compressor
**
** Copyright (C) 2002-20015 Elphelk, Inc
** Copyright (C) 2002-20015 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** huffman393 is free software - hardware description language (HDL) code.
......
compressor_jp/huffman_merge_code_literal.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: huffman_merge_code_literal
* Date:2015-10-22
* Author: andrey
* Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data,
* align result to MSB : {huffman,literal, {n{1'b0}}
*
* Copyright (c) 2015 Elphel, Inc .
* huffman_merge_code_literal.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_merge_code_literal.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module huffman_merge_code_literal(
input clk,
input in_valid,
input [15:0] huff_code,
input [ 3:0] huff_code_len, // 0 means 16
input [10:0] literal,
input [ 3:0] literal_len,
output reg out_valid, // latency 5 from input
output reg [26:0] out_bits, // latency 5 from input
output reg [ 4:0] out_len // latency 5 from input
);
reg [10:0] lit0;
reg [10:0] lit1;
reg [10:0] lit2;
reg [15:0] huff0; // SR-s will be extracted?
reg [15:0] huff1;
reg [15:0] huff2;
reg [26:0] data3;
reg [3:0] llen0;
reg [3:0] llen1;
reg [3:0] llen2;
reg [4:0] olen3;
reg [3:0] hlen0;
reg [3:0] hlen1;
reg [4:0] hlen2;
reg [3:0] hlen2m1;
reg [1:0] hlen3m1;
reg [3:0] valid;
always @ (posedge clk) begin
// input layer 0
lit0 <= literal;
llen0 <= literal_len;
huff0 <= huff_code;
hlen0 <= huff_code_len;
valid[0] <= in_valid;
// layer 1
casex (llen0[3:2])
2'b1x: lit1 <= lit0;
2'b01: lit1 <= {lit0[6:0],4'b0};
2'b00: lit1 <= {lit0[2:0],8'b0};
endcase
llen1 <= llen0;
huff1 <= huff0;
hlen1 <= hlen0;
valid[1] <= valid[0];
// layer 2
case (llen1[1:0])
2'b11: lit2 <= lit1;
2'b10: lit2 <= {lit1[9:0], 1'b0};
2'b01: lit2 <= {lit1[8:0], 2'b0};
2'b00: lit2 <= {lit1[7:0], 3'b0};
endcase
llen2 <= llen1;
huff2 <= huff1;
hlen2 <= {~(|hlen1),hlen1};
hlen2m1 <= hlen1 - 1; // s0
valid[2] <= valid[1];
// layer 3
olen3 <= hlen2 + llen2;
case (hlen2m1[3:2])
2'b11: data3 <= {huff2[15:0],lit2[10:0]};
2'b10: data3 <= {huff2[11:0],lit2[10:0], 4'b0};
2'b01: data3 <= {huff2[ 7:0],lit2[10:0], 8'b0};
2'b00: data3 <= {huff2[ 3:0],lit2[10:0],12'b0};
endcase
hlen3m1 <= hlen2m1[1:0];
valid[3] <= valid[2];
//layer4
out_len <= olen3;
case (hlen3m1[1:0])
2'b11: out_bits <= data3;
2'b10: out_bits <= {data3[25:0], 1'b0};
2'b01: out_bits <= {data3[24:0], 2'b0};
2'b00: out_bits <= {data3[23:0], 3'b0};
endcase
out_valid <= valid[3];
end
endmodule
compressor_jp/huffman_snglclk.v 0 → 100644
View file @ 69b1d30b
/*
** -----------------------------------------------------------------------------**
** huffman_snglclk.v
**
** Huffman encoder for JPEG compressor
**
** Copyright (C) 2002-20015 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** huffman_snglclk is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
`include "system_defines.vh"
module huffman_snglclk (
input xclk, // pixel clock, sync to incoming data
input rst, // @xclk
// Interface to program Huffman tables
input mclk, // system clock to write tables
input tser_we, // enable write to a table
input tser_a_not_d, // address/not data distributed to submodules
input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
// Input data
input [15:0] di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
input ds, // di valid strobe (sync to xclk)
// Output data
output [26:0] do27, // [26:0] output data, MSB aligned
output [ 4:0] dl, // [4:0] data length
output dv, // output data valid
output flush, // last block done - flush the rest bits
output last_block,
output reg test_lbw,
output gotLastBlock, // last block done - flush the rest bits
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk, // 1-cycle flush output @ clk_flush
output fifo_or_full // FIFO output register full - just for debuging
);
// A small input FIFO, only needed for RLL >16 that require several clock cycles to output
reg fifo_re_r;
wire fifo_rdy;
wire fifo_re = fifo_re_r && fifo_rdy;
wire [15:0] fifo_out;
fifo_same_clock #(
.DATA_WIDTH(16),
.DATA_DEPTH(4)
) fifo_same_clock_i (
.rst (1'b0), // input
.clk (xclk), // input
.sync_rst (rst), // input
.we (ds), // input
.re (fifo_re), // input
.data_in (di), // input[15:0]
.data_out (fifo_out), // output[15:0]
.nempty (fifo_rdy), // output
.half_full () // output reg
);
assign fifo_or_full = fifo_rdy;
wire gotDC= fifo_out[15] && fifo_out[14];
wire gotAC= fifo_out[15] && !fifo_out[14];
wire gotRLL= !fifo_out[15] && !fifo_out[12];
wire gotEOB= !fifo_out[15] && fifo_out[12];
assign gotLastBlock= fifo_out[15] && fifo_out[14] && fifo_out[12] && fifo_re;
wire gotLastWord= !fifo_out[14] && fifo_out[12] && fifo_re; // (AC or RLL) and last bit set
wire gotColor= fifo_out[13];
reg [5:0] rll; // 2 MSBs - counter to send "f0" codes
// reg [3:0] rll1; // valid at cycle "1"
wire [3:0] rll_late; // match AC's length timing
reg [2:0] gotAC_r;
reg [2:0] gotDC_r;
reg [2:0] gotEOB_r;
reg [2:0] gotColor_r;
reg [2:1] gotF0_r;
reg [11:0] sval; // signed input value
wire [3:0] val_length;
wire [10:0] val_literal;
reg [8:0] htable_addr; // address to huffman table
reg [2:0] htable_re; // Huffman table memory re, regen, out valid
wire [31:0] htable_out; // Only [19:0] are used
wire [3:0] val_length_late; // delay by 3 clocks to match Huffman table output
wire [10:0] val_literal_late;// delay by 3 clocks to match Huffman table output
reg ready_to_flush;
reg flush_r; // last block done - flush the rest bits
reg last_block_r;
reg [9:0] active_r;
wire active = fifo_re || active_r[0];
assign flush = flush_r;
assign last_block = last_block_r;
assign fifo_or_full = fifo_rdy;
always @(posedge xclk) begin
if (rst) fifo_re_r <= 0;
else fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL && (|fifo_out[5:4])) && !(|rll[5:4]);
if (rst) gotAC_r <= 0;
else gotAC_r <= {gotAC_r[1:0], gotAC && fifo_re};
if (rst) gotDC_r <= 0;
else gotDC_r <= {gotDC_r[1:0], gotDC && fifo_re};
if (rst) gotEOB_r <= 0;
else gotEOB_r <= {gotEOB_r[1:0], gotEOB && fifo_re};
if (rst) gotColor_r <= 0;
else gotColor_r <= {gotColor_r[1:0], (gotDC && fifo_re) ? gotColor : gotColor_r[0] };
if (rst) rll[5:4] <= 0;
else if (fifo_re && gotRLL) rll[5:4] <= fifo_out[5:4];
else if (gotAC_r[0]) rll[5:4] <= 0; // combine with !en?
else if (|rll[5:4]) rll[5:4] <=rll[5:4] - 1;
if (rst) rll[3:0] <= 0;
else if (fifo_re) rll[3:0] <= gotRLL ? fifo_out[3:0] : 4'b0;
// rll1 <= rll[3:0];
// rll_late <= rll1;
if (rst) gotF0_r[2:1] <= 0;
else gotF0_r[2:1] <= {gotF0_r[1], (|rll[5:4])};
// if (fifo_re) sval[11:0] <= fifo_out[11:0];
sval[11:0] <= fifo_out[11:0];
htable_addr[8] <= gotColor_r[2]; // switch Huffman tables
htable_addr[7:0] <= ({8{gotEOB_r[2]}} & 8'h0 ) | // generate 00 code (end of block)
({8{gotF0_r[2]}} & 8'hf0 ) | // generate f0 code (16 zeros)
({8{gotDC_r[2]}} & {val_length[3:0], 4'hf}) |
({8{gotAC_r[2]}} & {rll_late[3:0], val_length[3:0]});
if (rst) htable_re <= 0;
else htable_re <= {htable_re[1:0], gotEOB_r[2] | gotF0_r[2] | gotDC_r[2] | gotAC_r[2]};
// other signals
if (rst || flush_r) last_block_r <= 0;
else if (gotLastBlock) last_block_r <= 1;
if (rst || flush_r) ready_to_flush <= 0;
else if (last_block_r && gotLastWord) ready_to_flush <= 1;
test_lbw <= last_block && gotLastWord;
if (rst) active_r <= 0;
else if (fifo_re) active_r <= 10'h3ff;
else active_r <= active_r >> 1;
if (rst) flush_r <= 0;
else flush_r <= ready_to_flush && !active && !flush_r;
end
varlen_encode_snglclk varlen_encode_snglclk_i (
.clk (xclk), // input
.d (sval), // input[11:0]
.l (val_length), // output[3:0] reg
.q (val_literal) // output[10:0] reg
);
wire twe;
wire [15:0] tdi;
wire [22:0] ta;
table_ad_receive #(
.MODE_16_BITS (1),
.NUM_CHN (1)
) table_ad_receive_i (
.clk (mclk), // input
.a_not_d (tser_a_not_d), // input
.ser_d (tser_d), // input[7:0]
.dv (tser_we), // input
.ta (ta), // output[22:0]
.td (tdi), // output[15:0]
.twe (twe) // output
);
ram18_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(4),
.LOG2WIDTH_RD(5),
.DUMMY(0)
`ifdef PRELOAD_BRAMS
`include "includes/huffman.dat.vh"
`endif
) i_htab (
.rclk (xclk), // input
.raddr (htable_addr[8:0]), // input[8:0]
.ren (htable_re[0]), // input
.regen (htable_re[1]), // input
.data_out (htable_out), // output[31:0]
.wclk (mclk), // input
.waddr (ta[9:0]), // input[9:0]
.we (twe), // input
.web (4'hf), // input[3:0]
.data_in (tdi[15:0]) // input[15:0]
);
dly_16 #(
.WIDTH(11)
) dly_16_val_literal_i (
.clk (xclk), // input
.rst (rst), // input
.dly (4'h2), // input[3:0]
.din (val_literal), // input[0:0]
.dout (val_literal_late) // output[0:0]
);
dly_16 #(
.WIDTH(4)
) dly_16_val_length_i (
.clk (xclk), // input
.rst (rst), // input
.dly (4'h2), // input[3:0]
.din ((gotEOB_r[2] | gotF0_r[2]) ? 4'b0 : val_length), // input[0:0]
.dout (val_length_late) // output[0:0]
);
dly_16 #(
.WIDTH(4)
) dly_16_rll_late_i (
.clk (xclk), // input
.rst (rst), // input
.dly (4'h2), // input[3:0]
.din (rll[3:0]), // input[0:0]
.dout (rll_late) // output[0:0]
);
huffman_merge_code_literal huffman_merge_code_literal_i (
.clk (xclk), // input
.in_valid (htable_re[2]), // input
.huff_code (htable_out[15:0]), // input[15:0]
.huff_code_len (htable_out[19:16]), // input[3:0]
.literal (val_literal_late), // input[10:0]
.literal_len (val_length_late), // input[3:0]
.out_valid (dv), // output reg
.out_bits (do27), // output[26:0] reg
.out_len (dl) // output[4:0] reg
);
pulse_cross_clock flush_clk_i (
.rst (rst),
.src_clk (xclk),
.dst_clk (clk_flush),
.in_pulse (flush),
.out_pulse (flush_clk),
.busy ());
endmodule
compressor_jp/huffman_stuffer_meta.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: huffman_stuffer_meta
* Date:2015-10-26
* Author: andrey
* Description: Huffman encoder, bit stuffer, inser meta-data
* "New" part of the JPEG/JP4 comressor that used double frequency clock
*
* Copyright (c) 2015 Elphel, Inc .
* huffman_stuffer_meta.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_stuffer_meta.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module huffman_stuffer_meta(
input mclk, // system clock to write tables
input mrst,
input xclk, // pixel clock, sync to incoming data
input en_huffman, // @xclk
input en_stuffer, // @xclk
input abort_stuffer, // @ any
// Interface to program Huffman tables
input tser_we, // enable write to a table
input tser_a_not_d, // address/not data distributed to submodules
input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
// Input data
input [15:0] di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
input ds, // di valid strobe (sync to xclk)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
output [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
wire [26:0] huffman_do27;
wire [4:0] huffman_dl;
wire huffman_dv;
wire huffman_flush;
wire huffman_last_block;
wire [31:0] stuffer_do32;
wire [1:0] stuffer_bytes;
wire stuffer_dv;
wire stuffer_flush_out;
wire [31:0] escape_do32;
wire [1:0] escape_bytes;
wire escape_dv;
wire escape_flush_out;
huffman_snglclk huffman_snglclk_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.mclk (mclk), // input
.tser_we (tser_we), // input
.tser_a_not_d (tser_a_not_d), // input
.tser_d (tser_d), // input[7:0]
.di (di), // input[15:0]
.ds (ds), // input
.do27 (huffman_do27), // output[26:0]
.dl (huffman_dl), // output[4:0]
.dv (huffman_dv), // output
.flush (huffman_flush), // output
.last_block (huffman_last_block), // output
`ifdef DEBUG_RING
.test_lbw (test_lbw),
.gotLastBlock (gotLastBlock), // last block done - flush the rest bits
`else
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
bit_stuffer_27_32 #(
.DIN_LEN(27)
) bit_stuffer_27_32_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (huffman_do27), // input[26:0]
.dlen (huffman_dl), // input[4:0]
.ds (huffman_dv), // input
.flush_in (huffman_flush), // input
.d_out (stuffer_do32), // output[31:0]
.bytes_out (stuffer_bytes), // output[1:0] reg
.dv (stuffer_dv), // output reg
.flush_out (stuffer_flush_out) // output reg
);
bit_stuffer_escape bit_stuffer_escape_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (stuffer_do32), // input[31:0]
.bytes_in (stuffer_bytes), // input[1:0]
.in_stb (stuffer_dv), // input
.flush_in (stuffer_flush_out), // input
.d_out (escape_do32), // output[31:0] reg
.bytes_out (escape_bytes), // output[1:0] reg
.dv (escape_dv), // output reg
.flush_out (escape_flush_out) // output reg
);
bit_stuffer_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
.xrst (~en_stuffer), // input
.last_block (huffman_last_block), // input
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input
.din (escape_do32), // input[31:0]
.bytes_in (escape_bytes), // input[1:0]
.in_stb (escape_dv), // input
.flush (escape_flush_out), // input
.abort (abort_stuffer), // input
.data_out (data_out), // output[31:0] reg
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
);
endmodule
compressor_jp/jp_channel.v
View file @ 69b1d30b
......@@ -105,7 +105,9 @@ module jp_channel#(
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge xclk, sync reset
......@@ -306,12 +308,15 @@ module jp_channel#(
/// wire test_lbw;
wire stuffer_rdy; // receiver (bit stuffer) is ready to accept data;
`ifdef USE_XCLK2X
wire [15:0] huff_do; // output[15:0] reg
wire [3:0] huff_dl; // output[3:0] reg
wire huff_dv; // output reg
wire flush; // output reg @ negedge xclk2x
wire last_block; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy; // receiver (bit stuffer) is ready to accept data;
`endif
wire [31:0] cmd_data; // 32-bit data to write to tables and registers(LSB first) - from cmd_deser
......@@ -344,10 +349,24 @@ module jp_channel#(
assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE);
assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);
// assign buf_ren = buf_rd[0];
// assign buf_regen = buf_rd[1];
`ifdef USE_XCLK2X
// re-sync to posedge xclk2x
reg xrst2xn;
always @ (negedge xclk2x) xrst2xn <= xrst;
`endif
`ifdef DEBUG_RING
`ifndef USE_XCLK2X
// wire [15:0] huff_do; // output[15:0] reg
// wire [3:0] huff_dl; // output[3:0] reg
// wire huff_dv; // output reg
// wire flush; // output reg @ negedge xclk2x
wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
`endif
reg [31:0] debug_fifo_in;
reg [31:0] debug_fifo_out;
reg [15:0] pre_start_cntr;
......@@ -388,7 +407,11 @@ module jp_channel#(
wire [2:0] dbg_block_mem_wa_save;
timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
`else
.clk (xclk), // input
`endif
.pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg
......@@ -398,7 +421,11 @@ module jp_channel#(
// cmprs_standalone - use to reset flush
`ifdef USE_XCLK2X
always @ (posedge ~xclk2x) begin
`else
always @ (posedge xclk) begin
`endif
dbg_reset_fifo <= fifo_rst;
if (xrst2xn || dbg_reset_fifo) debug_fifo_in <= 0;
else if (stuffer_dv) debug_fifo_in <= debug_fifo_in + 1;
......@@ -880,7 +907,7 @@ module jp_channel#(
end
`ifdef USE_OLD_XDCT393
xdct393 xdct393_i (
.clk (xclk), // input
......@@ -893,6 +920,20 @@ module jp_channel#(
.dv (), // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.d_out (dct_out) // output[12:0]
);
`else
xdct393r xdct393_i (
.clk (xclk), // input
.en (frame_en), // input if zero will reset transpose memory page numbers
.start (dct_start), // input single-cycle start pulse that goes with the first pixel data. Other 63 should follow
.xin (yc_nodc), // input[9:0]
.last_in (dct_last_in), // output reg output high during input of the last of 64 pixels in a 8x8 block //
.pre_first_out (dct_pre_first_out), // outpu 1 cycle ahead of the first output in a 64 block
/// .dv (dct_dv), // output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.dv (), // not used: output data output valid. Will go high on the 94-th cycle after the start (now - on 95-th?)
.d_out (dct_out) // output[12:0]
);
`endif
wire quant_start;
dly_16 #(.WIDTH(1)) i_quant_start (.clk(xclk),.rst(1'b0), .dly(4'd0), .din(dct_pre_first_out), .dout(quant_start)); // dly=0+1
......@@ -968,7 +1009,11 @@ module jp_channel#(
// TODO: Verify focus_sharp393: quantizer output (with strobes) is now 2 cycles later than in 353 (relative to xdct out). Seems to be OK.
focus_sharp393 focus_sharp393_i (
.clk (xclk), // input - pixel clock
`ifdef USE_XCLK2X
.clk2x (xclk2x), // input 2x pixel clock
`else
.clk2x (xclk), // FIXME: fix the module not to use xclk2x
`endif
.en (frame_en), // input
.mclk (mclk), // input system clock to write tables
......@@ -991,21 +1036,28 @@ module jp_channel#(
.hifreq (hifreq[31:0]) // output[31:0] reg accumulated high frequency components in a frame sub-window
);
// Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was use3d for IMU instead of dcc
// Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was used for IMU instead of dcc
wire finish_dcc;
`ifdef USE_XCLK2X
wire [15:0] stuffer_do;
`else
wire [31:0] stuffer_do;
`endif
wire stuffer_dv;
wire stuffer_done;
wire eof_written_xclk2xn;
// re-sync to posedge xclk2x
reg xrst2xn;
always @ (negedge xclk2x) xrst2xn <= xrst;
`ifdef USE_XCLK2X
pulse_cross_clock finish_dcc_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
`else
assign finish_dcc = stuffer_done;
`endif
dcc_sync393 dcc_sync393_i (
`ifdef USE_XCLK2X
.sclk (xclk2x), // input
`else
.sclk (xclk), // input
`endif
.dcc_en (dcc_en), // input xclk rising, sync with start of the frame
.finish_dcc (finish_dcc), // input @ sclk rising
.dcc_vld (dccvld), // input xclk rising
......@@ -1053,6 +1105,7 @@ module jp_channel#(
// wire [2:0] dbg_block_mem_wa;
// wire [2:0] dbg_block_mem_wa_save;
`ifdef USE_XCLK2X
huffman393 i_huffman (
.xclk (xclk), // input
.xclk2x (xclk2x), // input
......@@ -1126,14 +1179,11 @@ module jp_channel#(
,.test_cntr1(test_cntr1[7:0])
`endif
);
/*
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
*/
//cat x393_testbench03-latest.log | grep "COMPRESSOR[32 ]*CHN" > compressors_out32.log
wire eof_written_xclk2xn;
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo cmprs_out_fifo_i (
// .rst (rst), // input mostly for simulation
// source (stuffer) clock domain
.wclk (~xclk2x), // input source clock (2x pixel clock, inverted) - same as stuffer out
.wrst (xrst2xn), // input mostly for simulation
......@@ -1155,6 +1205,103 @@ module jp_channel#(
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
);
pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
`ifdef DISPLAY_COMPRESSED_DATA
integer dbg_stuffer_word_number;
reg dbg_odd_stuffer_dv;
reg [15:0] dbg_even_stuffer_do;
wire [31:0] dbg_stuffer_do32 = {dbg_even_stuffer_do, stuffer_do};
always @ (negedge xclk2x) begin
if (stuffer_dv && dbg_odd_stuffer_dv) begin
$display ("COMPRESSOR CHN%d 0x%x -> 0x%x", CMPRS_NUMBER, dbg_stuffer_word_number, dbg_stuffer_do32);
end
if (stuffer_done) begin
$display ("COMPRESSOR CHN%d ***** DONE *****",CMPRS_NUMBER);
end
if (stuffer_dv && !dbg_odd_stuffer_dv) dbg_even_stuffer_do = stuffer_do;
if (!stuffer_en || stuffer_done) dbg_stuffer_word_number = 0;
else if (stuffer_dv && dbg_odd_stuffer_dv) dbg_stuffer_word_number = dbg_stuffer_word_number + 1;
if (!stuffer_en) dbg_odd_stuffer_dv = 0;
else if (stuffer_dv) dbg_odd_stuffer_dv = ~dbg_odd_stuffer_dv;
end
`endif
`else
huffman_stuffer_meta huffman_stuffer_meta_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
.en_huffman (frame_en), // input
.en_stuffer (stuffer_en), // input
.abort_stuffer (force_flush_long), // input
.tser_we (tser_he), // input
.tser_a_not_d (tser_a_not_d), // input
.tser_d (tser_d), // input[7:0]
.di (enc_do[15:0]), // input[15:0]
.ds (enc_dv), // input
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input valid @xclk - only for sec/usec
.data_out (stuffer_do), // output[31:0]
.data_out_valid (stuffer_dv), // output
.done (stuffer_done), // output
.running (stuffer_running), // output
.clk_flush (hclk), // input
.flush_clk (flush_hclk) // output
`ifdef DEBUG_RING
,.test_lbw (dbg_test_lbw), // output reg ??
.gotLastBlock (dbg_gotLastBlock), // output ?? - unused (was for debug)
.dbg_etrax_dma (etrax_dma), // output[3:0]
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) //output[7:0]
`endif
);
wire eof_written_xclk;
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo32 cmprs_out_fifo_i (
// source (stuffer) clock domain
.wclk (xclk), // input source clock (1x pixel clock, inverted) - same as stuffer out
.wrst (xrst), // input mostly for simulation
.we (stuffer_dv), // @ posedge(~xclk2x) input write data from stuffer
.wdata ({stuffer_do[7:0],stuffer_do[15:8],stuffer_do[23:16],stuffer_do[31:24]}), // input[15:0] data from stuffer module;
.wa_rst (!stuffer_en), // input reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
.wlast (stuffer_done), // input - written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
.eof_written_wclk (eof_written_xclk), // output - AFI had transferred frame data to the system memory
// AFI clock domain
.rclk (hclk), // @posedge(hclk) input - AFI clock
.rrst (hrst), // input - AFI clock
.rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count)
.ren (fifo_ren), // input - fifo read from AFI channel mux
.rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren)
.eof (fifo_eof), // output single hclk pulse signalling EOF
.eof_written (eof_written), // input single hclk pulse confirming frame data is written to the system memory
.flush_fifo (fifo_flush), // output level signalling that FIFO has data from the current frame (use short AXI burst if needed)
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
);
pulse_cross_clock eof_written_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(eof_written_xclk), .out_pulse(eof_written_mclk),.busy());
`ifdef DISPLAY_COMPRESSED_DATA
integer stuffer_word_number;
always @ (posedge xclk) begin
if (stuffer_dv) begin
$display ("COMPRESSOR CHN%d 0x%x -> 0x%x", CMPRS_NUMBER, stuffer_word_number, stuffer_do);
end
if (stuffer_done) begin
$display ("COMPRESSOR CHN%d ***** DONE *****",CMPRS_NUMBER);
end
if (!stuffer_en || stuffer_done) stuffer_word_number = 0;
else if (stuffer_dv) stuffer_word_number = stuffer_word_number + 1;
end
`endif
`endif
// TODO: Add status module to combine/FF, re-clock status signals
......
compressor_jp/varlen_encode393.v
View file @ 69b1d30b
......@@ -39,15 +39,7 @@ module varlen_encode393 (
output reg [3:0] l, // [3:0] code length
output reg [3:0] l_late,// delayed l (sync to q)
output reg [10:0] q); // [10:0]code
/*
varlen_encode393 i_varlen_encode(.clk(clk),
.en(stuffer_was_rdy), //will enable registers. 0 - freeze
.start(steps[0]),
.d(sval[11:0]), // 12-bit signed
.l(var_dl[ 3:0]), // [3:0] code length
.l_late(var_dl_late[3:0]),
.q(var_do[10:0])); // [10:0]code
*/
reg [11:0] d1;
reg [10:0] q0;
reg [2:0] cycles;
......
compressor_jp/varlen_encode_snglclk.v 0 → 100644
View file @ 69b1d30b
/*
** -----------------------------------------------------------------------------**
** varlen_encode_snglclk.v
**
** Part of the Huffman encoder for JPEG compressor - variable length encoder
**
** Copyright (C) 2002-2015 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** varlen_encode_snglclk.v is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module varlen_encode_snglclk (
input clk, // posedge
input [11:0] d, // 12-bit 2-s complement
output reg [3:0] l, // [3:0] code length, latency 2 clocks
output reg [10:0] q); // [10:0] literal, latency = 2 clocks
reg [11:0] d1;
wire this0 = |d1[ 3:0];
wire this1 = |d1[ 7:4];
wire this2 = |d1[10:8];
wire [1:0] codel0 = {|d1[ 3: 2],d1[ 3] || (d1[ 1] & ~d1[ 2])};
wire [1:0] codel1 = {|d1[ 7: 6],d1[ 7] || (d1[ 5] & ~d1[ 6])};
wire [1:0] codel2 = {|d1[ 10], (d1[ 9] & ~d1[10])};
wire [3:0] codel = this2? {2'b10,codel2[1:0]} :
(this1? {2'b01, codel1[1:0]} :
(this0 ? {2'b00,codel0[1:0]} : 4'b1111)); // after +1 will be 0;
always @(posedge clk) begin
d1[ 11] <= d[11];
d1[10:0] <= d[11] ? -d[10:0] : d[10:0];
q[10:0] <= d1[11] ? ~d1[10:0] : d1[10:0];
l <= codel[3:0]+1; // needed only ASAP, valid only 2 cycles after start
end
endmodule
compressor_jp/xdct393r.v 0 → 100644
View file @ 69b1d30b
/**********************************************************************
** -----------------------------------------------------------------------------**
** xdct393r.v
**
** 8x8 discrete Cosine Transform
** adding more registers to increase bandwidth
**
** Copyright (C) 2002-2015 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** xdct393r is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
** Modified by Andrey Filippov - goal to make it work in start/stop mode, using
** "start" input (going together with the first data, no restriction on the gap between 64-pixel blocks (>=0)
** Removed "RST" input ("en" is only used to reset ping-pong transpose memory address)
** Split module in 2 stages
** Also saved some area - original design compiled by XST to 865 slices (XC2S300e), this one - 780!
**
** It is based on the original design (Xilix app. note XAPP610) by:
** Author: Latha Pillai
** Senior Applications Engineer
**
** Video Applications
** Advanced Products Group
** Xilinx, Inc.
**
** Copyright (c) 2001 Xilinx, Inc.
** All rights reserved
**
** Date: Feb. 10, 2002
**
** RESTRICTED RIGHTS LEGEND
**
** This software has not been published by the author, and
** has been disclosed to others for the purpose of enhancing
** and promoting design productivity in Xilinx products.
**
** Therefore use, duplication or disclosure, now and in the
** future should give consideration to the productivity
** enhancements afforded the user of this code by the author's
** efforts. Thank you for using our products !
**
** Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
** WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
** IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
** A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
***********************************************************************/
/*
after I added DC subtraction before DCT I got 9-bit (allthough not likely to go out of 8bit range) signed data.
also increased transpose memory to 9 bits (anyway it is 16-bit wide) - see if it will help to prevent saturation
without significant increase in gates
Saturatuion is still visible on real pictures, but there was a bug - addsub<i>a_comp, addsub<i>b_comp where not using their
MSB. I added 1 more bit to add_sub<i>a and add_sub<i>b and fixed that bug. Only 2 mofre slices were used
*/
`timescale 1ns/1ps
// For xdct353 - increasing data in 9 bits -> 10 bits, out 12 bits ->13 bits
module xdct393r ( // increased latency by 3
input clk, // system clock, posedge
input en, // if zero will reset transpose memory page njumbers
input start, // single-cycle start pulse that goes with the first pixel data. Other 63 should follow
input [9:0] xin, // [7:0] - input data
output reg last_in, // output high during input of the last of 64 pixels in a 8x8 block
output pre_first_out, // 1 cycle ahead of the first output in a 64 block
output dv, // data output valid. Will go high on the 94-th cycle after the start
output [12:0] d_out); // [8:0]output data
wire stage1_done;
wire tm_page;
wire tm_we;
wire [6:0] tm_ra;
wire [6:0] tm_wa;
wire [15:0] tm_out;
wire [15:0] tm_di;
// reg stage1_done_r; // delay by one clock to use memory output register
wire tm_re; // =1'b1; // TODO: generate, for now just 1'b1
wire tm_regen;
always @ (posedge clk) begin
last_in <= (tm_wa[5:0]== 6'h30);
// stage1_done_r <= stage1_done;
// tm_regen <= tm_re;
end
dct393r_stage1 i_dct_stage1(
.clk (clk),
.en (en),
.start (start),
.xin (xin), // [7:0]
.we (tm_we), // write to transpose memory
.wr_cntr (tm_wa), // [6:0] transpose memory write address
.z_out (tm_di[15:0]),
.page (tm_page),
.done (stage1_done));
dct393r_stage2 i_dct_stage2(
.clk (clk),
.en (en),
.start (stage1_done), // stage 1 finished, data available in transpose memory (extra RAM latency)
.page (tm_page), // transpose memory page finished, valid at start
.rd_cntr (tm_ra[6:0]), // [6:0] transpose memory read address
.ren (tm_re), // output
.regen (tm_regen), // output reg
.tdin (tm_out[15:0]), // [7:0] - data from transpose memory
.endv (pre_first_out), // output
.dv (dv), // data output valid
.dct2_out (d_out[12:0])); // [10:0]output data
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY(0)
) i_transpose_mem (
.rclk (clk), // input
.raddr ({3'b0,tm_ra[6:0]}), // input[9:0]
.ren (tm_re), // input
.regen (tm_regen), // input
.data_out (tm_out[15:0]), // output[15:0]
.wclk (clk), // input
.waddr ({3'b0,tm_wa[6:0]}), // input[9:0]
.we (tm_we), // input
.web (4'hf), // input[3:0]
.data_in (tm_di[15:0]) // input[15:0]
);
endmodule
// 01/24/2004: Moved all clocks in stage 1 to "negedge" to reduce current pulses
module dct393r_stage1 ( // increased latency by 1
input clk, // system clock, posedge
input en,
input start, // single-cycle start pulse to replace RST
input [ 9:0] xin, // [7:0]
output we, // write to transpose memory
output [ 6:0] wr_cntr, // [6:0] transpose memory write address
output reg [15:0] z_out, //data to transpose memory
output page, // transpose memory page just filled (valid @ done)
output done); // last cycle writing to transpose memory - may use after it (move it earlier?)
/* constants */
localparam C3= 16'd54491;
localparam S3= 16'd36410;
localparam C4= 16'd46341;
localparam C6= 16'd25080;
localparam S6= 16'd60547;
localparam C7= 16'd12785;
localparam S7= 16'd64277;
reg [16:0] memory1a, memory2a, memory3a, memory4a;
/* 1D section */
/* The max value of a pixel after processing (to make their expected mean to zero)
is 127. If all the values in a row are 127, the max value of the product terms
would be (127*2)*(23170/256) and that of z_out_int would be (127*8)*23170/256.
This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of the value */
reg [ 9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in;
reg [ 9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg;
reg [ 9:0] addsub1a_comp, addsub2a_comp, addsub3a_comp, addsub4a_comp;
// reg [10:0] addsub1a_comp, addsub2a_comp, addsub3a_comp, addsub4a_comp; // AF2015: increasing width - was limiting
reg [10:0] add_sub1a, add_sub2a, add_sub3a, add_sub4a;
reg save_sign1a, save_sign2a, save_sign3a, save_sign4a;
reg [17:0] p1a, p2a, p3a, p4a;
wire [35:0] p1a_all, p2a_all, p3a_all, p4a_all;
reg toggleA;
reg [18:0] z_out_int1, z_out_int2;
reg [18:0] z_out_int;
wire [15:0] z_out_prelatch;
reg [ 2:0] indexi;
/* clks and counters */
reg [ 6:0] wr_cntr_prelatch;
/* memory section */
reg done_prelatch;
reg we_prelatch;
wire enwe;
wire pre_sxregs;
reg sxregs;
reg page_prelatch;
// TODO: See if negedge is needed
wire nclk = ~clk; // seems that everything here is running at negedge (and delays too), but not the transpose memory
// to conserve energy by disabling toggleA
wire sxregs_d8;
reg enable_toggle;
// SRL16_1 i_sxregs_d8 (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs)); // dly=7+1
dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(nclk),.rst(1'b0), .dly(4'd7), .din(sxregs), .dout(sxregs_d8)); // dly=7+1
// SRL16_1 i_pre_sxregs (.Q(pre_sxregs), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(start)); // dly=6+1
dly_16 #(.WIDTH(1)) i_pre_sxregs(.clk(nclk),.rst(1'b0), .dly(4'd6), .din(start), .dout(pre_sxregs)); // dly=6+1
// SRL16_1 i_enwe (.Q(enwe), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CLK(clk), .D(pre_sxregs)); // dly=5+1
dly_16 #(.WIDTH(1)) i_enwe(.clk(nclk),.rst(1'b0), .dly(4'd5), .din(pre_sxregs), .dout(enwe)); // dly=5+1
always @ (posedge nclk) begin
enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
done_prelatch<= (wr_cntr_prelatch[5:0]==6'h3f);
if (wr_cntr_prelatch[5:0]==6'h3f) page_prelatch <= wr_cntr_prelatch[6];
we_prelatch<= enwe || (en && we_prelatch && (wr_cntr_prelatch[5:0]!=6'h3f));
if (!en) wr_cntr_prelatch <= 7'b0;
else if (we_prelatch) wr_cntr_prelatch <= wr_cntr_prelatch + 1;
sxregs <= pre_sxregs || ((wr_cntr_prelatch[2:0]==3'h1) && (wr_cntr_prelatch[5:3]!=3'h7));
toggleA <= sxregs || (enable_toggle && (~toggleA));
if (sxregs) indexi <= 3'h7;
else if (enable_toggle) indexi<=indexi+1;
end
/* 1D-DCT BEGIN */
// store 1D-DCT constant coefficient values for multipliers */
always @ (posedge nclk) begin
case (indexi)
0 : begin memory1a <= {1'b0,C4}; //8'd91
memory2a <= {1'b0,C4}; //8'd91
memory3a <= {1'b0,C4}; //8'd91
memory4a <= {1'b0,C4}; //8'd91
end
1 : begin memory1a <= {1'b0,S7}; //8'd126;
memory2a <= {1'b0,C3}; //8'd106;
memory3a <= {1'b0,S3}; //8'd71;
memory4a <= {1'b0,C7}; //8'd25;
end
2 : begin memory1a <= {1'b0,S6}; //8'd118;
memory2a <= {1'b0,C6}; //8'd49;
memory3a <= {1'b1,C6}; //-8'd49;
memory4a <= {1'b1,S6}; //-8'd118
end
3 : begin memory1a <= {1'b0,C3}; // 8'd106;
memory2a <= {1'b1,C7}; //-8'd25;
memory3a <= {1'b1,S7}; //-8'd126;
memory4a <= {1'b1,S3}; //-8'd71;
end
4 : begin memory1a <= {1'b0,C4}; // 8'd91;
memory2a <= {1'b1,C4}; //-8'd91;
memory3a <= {1'b1,C4}; //-8'd91;
memory4a <= {1'b0,C4}; // 8'd91;
end
5 : begin memory1a <= {1'b0,S3}; // 8'd71;
memory2a <= {1'b1,S7}; //-8'd126;
memory3a <= {1'b0,C7}; // 8'd25;
memory4a <= {1'b0,C3}; // 8'd106;
end
6 : begin memory1a <= {1'b0,C6}; // 8'd49;
memory2a <= {1'b1,S6}; //-8'd118;
memory3a <= {1'b0,S6}; // 8'd118;
memory4a <= {1'b1,C6}; //-8'd49;
end
7 : begin memory1a <= {1'b0,C7}; // 8'd25;
memory2a <= {1'b1,S3}; //-8'd71;
memory3a <= {1'b0,C3}; // 8'd106;
memory4a <= {1'b1,S7}; //-8'd126;
end
endcase
end
/* 8-bit input shifted 8 times through a shift register*/
// xa0_in will see output registers from posedge, may be replaced by latches if needed - but currently delay is under 5ns
always @ (posedge nclk) begin
xa0_in <= xin;
xa1_in <= xa0_in;
xa2_in <= xa1_in;
xa3_in <= xa2_in;
xa4_in <= xa3_in;
xa5_in <= xa4_in;
xa6_in <= xa5_in;
xa7_in <= xa6_in;
end
/* shifted inputs registered every 8th clk (using cntr8)*/
always @ (posedge nclk) if (sxregs) begin
xa0_reg <= xa0_in;
xa1_reg <= xa1_in;
xa2_reg <= xa2_in;
xa3_reg <= xa3_in;
xa4_reg <= xa4_in;
xa5_reg <= xa5_in;
xa6_reg <= xa6_in;
xa7_reg <= xa7_in;
end
/* adder / subtractor block */
always @ (negedge clk)
if (toggleA == 1'b1) begin
add_sub1a <= {xa7_reg[9],xa7_reg[9:0]} + {xa0_reg[9],xa0_reg[9:0]};
add_sub2a <= {xa6_reg[9],xa6_reg[9:0]} + {xa1_reg[9],xa1_reg[9:0]};
add_sub3a <= {xa5_reg[9],xa5_reg[9:0]} + {xa2_reg[9],xa2_reg[9:0]};
add_sub4a <= {xa4_reg[9],xa4_reg[9:0]} + {xa3_reg[9],xa3_reg[9:0]};
end else begin
add_sub1a <= {xa7_reg[9],xa7_reg[9:0]} - {xa0_reg[9],xa0_reg[9:0]};
add_sub2a <= {xa6_reg[9],xa6_reg[9:0]} - {xa1_reg[9],xa1_reg[9:0]};
add_sub3a <= {xa5_reg[9],xa5_reg[9:0]} - {xa2_reg[9],xa2_reg[9:0]};
add_sub4a <= {xa4_reg[9],xa4_reg[9:0]} - {xa3_reg[9],xa3_reg[9:0]};
end
// First valid add_sub appears at the 10th clk (8 clks for shifting inputs,
// 9th clk for registering shifted input and 10th clk for add_sub
// to synchronize the i value to the add_sub value, i value is incremented
// only after 10 clks
// Adding these wires to get rid of the MSB that is always 0
wire [10:0] addsub1a_comp_w = add_sub1a[10]? (-add_sub1a) : add_sub1a;
wire [10:0] addsub2a_comp_w = add_sub2a[10]? (-add_sub2a) : add_sub2a;
wire [10:0] addsub3a_comp_w = add_sub3a[10]? (-add_sub3a) : add_sub3a;
wire [10:0] addsub4a_comp_w = add_sub4a[10]? (-add_sub4a) : add_sub4a;
always @ (posedge nclk) begin
save_sign1a <= add_sub1a[10];
save_sign2a <= add_sub2a[10];
save_sign3a <= add_sub3a[10];
save_sign4a <= add_sub4a[10];
addsub1a_comp <= addsub1a_comp_w[9:0]; //add_sub1a[10]? (-add_sub1a) : add_sub1a;
addsub2a_comp <= addsub2a_comp_w[9:0]; //add_sub2a[10]? (-add_sub2a) : add_sub2a;
addsub3a_comp <= addsub3a_comp_w[9:0]; //add_sub3a[10]? (-add_sub3a) : add_sub3a;
addsub4a_comp <= addsub4a_comp_w[9:0]; //add_sub4a[10]? (-add_sub4a) : add_sub4a;
end
assign p1a_all = addsub1a_comp * memory1a[15:0]; // [16] is sign!
assign p2a_all = addsub2a_comp * memory2a[15:0];
assign p3a_all = addsub3a_comp * memory3a[15:0];
assign p4a_all = addsub4a_comp * memory4a[15:0];
reg [17:0] p1a_all_r;
reg [17:0] p2a_all_r;
reg [17:0] p3a_all_r;
reg [17:0] p4a_all_r;
reg p1a_sig, p2a_sig, p3a_sig, p4a_sig;
always @ (posedge nclk) begin
p1a_all_r <= p1a_all[26:9];
p2a_all_r <= p2a_all[26:9];
p3a_all_r <= p3a_all[26:9];
p4a_all_r <= p4a_all[26:9];
p1a_sig <= (save_sign1a ^ memory1a[16]);
p2a_sig <= (save_sign2a ^ memory2a[16]);
p3a_sig <= (save_sign3a ^ memory3a[16]);
p4a_sig <= (save_sign4a ^ memory4a[16]);
end
always @ (posedge nclk) begin
p1a <= p1a_sig ? (-p1a_all_r) : p1a_all_r;
p2a <= p2a_sig ? (-p2a_all_r) : p2a_all_r;
p3a <= p3a_sig ? (-p3a_all_r) : p3a_all_r;
p4a <= p4a_sig ? (-p4a_all_r) : p4a_all_r;
end
/* Final adder. Adding the ouputs of the 4 multipliers */
always @ (posedge nclk) begin
z_out_int1 <= ({p1a[17],p1a} + {p2a[17],p2a});
z_out_int2 <= ({p3a[17],p3a} + {p4a[17],p4a});
z_out_int <= (z_out_int1 + z_out_int2);
end
// rounding of the value
assign z_out_prelatch[15:0] = z_out_int[18:3]+ z_out_int[2]; // correct rounding
// outputs from output latches to cross clock edge boundary
always @ (posedge clk) begin
z_out[15:0] <= z_out_prelatch[15:0];
// wr_cntr[6:0] <= wr_cntr_prelatch[6:0];
// done <= done_prelatch;
// we <= we_prelatch;
// page <= page_prelatch;
end
dly_16 #(.WIDTH(10)) i_delayed_outs(
.clk(clk),
.rst(1'b0),
.dly(4'd1),
.din( {wr_cntr_prelatch[6:0], done_prelatch, we_prelatch, page_prelatch}),
.dout({wr_cntr[6:0], done, we, page}));
/* 1D-DCT END */
endmodule
module dct393r_stage2 ( // increased latency by 2 clocks
input clk, // system clock, posedge
input en,
input start, // stage 1 finished, data available in transpose memory
input page, // transpose memory page finished, valid at start
output [6:0] rd_cntr, // [6:0] transpose memory read address
output ren, // read enable transpose memory
output reg regen, // register enable in transpose memory
input [15:0] tdin, // [15:0] - data from transpose memory, added 6 bit fractional part
output reg endv, // one cycle ahead of starting (continuing) dv
output reg dv, // data output valid
output reg [12:0] dct2_out);// [8:0]output data
/* constants */
localparam C3= 16'd54491;
localparam S3= 16'd36410;
localparam C4= 16'd46341;
localparam C6= 16'd25080;
localparam S6= 16'd60547;
localparam C7= 16'd12785;
localparam S7= 16'd64277;
reg [16:0] memory1a, memory2a, memory3a, memory4a;
reg [2:0] indexi;
/* 2D section */
reg [15:0] xb0_in, xb1_in, xb2_in, xb3_in, xb4_in, xb5_in, xb6_in, xb7_in;
reg [15:0] xb0_reg, xb1_reg, xb2_reg, xb3_reg, xb4_reg, xb5_reg, xb6_reg, xb7_reg;
reg [16:0] add_sub1b, add_sub2b, add_sub3b, add_sub4b;
reg [15:0] addsub1b_comp, addsub2b_comp, addsub3b_comp, addsub4b_comp;
reg save_sign1b, save_sign2b, save_sign3b, save_sign4b;
reg [18:0] p1b, p2b, p3b, p4b;
wire [35:0] p1b_all, p2b_all, p3b_all, p4b_all;
reg toggleB;
reg [19:0] dct2d_int1, dct2d_int2;
reg [20:0] dct_2d_int;
wire [12:0] dct_2d_rnd;
// transpose memory read address
reg [ 5:0] rd_cntrs;
reg rd_page;
// start with the same as stage1
wire sxregs;
// to conserve energy by disabling toggleB
wire sxregs_d8;
reg enable_toggle;
reg en_started;
wire pre2_endv;
wire pre2_disdv; // AF2015: was missing
reg pre_endv;
reg pre_disdv;
reg pre_dv;
// SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1
// dly_16 #(.WIDTH(1)) i_endv(.clk(clk),.rst(1'b0), .dly(4'd14), .din(start), .dout(endv)); // dly=14+1
dly_16 #(.WIDTH(1)) i_pre2_endv(.clk(clk),.rst(1'b0), .dly(4'd15), .din(start), .dout(pre2_endv)); // dly=15+1
// SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntrs[5:0]==6'h3f)); // dly=14+1
// dly_16 #(.WIDTH(1)) i_disdv(.clk(clk),.rst(1'b0), .dly(4'd14), .din(rd_cntrs[5:0]==6'h3f), .dout(disdv)); // dly=14+1
dly_16 #(.WIDTH(1)) i_pre2_disdv(.clk(clk),.rst(1'b0), .dly(4'd15), .din(rd_cntrs[5:0]==6'h3f), .dout(pre2_disdv)); // dly=15+1
// SRL16 i_sxregs (.Q(sxregs), .A0(1'b0), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(clk),.D((rd_cntr[5:3]==3'h0) && en_started)); // dly=8+1
// dly_16 #(.WIDTH(1)) i_sxregs(.clk(clk),.rst(1'b0), .dly(4'd8), .din((rd_cntr[5:3]==3'h0) && en_started), .dout(sxregs)); // dly=8+1
dly_16 #(.WIDTH(1)) i_sxregs(.clk(clk),.rst(1'b0), .dly(4'd9), .din((rd_cntrs[2:0]==3'h0) && en_started), .dout(sxregs)); // dly=9+1
// SRL16 i_sxregs_d8 (.Q(sxregs_d8), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(clk),.D(sxregs && en_started)); // dly=7+1
dly_16 #(.WIDTH(1)) i_sxregs_d8(.clk(clk),.rst(1'b0), .dly(4'd7), .din(sxregs && en_started), .dout(sxregs_d8)); // dly=7+1
assign ren = en_started;
always @ (posedge clk) begin
enable_toggle <= en && (sxregs || (enable_toggle && !sxregs_d8));
// en_started <= en && (start || en_started);
if (!en) en_started <= 0;
else if (start) en_started <= 1;
else if (rd_cntrs[5:0] == 6'h3f) en_started <= 0; // should be after (start) as they happen simultaneously
regen <= en_started;
pre_endv <=pre2_endv;
endv <= pre_endv; // output reg
pre_disdv <= pre2_disdv;
pre_dv <= en && (pre_endv || (pre_dv && ~pre_disdv));
// dv <= en && (endv || (dv && ~disdv));
dv <= en && pre_dv; // output reg
toggleB <= sxregs || (enable_toggle && (~toggleB));
if (sxregs) indexi <= 3'h7;
else if (enable_toggle) indexi<=indexi+1;
if (start) rd_page <= page;
if (start) rd_cntrs[5:0] <=6'b0; // will always count, but that does not matter- What about saving energy ;-) ? Saved...
else if (rd_cntrs[5:0]!=6'h3f) rd_cntrs[5:0] <= rd_cntrs[5:0]+1;
end
assign rd_cntr[6:0]= {rd_page,rd_cntrs[2:0],rd_cntrs[5:3]}; // transposed counter
// duplicate memory<i>a from stage 1
// store 1D-DCT constant coeeficient values for multipliers */
always @ (posedge clk) begin
case (indexi)
0 : begin memory1a <= {1'b0,C4}; //8'd91
memory2a <= {1'b0,C4}; //8'd91
memory3a <= {1'b0,C4}; //8'd91
memory4a <= {1'b0,C4}; //8'd91
end
1 : begin memory1a <= {1'b0,S7}; //8'd126;
memory2a <= {1'b0,C3}; //8'd106;
memory3a <= {1'b0,S3}; //8'd71;
memory4a <= {1'b0,C7}; //8'd25;
end
2 : begin memory1a <= {1'b0,S6}; //8'd118;
memory2a <= {1'b0,C6}; //8'd49;
memory3a <= {1'b1,C6}; //-8'd49;
memory4a <= {1'b1,S6}; //-8'd118
end
3 : begin memory1a <= {1'b0,C3}; // 8'd106;
memory2a <= {1'b1,C7}; //-8'd25;
memory3a <= {1'b1,S7}; //-8'd126;
memory4a <= {1'b1,S3}; //-8'd71;
end
4 : begin memory1a <= {1'b0,C4}; // 8'd91;
memory2a <= {1'b1,C4}; //-8'd91;
memory3a <= {1'b1,C4}; //-8'd91;
memory4a <= {1'b0,C4}; // 8'd91;
end
5 : begin memory1a <= {1'b0,S3}; // 8'd71;
memory2a <= {1'b1,S7}; //-8'd126;
memory3a <= {1'b0,C7}; // 8'd25;
memory4a <= {1'b0,C3}; // 8'd106;
end
6 : begin memory1a <= {1'b0,C6}; // 8'd49;
memory2a <= {1'b1,S6}; //-8'd118;
memory3a <= {1'b0,S6}; // 8'd118;
memory4a <= {1'b1,C6}; //-8'd49;
end
7 : begin memory1a <= {1'b0,C7}; // 8'd25;
memory2a <= {1'b1,S3}; //-8'd71;
memory3a <= {1'b0,C3}; // 8'd106;
memory4a <= {1'b1,S7}; //-8'd126;
end
endcase
end
always @ (posedge clk) begin
xb0_in <= tdin;
xb1_in <= xb0_in;
xb2_in <= xb1_in;
xb3_in <= xb2_in;
xb4_in <= xb3_in;
xb5_in <= xb4_in;
xb6_in <= xb5_in;
xb7_in <= xb6_in;
end
/* register inputs, inputs read in every eighth clk*/
always @ (posedge clk) if (sxregs) begin
xb0_reg <= xb0_in;
xb1_reg <= xb1_in;
xb2_reg <= xb2_in;
xb3_reg <= xb3_in;
xb4_reg <= xb4_in;
xb5_reg <= xb5_in;
xb6_reg <= xb6_in;
xb7_reg <= xb7_in;
end
always @ (posedge clk)
if (toggleB == 1'b1) begin
add_sub1b <= {xb7_reg[15],xb7_reg[15:0]} + {xb0_reg[15],xb0_reg[15:0]};
add_sub2b <= {xb6_reg[15],xb6_reg[15:0]} + {xb1_reg[15],xb1_reg[15:0]};
add_sub3b <= {xb5_reg[15],xb5_reg[15:0]} + {xb2_reg[15],xb2_reg[15:0]};
add_sub4b <= {xb4_reg[15],xb4_reg[15:0]} + {xb3_reg[15],xb3_reg[15:0]};
end else begin
add_sub1b <= {xb7_reg[15],xb7_reg[15:0]} - {xb0_reg[15],xb0_reg[15:0]};
add_sub2b <= {xb6_reg[15],xb6_reg[15:0]} - {xb1_reg[15],xb1_reg[15:0]};
add_sub3b <= {xb5_reg[15],xb5_reg[15:0]} - {xb2_reg[15],xb2_reg[15:0]};
add_sub4b <= {xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]};
end
// Adding these wires to get rid of the MSB that is always 0
wire [16:0] addsub1b_comp_w = add_sub1b[16]? (-add_sub1b) : add_sub1b;
wire [16:0] addsub2b_comp_w = add_sub2b[16]? (-add_sub2b) : add_sub2b;
wire [16:0] addsub3b_comp_w = add_sub3b[16]? (-add_sub3b) : add_sub3b;
wire [16:0] addsub4b_comp_w = add_sub4b[16]? (-add_sub4b) : add_sub4b;
always @ (posedge clk) begin
save_sign1b <= add_sub1b[16];
save_sign2b <= add_sub2b[16];
save_sign3b <= add_sub3b[16];
save_sign4b <= add_sub4b[16];
addsub1b_comp <= addsub1b_comp_w[15:0]; // add_sub1b[16]? (-add_sub1b) : add_sub1b;
addsub2b_comp <= addsub2b_comp_w[15:0]; // add_sub2b[16]? (-add_sub2b) : add_sub2b;
addsub3b_comp <= addsub3b_comp_w[15:0]; // add_sub3b[16]? (-add_sub3b) : add_sub3b;
addsub4b_comp <= addsub4b_comp_w[15:0]; // add_sub4b[16]? (-add_sub4b) : add_sub4b;
end
assign p1b_all = addsub1b_comp * memory1a[15:0]; // MSB [16] is sign!
assign p2b_all = addsub2b_comp * memory2a[15:0];
assign p3b_all = addsub3b_comp * memory3a[15:0];
assign p4b_all = addsub4b_comp * memory4a[15:0];
reg [18:0] p1b_all_r;
reg [18:0] p2b_all_r;
reg [18:0] p3b_all_r;
reg [18:0] p4b_all_r;
reg p1b_sig, p2b_sig, p3b_sig, p4b_sig;
always @ (posedge clk) begin
p1b_all_r <= p1b_all[32:14];
p2b_all_r <= p2b_all[32:14];
p3b_all_r <= p3b_all[32:14];
p4b_all_r <= p4b_all[32:14];
p1b_sig <= (save_sign1b ^ memory1a[16]);
p2b_sig <= (save_sign2b ^ memory2a[16]);
p3b_sig <= (save_sign3b ^ memory3a[16]);
p4b_sig <= (save_sign4b ^ memory4a[16]);
end
always @ (posedge clk) begin
p1b[18:0] <= p1b_sig ? (-p1b_all_r) :(p1b_all_r);
p2b[18:0] <= p2b_sig ? (-p2b_all_r) :(p2b_all_r);
p3b[18:0] <= p3b_sig ? (-p3b_all_r) :(p3b_all_r);
p4b[18:0] <= p4b_sig ? (-p4b_all_r) :(p4b_all_r);
end
/* multiply the outputs of the add/sub block with the 8 sets of stored coefficients */
/* Final adder. Adding the ouputs of the 4 multipliers */
always @ (posedge clk) begin
dct2d_int1 <= ({p1b[18],p1b[18:0]} + {p2b[18],p2b[18:0]});
dct2d_int2 <= ({p3b[18],p3b[18:0]} + {p4b[18],p4b[18:0]});
dct_2d_int <= ({dct2d_int1[19],dct2d_int1[19:0]} + {dct2d_int2[19],dct2d_int2[19:0]});
if (pre_dv) dct2_out[12:0] <= dct_2d_rnd[12:0] + dct_2d_int[7];
end
assign dct_2d_rnd[12:0] = dct_2d_int[20:8];
// assign dct2_out[12:0] = dct_2d_rnd[12:0] + dct_2d_int[7];
endmodule
ddr3/ddr3.v
View file @ 69b1d30b
......@@ -85,7 +85,7 @@
* 1.69 SPH 03/19/13 Update tZQCS, tZQinit, tZQoper timing parameters
* 1.70 SPH 04/08/14 Update tRFC to PRECARGE check
*****************************************************************************************/
`define den4096Mb 1
`include "system_defines.vh"
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
......@@ -121,6 +121,19 @@ module ddr3 (
// to select the correct component density before continuing
ERROR: You must specify component density with +define+den____Mb.
`endif
initial begin
$display ("TCK_MIN = %d", TCK_MIN);
`ifdef sg15E
$display ("sg15E = `sg15E");
`endif
`ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
$display ("sg093");
`elsif sg15E
$display ("sg15E");
`endif
end
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
......
fpga_version.vh
View file @ 69b1d30b
parameter FPGA_VERSION = 32'h03930042;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
// parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
// parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
// parameter FPGA_VERSION = 32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases
// parameter FPGA_VERSION = 32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
// parameter FPGA_VERSION = 32'h03930061; // restored bufr instead of bufio for memory high speed clock
// parameter FPGA_VERSION = 32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib
// parameter FPGA_VERSION = 32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
// parameter FPGA_VERSION = 32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
// parameter FPGA_VERSION = 32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
// parameter FPGA_VERSION = 32'h0393005c; // 250MHz OK, no timing violations
// parameter FPGA_VERSION = 32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
// parameter FPGA_VERSION = 32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
// parameter FPGA_VERSION = 32'h03930059; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930058; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - broken end of frame
// parameter FPGA_VERSION = 32'h03930057; // 'new' (no pclk2x, yes xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
// parameter FPGA_VERSION = 32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK
// parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
// parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
\ No newline at end of file
includes/x393_parameters.vh
View file @ 69b1d30b
......@@ -138,7 +138,11 @@
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
`ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
......@@ -150,11 +154,12 @@
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000, //11.25, /// 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
parameter MCLK_PHASE = 90.000, //78.75, // 90.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
......@@ -273,6 +278,7 @@
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
......@@ -429,11 +435,20 @@
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
//`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
//`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
//`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
......@@ -442,7 +457,9 @@
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
//`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
//`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
......@@ -466,10 +483,13 @@
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 4'd5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
//`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
......@@ -505,15 +525,30 @@
`endif
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
//`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
......@@ -530,12 +565,24 @@
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
//`ifdef HISPI
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT",
//`endif
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
......@@ -760,12 +807,19 @@
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
`ifdef HISPI
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 36, // 880 MHz
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
`endif
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
......@@ -773,7 +827,11 @@
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
`else
parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
`endif
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
......
includes/x393_simulation_parameters.vh
View file @ 69b1d30b
......@@ -38,6 +38,10 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR_IMAGE_TYPE0 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......
includes/x393_tasks_mcntrl_timing.vh
View file @ 69b1d30b
......@@ -193,12 +193,20 @@
task axi_set_phase;
input [PHASE_WIDTH-1:0] phase;
begin
reg [PHASE_WIDTH-1:0] inverted_phase;
begin
if (CLKFBOUT_USE_FINE_PS) begin
inverted_phase = -phase;
$display("SET CLOCK INVERTED PHASE (0x%x) to 0x%x @ %t",phase,inverted_phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},inverted_phase}); // control regiter address
target_phase <= inverted_phase;
end else begin
$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
write_contol_register(DLY_SET,0);
target_phase <= phase;
end
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_wbuf_delay;
......
input_data/sensor_run1.dat 0 → 100644
View file @ 69b1d30b
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001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
memctrl/cmd_encod_tiled_32_rd.v
View file @ 69b1d30b
......@@ -224,7 +224,7 @@ module cmd_encod_tiled_32_rd #(
// ROM-based (registered output) encoded sequence
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
if (mrst) rom_r <= 0; // TODO: make mrst cause gen_addr = 4'hf?
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
......
memctrl/mcntrl393.v
View file @ 69b1d30b
......@@ -153,6 +153,7 @@ module mcntrl393 #(
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
......@@ -241,7 +242,8 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
) (
input rst_in,
......@@ -299,6 +301,7 @@ module mcntrl393 #(
output [3:0] sens_buf_rd, // (), // input
input [255:0] sens_buf_dout, // (), // output[63:0]
input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer
output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block.
// compressor subsystem interface
// Buffer interfaces, combined for 4 channels
output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw (
......@@ -412,6 +415,7 @@ module mcntrl393 #(
wire want_rq0;
wire need_rq0;
wire channel_pgm_en0;
wire reject0 = 1'b0;
wire [9:0] seq_data0; // only 10 bits used
// wire seq_wr0; // not used
wire seq_set0;
......@@ -428,6 +432,7 @@ module mcntrl393 #(
wire want_rq1;
wire need_rq1;
wire channel_pgm_en1;
wire reject1; // = 1'b0;
wire seq_done1;
// routed outside to membredge module
/*
......@@ -441,6 +446,7 @@ module mcntrl393 #(
wire want_rq2;
wire need_rq2;
wire channel_pgm_en2;
wire reject2 = 1'b0;
wire seq_done2;
wire buf_wr_chn2;
wire buf_wpage_nxt_chn2;
......@@ -452,6 +458,7 @@ module mcntrl393 #(
wire want_rq3;
wire need_rq3;
wire channel_pgm_en3;
wire reject3; // = 1'b0;
wire seq_done3;
wire buf_wr_chn3;
wire buf_wpage_nxt_chn3;
......@@ -463,6 +470,7 @@ module mcntrl393 #(
wire want_rq4;
wire need_rq4;
wire channel_pgm_en4;
wire reject4 = 1'b0;
wire seq_done4;
wire buf_wr_chn4;
wire buf_wpage_nxt_chn4;
......@@ -538,6 +546,7 @@ module mcntrl393 #(
wire [3:0] cmprs_need;
wire [3:0] sens_channel_pgm_en;
wire [3:0] sens_reject;
wire [3:0] sens_start_wr;
wire [11:0] sens_bank; // output[2:0]
wire [4*ADDRESS_NUMBER-1:0] sens_row; // output[14:0]
......@@ -547,6 +556,7 @@ module mcntrl393 #(
wire [3:0] sens_seq_done; // input : sequence over
wire [3:0] cmprs_channel_pgm_en;
wire [3:0] cmprs_reject = 4'h0;
wire [3:0] cmprs_start_rd16;
wire [3:0] cmprs_start_rd32;
wire [11:0] cmprs_bank; // output[2:0]
......@@ -1059,7 +1069,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
) mcntrl_linear_wr_sensor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1078,6 +1089,7 @@ module mcntrl393 #(
.xfer_want (sens_want[i]), // output
.xfer_need (sens_need[i]), // output
.xfer_grant (sens_channel_pgm_en[i]), // input
.xfer_reject (sens_reject[i]), // output
.xfer_start_rd (), // output
.xfer_start_wr (sens_start_wr[i]), // output
.xfer_bank (sens_bank[3 * i +: 3]), // output[2:0]
......@@ -1088,6 +1100,7 @@ module mcntrl393 #(
.xfer_done (sens_seq_done[i]), // input : page sequence over
.xfer_page_rst_wr (sens_rpage_set[i]), // output @ posedge mclk
.xfer_page_rst_rd (), // output @ negedge mclk
.xfer_skipped (sens_xfer_skipped[i]), // output reg
.cmd_wrmem () // output
);
......@@ -1196,7 +1209,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
) mcntrl_linear_rw_chn1_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1215,6 +1229,7 @@ module mcntrl393 #(
.xfer_want (want_rq1), // output
.xfer_need (need_rq1), // output
.xfer_grant (channel_pgm_en1), // input
.xfer_reject (reject1), //input
.xfer_start_rd (lin_rw_chn1_start_rd), // output
.xfer_start_wr (lin_rw_chn1_start_wr), // output
.xfer_bank (lin_rw_chn1_bank), // output[2:0]
......@@ -1225,6 +1240,7 @@ module mcntrl393 #(
.xfer_done (seq_done1), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page1_wr), // output
.xfer_page_rst_rd (xfer_reset_page1_rd), // output
.xfer_skipped (), // output reg
.cmd_wrmem (cmd_wrmem_chn1) // output
);
......@@ -1257,7 +1273,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
) mcntrl_linear_rw_chn3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1276,6 +1293,7 @@ module mcntrl393 #(
.xfer_want (want_rq3), // output
.xfer_need (need_rq3), // output
.xfer_grant (channel_pgm_en3), // input
.xfer_reject (reject3), //input
.xfer_start_rd (lin_rw_chn3_start_rd), // output
.xfer_start_wr (lin_rw_chn3_start_wr), // output
.xfer_bank (lin_rw_chn3_bank), // output[2:0]
......@@ -1286,6 +1304,7 @@ module mcntrl393 #(
.xfer_done (seq_done3), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page3_wr), // output
.xfer_page_rst_rd (xfer_reset_page3_rd), // output
.xfer_skipped (), // output reg
.cmd_wrmem () // output
);
......@@ -1390,7 +1409,6 @@ module mcntrl393 #(
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rw_chn4_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1799,6 +1817,7 @@ module mcntrl393 #(
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
......@@ -1836,6 +1855,7 @@ module mcntrl393 #(
.want_rq0 (want_rq0), // input
.need_rq0 (need_rq0), // input
.channel_pgm_en0 (channel_pgm_en0), // output reg
.reject0 (reject0), // input
.seq_done0 (seq_done0), // output
.page_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0), // output
......@@ -1850,6 +1870,7 @@ module mcntrl393 #(
.want_rq1 (want_rq1), // input
.need_rq1 (need_rq1), // input
.channel_pgm_en1 (channel_pgm_en1), // output reg
.reject1 (reject1), // input
.seq_done1 (seq_done1), // output
.page_nxt_chn1 (page_ready_chn1), //rpage_nxt_chn0), not used
.buf_run1 (), // output
......@@ -1864,6 +1885,7 @@ module mcntrl393 #(
.want_rq2 (want_rq2), // input
.need_rq2 (need_rq2), // input
.channel_pgm_en2 (channel_pgm_en2), // output reg
.reject2 (reject2), // input
.seq_done2 (seq_done2), // output
.page_nxt_chn2 (page_ready_chn2), //rpage_nxt_chn0), not used
.buf_run2 (), // output //buf_run2),
......@@ -1878,6 +1900,7 @@ module mcntrl393 #(
.want_rq3 (want_rq3), // input
.need_rq3 (need_rq3), // input
.channel_pgm_en3 (channel_pgm_en3), // output reg
.reject3 (reject3), // input
.seq_done3 (seq_done3), // output
.page_nxt_chn3 (page_ready_chn3), //rpage_nxt_chn0), not used
.buf_run3 (), // output//buf_run3),
......@@ -1892,6 +1915,7 @@ module mcntrl393 #(
.want_rq4 (want_rq4), // input
.need_rq4 (need_rq4), // input
.channel_pgm_en4 (channel_pgm_en4), // output reg
.reject4 (reject4), // input
.seq_done4 (seq_done4), // output
.page_nxt_chn4 (page_ready_chn4), //rpage_nxt_chn0), not used
.buf_run4 (), // output //buf_run4),
......@@ -1906,6 +1930,7 @@ module mcntrl393 #(
.want_rq8 (sens_want[0]), // input
.need_rq8 (sens_need[0]), // input
.channel_pgm_en8 (sens_channel_pgm_en[0]), // output reg
.reject8 (sens_reject[0]), // input
.seq_done8 (sens_seq_done[0]), // output
.page_nxt_chn8 (), // output ?
.buf_run8 (), // output
......@@ -1916,6 +1941,7 @@ module mcntrl393 #(
.want_rq9 (sens_want[1]), // input
.need_rq9 (sens_need[1]), // input
.channel_pgm_en9 (sens_channel_pgm_en[1]), // output reg
.reject9 (sens_reject[1]), // input
.seq_done9 (sens_seq_done[1]), // output
.page_nxt_chn9 (), // output ?
.buf_run9 (), // output
......@@ -1926,6 +1952,7 @@ module mcntrl393 #(
.want_rq10 (sens_want[2]), // input
.need_rq10 (sens_need[2]), // input
.channel_pgm_en10 (sens_channel_pgm_en[2]), // output reg
.reject10 (sens_reject[2]), // input
.seq_done10 (sens_seq_done[2]), // output
.page_nxt_chn10 (), // output
.buf_run10 (), // output
......@@ -1936,6 +1963,7 @@ module mcntrl393 #(
.want_rq11 (sens_want[3]), // input
.need_rq11 (sens_need[3]), // input
.channel_pgm_en11 (sens_channel_pgm_en[3]), // output reg
.reject11 (sens_reject[3]), // input
.seq_done11 (sens_seq_done[3]), // output
.page_nxt_chn11 (), // output
.buf_run11 (), // output
......@@ -1946,6 +1974,7 @@ module mcntrl393 #(
.want_rq12 (cmprs_want[0]), // input
.need_rq12 (cmprs_need[0]), // input
.channel_pgm_en12 (cmprs_channel_pgm_en[0]), // output reg
.reject12 (cmprs_reject[0]), // input
.seq_done12 (cmprs_seq_done[0]), // output
.page_nxt_chn12 (cmprs_page_ready[0]), // output ???
.buf_run12 (), // output
......@@ -1957,6 +1986,7 @@ module mcntrl393 #(
.want_rq13 (cmprs_want[1]), // input
.need_rq13 (cmprs_need[1]), // input
.channel_pgm_en13 (cmprs_channel_pgm_en[1]), // output reg
.reject13 (cmprs_reject[1]), // input
.seq_done13 (cmprs_seq_done[1]), // output
.page_nxt_chn13 (cmprs_page_ready[1]), // output ???
.buf_run13 (), // output
......@@ -1968,6 +1998,7 @@ module mcntrl393 #(
.want_rq14 (cmprs_want[2]), // input
.need_rq14 (cmprs_need[2]), // input
.channel_pgm_en14 (cmprs_channel_pgm_en[2]), // output reg
.reject14 (cmprs_reject[2]), // input
.seq_done14 (cmprs_seq_done[2]), // output
.page_nxt_chn14 (cmprs_page_ready[2]), // output ???
.buf_run14 (), // output
......@@ -1979,6 +2010,7 @@ module mcntrl393 #(
.want_rq15 (cmprs_want[3]), // input
.need_rq15 (cmprs_need[3]), // input
.channel_pgm_en15 (cmprs_channel_pgm_en[3]), // output reg
.reject15 (cmprs_reject[3]), // input
.seq_done15 (cmprs_seq_done[3]), // output
.page_nxt_chn15 (cmprs_page_ready[3]), // output ???
.buf_run15 (), // output
......
memctrl/mcntrl_linear_rw.v
View file @ 69b1d30b
......@@ -57,7 +57,8 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
)(
input mrst,
input mclk,
......@@ -82,6 +83,7 @@ module mcntrl_linear_rw #(
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
output xfer_reject, // reject granted access (when skipping)
output xfer_start_rd, // initiate a transfer (next cycle after xfer_grant)
output xfer_start_wr, // initiate a transfer (next cycle after xfer_grant)
output [2:0] xfer_bank, // bank address
......@@ -92,6 +94,7 @@ module mcntrl_linear_rw #(
input xfer_done, // transfer to/from the buffer finished
output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge
output xfer_page_rst_rd, // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
output reg xfer_skipped,
output cmd_wrmem
);
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
......@@ -150,6 +153,7 @@ module mcntrl_linear_rw #(
// wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire skip_too_late;
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
......@@ -173,6 +177,7 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
wire pre_want;
reg pre_want_r1;
wire [1:0] status_data;
wire [3:0] cmd_a;
wire [31:0] cmd_data;
......@@ -191,7 +196,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [12:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
......@@ -214,7 +219,7 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start
reg xfer_done_d; // xfer_done delayed by 1 cycle;
reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
assign frame_number = frame_number_current;
assign set_mode_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
......@@ -233,7 +238,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // 4:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[12:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -261,8 +266,8 @@ module mcntrl_linear_rw #(
if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number;
if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
// if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
if (mrst) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1;
......@@ -320,8 +325,9 @@ module mcntrl_linear_rw #(
assign frame_done= frame_done_r;
assign frame_finished= frame_finished_r;
// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !frame_start_r[0];
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
// assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r);
// accelerating pre_want:
assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
assign last_row_w= next_y==window_height;
......@@ -337,19 +343,80 @@ module mcntrl_linear_rw #(
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
integer i;
wire xfer_limited_by_mem_page;
wire xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
reg xfer_limited_by_mem_page_r;
assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
// skipping pages that did not make it
// reg skip_tail; // skip end of frame if the next frame started (TBD)
// Now skip if write and >=4 or read and >=5 (read starts with 4 and may end with 4)
// Also if the next page signal is used by the source/dest of data, it should use reject pulse to advance external
// page counter
wire start_skip_w;
reg start_skip_r;
reg skip_run = 0; // run "skip" - advance addresses, but no actual read/write
reg xfer_reject_r;
reg frame_start_pending; // frame_start came before previous one was finished
reg [1:0] frame_start_pending_long;
wire xfer_done_skipped = xfer_skipped || xfer_done;
wire frame_start_delayed = frame_start_pending_long[1] && !frame_start_pending_long[0];
wire frame_start_mod = (frame_start && !busy_r) || frame_start_delayed; // when frame_start_delayed it will completely miss a frame_start
assign xfer_reject = xfer_reject_r;
assign start_skip_w = skip_too_late && want_r && !xfer_grant && !skip_run &&
(((|page_cntr) && frame_start_pending) || ((page_cntr >= 4) && (cmd_wrmem || page_cntr[0]))); //&& busy_r && skip_run;
always @(posedge mclk) begin // Handling skip/reject
if (mrst) xfer_reject_r <= 0;
else xfer_reject_r <= xfer_grant && !chn_rst && skip_run;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r};
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !skip_run;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !skip_run;
if (mrst || recalc_r[PAR_MOD_LATENCY-1]) skip_run <= 0;
else if (start_skip_w) skip_run <= 1;
if (mrst) start_skip_r <= 0;
else start_skip_r <= start_skip_w;
if (mrst) xfer_skipped <= 0;
else xfer_skipped <= start_not_partial && skip_run;
// if (mrst || frame_start_delayed) frame_start_pending <= 0;
if (mrst) frame_start_pending <= 0;
// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] | frame_start)};
else frame_start_pending <= busy_r && (frame_start_pending | frame_start);
if (mrst) frame_start_pending_long <= 0;
else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r || skip_run) && (frame_start_pending_long[0] | frame_start)};
if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en};
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant || start_skip_r) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0;
else if (pre_want && (page_cntr > {1'b0,cmd_extra_pages})) want_r <= 1;
end
/// Recalcualting just after starting request - preparing for the next one. Also happens after parameter change.
/// Should dpepend only on the parameters updated separately (curr_x, curr_y)
/// Should dppend only on the parameters updated separately (curr_x, curr_y)
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
if (recalc_r[0]) begin // cycle 1
frame_x <= curr_x + window_x0;
......@@ -404,6 +471,9 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// now have row start address, bank and row_left ;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge mclk) begin
// acceletaring pre_want
pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
if (mrst) par_mod_r<=0;
else if (pgm_param_w ||
xfer_start_r[0] ||
......@@ -425,7 +495,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (frame_done_r) busy_r <= 0;
if (mrst) xfer_done_d <= 0;
else xfer_done_d <= xfer_done;
else xfer_done_d <= xfer_done_skipped;
if (mrst) continued_xfer <= 1'b0;
......@@ -442,22 +512,14 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem;
// if (mrst || disable_need) need_r <= 0;
// else if (chn_rst || xfer_grant || start_skip_r) need_r <= 0;
// else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
// if (mrst) want_r <= 0;
// else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0;
// else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
if (mrst) page_cntr <= 0;
else if (frame_start_r[0]) page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end?
......@@ -486,35 +548,13 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (mrst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
/*
//line_unfinished_r cmd_wrmem
if (mrst) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (mrst) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
// else if (chn_rst || frame_start_r[0]) line_unfinished_r[1] <= window_y0+start_y;
else if (chn_rst || frame_start_r[2]) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= line_unfinished_r[0 +: FRAME_HEIGHT_BITS];
*/
/*
if (mrst) line_unfinished_relw_r <= 0;
else if (cmd_wrmem && (frame_start_r[1] || !chn_en)) line_unfinished_relw_r <= start_y;
else if ((!cmd_wrmem && recalc_r[1]) || xfer_start_r[2]) line_unfinished_relw_r <= next_y[FRAME_HEIGHT_BITS-1:0];
// xfer_start_r[2] and recalc_r[1] are at the same time
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
*/
else if ( xfer_start_r[0] && !xfer_done_skipped) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done_skipped) pending_xfers <= pending_xfers - 1;
if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: 1);
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
// if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
if (mrst || (frame_start_mod || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
......
memctrl/memctrl16.v
View file @ 69b1d30b
......@@ -126,6 +126,7 @@ module memctrl16 #(
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
......@@ -168,6 +169,7 @@ module memctrl16 #(
input want_rq0, // both want_rq and need_rq should go inactive after being granted
input need_rq0, // want_rq should be active when need_rq is.
output reg channel_pgm_en0, // channel can program sequence data
input reject0, // reject grant
output seq_done0, // sequencer finished executing sequence for this channel
output page_nxt_chn0,
output buf_run0, // external buffer run (may be used to force page) @posedge mclk
......@@ -189,6 +191,7 @@ module memctrl16 #(
input want_rq1, // both want_rq and need_rq should go inactive after being granted
input need_rq1,
output reg channel_pgm_en1, // channel can program sequence data
input reject1, // reject grant
output seq_done1, // sequencer finished executing sequence for this channel
output page_nxt_chn1,
output buf_run1, // external buffer run (may be used to force page) @posedge mclk
......@@ -210,6 +213,7 @@ module memctrl16 #(
input want_rq2, // both want_rq and need_rq should go inactive after being granted
input need_rq2,
output reg channel_pgm_en2, // channel can program sequence data
input reject2, // reject grant
output seq_done2, // sequencer finished executing sequence for this channel
output page_nxt_chn2,
output buf_run2, // external buffer run (may be used to force page) @posedge mclk
......@@ -231,6 +235,7 @@ module memctrl16 #(
input want_rq3, // both want_rq and need_rq should go inactive after being granted
input need_rq3,
output reg channel_pgm_en3, // channel can program sequence data
input reject3, // reject grant
output seq_done3, // sequencer finished executing sequence for this channel
output page_nxt_chn3,
output buf_run3, // external buffer run (may be used to force page) @posedge mclk
......@@ -252,6 +257,7 @@ module memctrl16 #(
input want_rq4, // both want_rq and need_rq should go inactive after being granted
input need_rq4,
output reg channel_pgm_en4, // channel can program sequence data
input reject4, // reject grant
output seq_done4, // sequencer finished executing sequence for this channel
output page_nxt_chn4,
output buf_run4, // external buffer run (may be used to force page) @posedge mclk
......@@ -273,6 +279,7 @@ module memctrl16 #(
input want_rq5, // both want_rq and need_rq should go inactive after being granted
input need_rq5,
output reg channel_pgm_en5, // channel can program sequence data
input reject5, // reject grant
output seq_done5, // sequencer finished executing sequence for this channel
output page_nxt_chn5,
output buf_run5, // external buffer run (may be used to force page) @posedge mclk
......@@ -294,6 +301,7 @@ module memctrl16 #(
input want_rq6, // both want_rq and need_rq should go inactive after being granted
input need_rq6,
output reg channel_pgm_en6, // channel can program sequence data
input reject6, // reject grant
output seq_done6, // sequencer finished executing sequence for this channel
output page_nxt_chn6,
output buf_run6, // external buffer run (may be used to force page) @posedge mclk
......@@ -315,6 +323,7 @@ module memctrl16 #(
input want_rq7, // both want_rq and need_rq should go inactive after being granted
input need_rq7,
output reg channel_pgm_en7, // channel can program sequence data
input reject7, // reject grant
output seq_done7, // sequencer finished executing sequence for this channel
output page_nxt_chn7,
output buf_run7, // external buffer run (may be used to force page) @posedge mclk
......@@ -336,6 +345,7 @@ module memctrl16 #(
input want_rq8, // both want_rq and need_rq should go inactive after being granted
input need_rq8,
output reg channel_pgm_en8, // channel can program sequence data
input reject8, // reject grant
output seq_done8, // sequencer finished executing sequence for this channel
output page_nxt_chn8,
output buf_run8, // external buffer run (may be used to force page) @posedge mclk
......@@ -357,6 +367,7 @@ module memctrl16 #(
input want_rq9, // both want_rq and need_rq should go inactive after being granted
input need_rq9,
output reg channel_pgm_en9, // channel can program sequence data
input reject9, // reject grant
output seq_done9, // sequencer finished executing sequence for this channel
output page_nxt_chn9,
output buf_run9, // external buffer run (may be used to force page) @posedge mclk
......@@ -378,6 +389,7 @@ module memctrl16 #(
input want_rq10, // both want_rq and need_rq should go inactive after being granted
input need_rq10,
output reg channel_pgm_en10, // channel can program sequence data
input reject10, // reject grant
output seq_done10, // sequencer finished executing sequence for this channel
output page_nxt_chn10,
output buf_run10, // external buffer run (may be used to force page) @posedge mclk
......@@ -399,6 +411,7 @@ module memctrl16 #(
input want_rq11, // both want_rq and need_rq should go inactive after being granted
input need_rq11,
output reg channel_pgm_en11, // channel can program sequence data
input reject11, // reject grant
output seq_done11, // sequencer finished executing sequence for this channel
output page_nxt_chn11,
output buf_run11, // external buffer run (may be used to force page) @posedge mclk
......@@ -420,6 +433,7 @@ module memctrl16 #(
input want_rq12, // both want_rq and need_rq should go inactive after being granted
input need_rq12,
output reg channel_pgm_en12, // channel can program sequence data
input reject12, // reject grant
output seq_done12, // sequencer finished executing sequence for this channel
output page_nxt_chn12,
output buf_run12, // external buffer run (may be used to force page) @posedge mclk
......@@ -441,6 +455,7 @@ module memctrl16 #(
input want_rq13, // both want_rq and need_rq should go inactive after being granted
input need_rq13,
output reg channel_pgm_en13, // channel can program sequence data
input reject13, // reject grant
output seq_done13, // sequencer finished executing sequence for this channel
output page_nxt_chn13,
output buf_run13, // external buffer run (may be used to force page) @posedge mclk
......@@ -462,6 +477,7 @@ module memctrl16 #(
input want_rq14, // both want_rq and need_rq should go inactive after being granted
input need_rq14,
output reg channel_pgm_en14, // channel can program sequence data
input reject14, // reject grant
output seq_done14, // sequencer finished executing sequence for this channel
output page_nxt_chn14,
output buf_run14, // external buffer run (may be used to force page) @posedge mclk
......@@ -483,6 +499,7 @@ module memctrl16 #(
input want_rq15, // both want_rq and need_rq should go inactive after being granted
input need_rq15,
output reg channel_pgm_en15, // channel can program sequence data
input reject15, // reject grant
output seq_done15, // sequencer finished executing sequence for this channel
output page_nxt_chn15,
output buf_run15, // external buffer run (may be used to force page) @posedge mclk
......@@ -529,7 +546,7 @@ module memctrl16 #(
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here?
);
wire reject; // OR-ed reject from all channels
wire ext_buf_rd;
wire ext_buf_rpage_nxt;
wire ext_buf_page_nxt;
......@@ -779,12 +796,15 @@ assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !cmd_seq_run && (
assign pre_run_chn_w= pre_run_seq_w && !sel_refresh_w;
assign en_schedul= mcontr_enabled && !cmd_seq_fill && !cmd_seq_full;
reg reject_r;
// sequential logic for commands transfer to the sequencer
always @ (posedge mclk) begin
if (mrst) grant_r <= 0;
else grant_r <= grant;
if (mrst) reject_r <= 0;
else reject_r <= reject;
if (mrst) cmd_seq_set <= 0;
else if (grant_r) cmd_seq_set <= 0;
else if (seq_wr) cmd_seq_set <= 1;
......@@ -795,7 +815,7 @@ always @ (posedge mclk) begin
//TODO: Modify,cmd_seq_fill was initially used to see if any sequaence data was written (or PS is used), now it is cmd_seq_set
if (mrst) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full ) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full || reject_r) cmd_seq_fill <= 0;
else if (grant) cmd_seq_fill <= 1;
if (mrst) cmd_seq_full <= 0;
......@@ -886,6 +906,7 @@ end
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
......@@ -1457,5 +1478,58 @@ assign need_rq[15:0]= {need_rq15,need_rq14,need_rq13,need_rq12,need_rq11,need_
always @ (posedge mclk) channel_pgm_en15 <= grant && (grant_chn == 15);
`endif
// input reject0, // reject grant
assign reject = 1'b0
`ifdef def_enable_mem_chn0
|| reject0
`endif
`ifdef def_enable_mem_chn1
|| reject1
`endif
`ifdef def_enable_mem_chn2
|| reject2
`endif
`ifdef def_enable_mem_chn3
|| reject3
`endif
`ifdef def_enable_mem_chn4
|| reject4
`endif
`ifdef def_enable_mem_chn5
|| reject5
`endif
`ifdef def_enable_mem_chn6
|| reject6
`endif
`ifdef def_enable_mem_chn7
|| reject7
`endif
`ifdef def_enable_mem_chn8
|| reject8
`endif
`ifdef def_enable_mem_chn9
|| reject9
`endif
`ifdef def_enable_mem_chn10
|| reject10
`endif
`ifdef def_enable_mem_chn11
|| reject11
`endif
`ifdef def_enable_mem_chn12
|| reject12
`endif
`ifdef def_enable_mem_chn13
|| reject13
`endif
`ifdef def_enable_mem_chn14
|| reject14
`endif
`ifdef def_enable_mem_chn15
|| reject15
`endif
;
endmodule
memctrl/phy/byte_lane.v
View file @ 69b1d30b
......@@ -78,7 +78,27 @@ reg set_r=0;
reg dci_disable_dqs_r, dci_disable_dq_r;
reg [7:0] ld_odly=8'b0, ld_idly=8'b0;
reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
/*
wire iclk_int;
//BUFR iclk_int_i (.O(iclk_int), .I(dqs_read), .CLR(1'b0),.CE(1'b1));
assign iclk_int = dqs_read && !rst;
BUFIO iclk_i (.O(iclk), .I(iclk_int));
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M at N7 (IOB_X1Y120
since it belongs to a shape containing instance mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i.
The shape requires relative placement between
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M and
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i that cannnot be honored because it would result in
an invalid location for mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i. [x393.xdc:193]
----------
ERROR: [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/iclk_int,
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_int.
*/
wire [9:0] decode_sel={
(dly_addr[3:0]==9)?1'b1:1'b0,
(dly_addr[3:0]==8)?1'b1:1'b0,
......
memctrl/phy/mcontr_sequencer.v
View file @ 69b1d30b
......@@ -80,6 +80,7 @@ module mcontr_sequencer #(
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
......@@ -505,6 +506,7 @@ module mcontr_sequencer #(
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren (ren0), // input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen
// .ren (ren0 && !sequence_done), // input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen
.regen (ren0), // input
.data_out (phy_cmd0_word), // output[31:0]
.wclk (cmd0_clk), // input
......@@ -513,14 +515,19 @@ module mcontr_sequencer #(
.web (4'hf), // input[3:0]
.data_in (cmd0_data) // input[31:0]
);
// NOTE: Simulation sometimes may show:
// Memory Collision Error on RAMB36E1 : x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.RAMB36E1_i.genblk1.INT_RAMB_TDP.chk_for_col_msg
// It is OK, as the sequencer reads 2 extra (unused) locations before it stops at the end of block (stop depends on the read memory that has latency)
// Command sequence memory 0 ("manual"):
// Command sequence memory 1
ram_1kx32_1kx32 #(
.REGISTERS (1) // (0) // register output
) cmd1_buf_i (
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren ( ren1), // input ??? TODO: make cleaner ren/regen
// .ren ( ren1 && !sequence_done), // input ??? TODO: make cleaner ren/regen
.regen ( ren1), // input ???
.data_out (phy_cmd1_word), // output[31:0]
.wclk (cmd1_clk), // input
......@@ -545,9 +552,9 @@ module mcontr_sequencer #(
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE), /// debugging
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
......
memctrl/phy/phy_cmd.v
View file @ 69b1d30b
......@@ -36,6 +36,7 @@ module phy_cmd#(
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
......@@ -379,6 +380,7 @@ module phy_cmd#(
.CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
......
memctrl/phy/phy_top.v
View file @ 69b1d30b
......@@ -43,6 +43,7 @@ module phy_top #(
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
......@@ -312,6 +313,7 @@ wire sdclk; // BUFIO
// So shifting phase dynamically by plus/- 113 moves SDCLK by a full period (2.5ns) forward and backward (113= 0x71)
wire clk_pre, clk_div_pre, sdclk_pre, mclk_pre, clk_fb;
BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
//BUFIO clk_buf_i (.O(clk), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
//BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
......@@ -325,19 +327,21 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKOUT0_PHASE (SDCLK_PHASE),
.CLKOUT1_PHASE (CLK_PHASE),
.CLKOUT2_PHASE (CLK_DIV_PHASE),
.CLKOUT3_PHASE (MCLK_PHASE),
.CLKFBOUT_PHASE (CLKFBOUT_USE_FINE_PS? 0.0 : CLKFBOUT_PHASE),
.CLKOUT0_PHASE (CLKFBOUT_USE_FINE_PS? 0.0 : SDCLK_PHASE),
.CLKOUT1_PHASE (CLKFBOUT_USE_FINE_PS? CLK_PHASE : 0.0),
.CLKOUT2_PHASE (CLKFBOUT_USE_FINE_PS? CLK_DIV_PHASE : 0.0),
.CLKOUT3_PHASE (CLKFBOUT_USE_FINE_PS? MCLK_PHASE : 90.000), // (78.75), // (MCLK_PHASE), // should be multiple of 11.25 (90.000/8)
//ERROR: [DRC 23-20] Rule violation (AVAL-139) Phase shift check - The MMCME2_ADV cell mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i has a fractional CLKOUT3_PHASE value (75.000) with CLKOUT3_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKOUT3_DIVIDE] = [45 / 4] = 11.250.
// .CLKOUT4_PHASE (0.000),
// .CLKOUT5_PHASE (0.000),
// .CLKOUT6_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_USE_FINE_PS ("TRUE"),
.CLKOUT2_USE_FINE_PS ("TRUE"),
.CLKOUT3_USE_FINE_PS ("TRUE"),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
.CLKOUT0_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
.CLKOUT1_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
.CLKOUT2_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
.CLKOUT3_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
// .CLKOUT4_USE_FINE_PS("FALSE"),
// .CLKOUT5_USE_FINE_PS("FALSE"),
// .CLKOUT6_USE_FINE_PS("FALSE"),
......
py393/dbg/x393_mcntrl.pickle
View file @ 69b1d30b
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/import_verilog_parameters.py
View file @ 69b1d30b
......@@ -393,6 +393,11 @@ class ImportVerilogParameters(object):
# Try binary operation
# repeat until end of line or ')'
while True:
try:
opStart=skipWS(operand1[2])
except:
print("line=\n",line)
print("defines=\n",self.defines)
opStart=skipWS(operand1[2])
if (opStart == len(line)) : # or (line[opStart] == ')'): # just primary
return operand1
......@@ -485,7 +490,7 @@ class ImportVerilogParameters(object):
# Macro substitution excluding the very first character
if "`" in line [1:]:
for define in self.defines:
line.replace("`"+define,self.defines[define])
line = line.replace("`"+define,self.defines[define])
if line[0]== "`":
tokens=line[1:].replace("\t"," ").split(" ",1) #second tokens
for i in (1,2):
......
py393/vrlg.py
View file @ 69b1d30b
......@@ -144,12 +144,13 @@ CMPRS_CBIT_CMODE_MONO6__RAW = str
MCONTR_PHY_0BIT_DCI_RST = int
SENSOR_FIFO_2DEPTH = int
HIGH_PERFORMANCE_MODE__TYPE = str
PXD_CAPACITANCE__RAW = str
AFI_LO_ADDR64__TYPE = str
CAMSYNC_TRIG_DELAY2 = int
AFI_SIZE64 = int
LOGGER_CONF_IMU_BITS = int
SENS_JTAG_TCK__RAW = str
MCNTRL_SCANLINE_MASK__TYPE = str
HISPI_DIFF_TERM = str
MCONTR_PHY_0BIT_SDRST_ACT = int
SENSI2C_IBUF_LOW_PWR = str
CLKOUT_DIV_PCLK2X__RAW = str
......@@ -176,6 +177,7 @@ CLKFBOUT_PHASE_SENSOR = float
DFLT_REFRESH_PERIOD = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
NUM_CYCLES_20__TYPE = str
CMPRS_CSAT_CB__RAW = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
CMPRS_CBIT_RUN_BITS__TYPE = str
......@@ -243,6 +245,7 @@ SENSI2C_CMD_RUN_PBITS__TYPE = str
LOGGER_CONF_SYN_BITS__TYPE = str
GPIO_ADDR__TYPE = str
CAMSYNC_TRIG_SRC = int
SENS_CTRL_GP1__RAW = str
CLKOUT_DIV_PCLK__TYPE = str
LOGGER_PAGE_IMU = int
MEMCLK_IOSTANDARD__RAW = str
......@@ -297,6 +300,7 @@ MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
SENS_CTRL_RST_MMCM = int
LOGGER_CONF_EN_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
MAX_TILE_WIDTH__TYPE = str
SENS_LENS_POST_SCALE_MASK = int
BUF_IPCLK2X_SENS1__RAW = str
SENSOR_MODE_WIDTH__RAW = str
......@@ -309,6 +313,7 @@ CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_AFIMUX_MASK__TYPE = str
MCONTR_SENS_INC = int
CAMSYNC_TRIG_PERIOD__TYPE = str
CMPRS_STATUS_REG_BASE__RAW = str
DFLT_DQS_PATTERN = int
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
......@@ -335,7 +340,7 @@ DFLT_WBUF_DELAY__RAW = str
CAMSYNC_POST_MAGIC__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
NUM_CYCLES_24__RAW = str
NUM_CYCLES_13__RAW = str
SENS_REFCLK_FREQUENCY__TYPE = str
LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
LAST_FRAME_BITS__RAW = str
......@@ -367,6 +372,7 @@ MCONTR_CMPRS_STATUS_BASE = int
BUFFER_DEPTH32 = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
SENS_LENS_BX_MASK__TYPE = str
TEST01_SUSPEND__RAW = str
......@@ -374,6 +380,7 @@ SENS_GAMMA_HEIGHT01__TYPE = str
CMPRS_HIFREQ_REG_INC = int
STATUS_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
NUM_CYCLES_13__RAW = str
TEST01_START_FRAME = int
RTC_SET_USEC__RAW = str
LOGGER_CONF_SYN_BITS__RAW = str
......@@ -402,6 +409,7 @@ NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
CMDFRAMESEQ_REL__TYPE = str
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
NUM_CYCLES_LOW_BIT__TYPE = str
......@@ -421,9 +429,10 @@ CMPRS_CBIT_DCSUB_BITS__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
CAMSYNC_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str
CONTROL_ADDR__RAW = str
SENSI2C_CMD_RESET = int
TILED_STARTY__RAW = str
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
NUM_CYCLES_14__TYPE = str
......@@ -519,6 +528,7 @@ MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
HISTOGRAM_RADDR0__TYPE = str
LOGGER_CONF_SYN_BITS = int
NUM_CYCLES_19 = int
SENS_CTRL_GP1__TYPE = str
MCNTRL_TEST01_MASK__TYPE = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
SENSOR_FIFO_DELAY__RAW = str
......@@ -540,6 +550,7 @@ BUF_IPCLK_SENS1__TYPE = str
FFCLK0_IFD_DELAY_VALUE__TYPE = str
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
HISPI_IOSTANDARD__TYPE = str
CMPRS_AFIMUX_RST = int
NUM_CYCLES_18 = int
SENS_LENS_POST_SCALE_MASK__RAW = str
......@@ -555,10 +566,11 @@ CMPRS_CBIT_BAYER = int
GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
CLKFBOUT_DIV_REF__RAW = str
HISPI_DIFF_TERM__TYPE = str
SENSI2C_CMD_ACIVE_EARLY0 = int
CMD_PAUSE_BITS = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
SENSIO_STATUS_REG_REL = int
HISPI_IOSTANDARD__RAW = str
SENSI2C_TBL_SA__TYPE = str
BUF_IPCLK_SENS3__TYPE = str
MCNTRL_TILED_MODE = int
......@@ -589,6 +601,7 @@ SENSIO_RADDR__TYPE = str
CLKFBOUT_MULT_PCLK__TYPE = str
CLK_ADDR__TYPE = str
CMPRS_FORMAT = int
SENSIO_STATUS_REG_REL = int
FFCLK1_CAPACITANCE = str
CMPRS_CBIT_CMODE_BITS__RAW = str
CMPRS_TABLES = int
......@@ -597,7 +610,7 @@ CMPRS_AFIMUX_RADDR0__RAW = str
CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
SENS_REFCLK_FREQUENCY__TYPE = str
FFCLK1_DQS_BIAS__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
......@@ -669,7 +682,7 @@ SENS_LENS_FAT0_OUT_MASK__TYPE = str
SENSI2C_ABS_RADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
WBUF_DLY_WLV__TYPE = str
MEMBRIDGE_WIDTH64__TYPE = str
HISPI_MSB_FIRST__TYPE = str
MCONTR_TOP_16BIT_CHN_EN = int
BUF_IPCLK2X_SENS1__TYPE = str
DEFAULT_STATUS_MODE = int
......@@ -722,6 +735,7 @@ AXI_RD_ADDR_BITS__RAW = str
RTC_BITC_PREDIV = int
SENS_SS_MOD_PERIOD__TYPE = str
BUF_CLK1X_SYNC__RAW = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
MEMBRIDGE_LEN64__RAW = str
MCONTR_LINTILE_EN = int
......@@ -729,16 +743,19 @@ DFLT_REFRESH_ADDR__RAW = str
GPIO_N = int
MCONTR_ARBIT_ADDR_MASK__TYPE = str
SENS_CTRL_MRST__TYPE = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP1 = int
FFCLK0_IBUF_LOW_PWR__TYPE = str
FFCLK1_DQS_BIAS__TYPE = str
SENS_GAMMA_RADDR = int
NUM_CYCLES_14__RAW = str
CMPRS_AFIMUX_MASK__RAW = str
NUM_CYCLES_28__RAW = str
CLKIN_PERIOD_SENSOR__RAW = str
PHASE_WIDTH__TYPE = str
CMPRS_JP4__RAW = str
CMPRS_HIFREQ_REG_BASE__RAW = str
SS_MOD_PERIOD = int
MCONTR_CMPRS_BASE__TYPE = str
HISPI_CAPACITANCE__TYPE = str
TEST01_SUSPEND__TYPE = str
SENS_LENS_POST_SCALE = int
LOGGER_STATUS_REG_ADDR__TYPE = str
......@@ -758,11 +775,13 @@ PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MCNTRL_SCANLINE_MASK = int
CLKOUT_DIV_XCLK2X = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
CLKFBOUT_MULT__RAW = str
CMPRS_STATUS_REG_INC__RAW = str
HISTOGRAM_RADDR0__RAW = str
STATUS_ADDR_MASK = int
PXD_CAPACITANCE = str
SENS_LENS_AY = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
HISTOGRAM_RAM_MODE__RAW = str
......@@ -778,6 +797,7 @@ NEWPAR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
LOGGER_CONFIG__RAW = str
LD_DLY_LANE0_ODELAY__RAW = str
PXD_CLK_DIV_BITS__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMDSEQMUX_ADDR = int
CLKOUT_DIV_AXIHP = int
......@@ -828,6 +848,7 @@ SENSIO_CTRL__TYPE = str
SENSIO_WIDTH__RAW = str
CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
HISPI_IFD_DELAY_VALUE__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
CLKOUT_DIV_SYNC = int
SS_MODE__TYPE = str
......@@ -835,7 +856,9 @@ SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
T_RFC__TYPE = str
HISPI_IBUF_DELAY_VALUE__RAW = str
MCONTR_LINTILE_NRESET__TYPE = str
PXD_CLK_DIV__RAW = str
SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
BUF_IPCLK_SENS3__RAW = str
......@@ -843,15 +866,16 @@ CLK_STATUS__RAW = str
FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
MAX_TILE_WIDTH__TYPE = str
HISPI_DQS_BIAS__TYPE = str
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
REF_JITTER1 = float
CMPRS_CSAT_CB__TYPE = str
CMDSEQMUX_STATUS = int
TILE_WIDTH = int
GPIO_MASK = int
DLY_LANE0_ODELAY = long
NUM_XFER_BITS = int
HISPI_NUMLANES__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
DLY_DQS_ODELAY__TYPE = str
DLY_LANE0_ODELAY__RAW = str
......@@ -874,6 +898,7 @@ TEST_INITIAL_BURST__TYPE = str
NUM_CYCLES_19__RAW = str
MCNTRL_PS_MASK__RAW = str
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
MEMBRIDGE_LO_ADDR64__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
......@@ -904,7 +929,7 @@ LOGGER_MASK = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
WINDOW_Y0 = int
CAMSYNC_PRE_MAGIC__RAW = str
MCNTRL_TILED_TILE_WHS__TYPE = str
PXD_CLK_DIV_BITS = int
SENSOR_CHN_EN_BIT = int
LD_DLY_LANE0_ODELAY = int
FFCLK1_IBUF_DELAY_VALUE__RAW = str
......@@ -939,7 +964,7 @@ MCNTRL_TILED_WINDOW_WH = int
CMDFRAMESEQ_MASK = int
CLK_ADDR = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
SENS_CTRL_EXT_CLK__TYPE = str
NUM_XFER_BITS__RAW = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CBIT_RUN__RAW = str
......@@ -960,7 +985,7 @@ CMPRS_FRMT_MBRM1_BITS__TYPE = str
MCNTRL_TILED_TILE_WHS__RAW = str
SENS_REFCLK_FREQUENCY = float
CMD_PAUSE_BITS__TYPE = str
NUM_XFER_BITS__RAW = str
SENS_CTRL_EXT_CLK__TYPE = str
SENS_LENS_BY = int
SENS_LENS_BX = int
NUM_CYCLES_02__TYPE = str
......@@ -1005,11 +1030,14 @@ MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
BUF_CLK1X_XCLK2X__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
SENSI2C_TBL_NBRD__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
PXD_CLK_DIV_BITS__TYPE = str
MCONTR_CMPRS_INC__RAW = str
CMPRS_HIFREQ_REG_INC__RAW = str
PXD_CLK_DIV__TYPE = str
SENSOR_DATA_WIDTH__RAW = str
SENSI2C_TBL_DLY_BITS__TYPE = str
MEMBRIDGE_MASK = int
......@@ -1034,6 +1062,7 @@ ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
FFCLK1_IBUF_DELAY_VALUE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
MAX_TILE_WIDTH = int
NUM_CYCLES_09__TYPE = str
LD_DLY_LANE0_IDELAY__RAW = str
FRAME_WIDTH_BITS__TYPE = str
......@@ -1052,6 +1081,7 @@ MCNTRL_TILED_WINDOW_X0Y0 = int
MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
MULT_SAXI_WLOG__TYPE = str
STATUS_2LSB_SHFT = int
HISPI_IFD_DELAY_VALUE = str
CMPRS_CBIT_CMODE_JP4DC = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
......@@ -1077,7 +1107,7 @@ LOGGER_PAGE_GPS__RAW = str
SENS_PHASE_WIDTH__TYPE = str
CMPRS_COLOR18__TYPE = str
CMPRS_HIFREQ_REG_INC__TYPE = str
MCNTRL_TILED_CHN2_ADDR = int
PXD_CLK_DIV = int
MCNTRL_TILED_STATUS_CNTRL = int
NUM_CYCLES_29__RAW = str
GPIO_SET_STATUS__TYPE = str
......@@ -1104,9 +1134,10 @@ TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
CLK_STATUS_REG_ADDR = int
SENS_PCLK_PERIOD__RAW = str
CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
GPIO_SET_PINS = int
SENSOR_CHN_EN_BIT__TYPE = str
LOGGER_BIT_DURATION = int
......@@ -1120,11 +1151,13 @@ SENSI2C_CTRL_RADDR__TYPE = str
SENSIO_ADDR_MASK__RAW = str
LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int
PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str
HISPI_NUMLANES__TYPE = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
......@@ -1136,12 +1169,14 @@ LOGGER_PERIOD__TYPE = str
WSEL = int
SENS_REFCLK_FREQUENCY__RAW = str
LOGGER_STATUS_MASK__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
CMDFRAMESEQ_REL = int
CAMSYNC_POST_MAGIC__TYPE = str
NUM_CYCLES_29__TYPE = str
......@@ -1194,11 +1229,13 @@ CMPRS_CORING_BITS__TYPE = str
STATUS_DEPTH__TYPE = str
SENSI2C_TBL_RAH__TYPE = str
CMPRS_AFIMUX_CYCBITS__TYPE = str
HISPI_MSB_FIRST = int
SENS_SS_EN__RAW = str
SENS_LENS_ADDR_MASK = int
SENSOR_CTRL_RADDR__TYPE = str
CMPRS_CBIT_FRAMES_SINGLE__RAW = str
CLKOUT_DIV_PCLK = int
MCNTRL_SCANLINE_MASK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET__TYPE = str
PXD_IOSTANDARD__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR = int
......@@ -1261,6 +1298,7 @@ HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR3 = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
SENS_LENS_AY_MASK__TYPE = str
SENS_CTRL_IGNORE_EMBED__RAW = str
READ_BLOCK_OFFSET__TYPE = str
CONTROL_ADDR_MASK__RAW = str
LD_DLY_CMDA__RAW = str
......@@ -1270,6 +1308,7 @@ MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
MEMBRIDGE_WIDTH64__TYPE = str
MULT_SAXI_ADV_RD = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
DLY_PHASE__TYPE = str
......@@ -1303,7 +1342,7 @@ CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
TEST01_START_FRAME__TYPE = str
MCONTR_LINTILE_SKIP_LATE = int
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
RTC_SEC_USEC_ADDR__TYPE = str
......@@ -1322,6 +1361,7 @@ TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str
WSEL__RAW = str
CLKOUT_DIV_XCLK__TYPE = str
SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
NUM_CYCLES_00__TYPE = str
......@@ -1334,6 +1374,7 @@ HIGH_PERFORMANCE_MODE = str
DQTRI_LAST__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
CLKOUT_DIV_AXIHP__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
......@@ -1361,6 +1402,7 @@ MCONTR_WR_MASK = int
CMPRS_FRMT_MBCM1 = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str
CLKFBOUT_USE_FINE_PS__TYPE = str
CMPRS_FRMT_LMARG = int
FFCLK0_IBUF_DELAY_VALUE__TYPE = str
CMPRS_TIMEOUT__RAW = str
......@@ -1382,7 +1424,6 @@ SENSIO_CTRL = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
CLKIN_PERIOD_SYNC__RAW = str
SENS_PCLK_PERIOD = float
SCANLINE_STARTY__RAW = str
GPIO_ADDR = int
SENS_SYNC_MINBITS__RAW = str
......@@ -1390,7 +1431,7 @@ SENS_SS_MOD_PERIOD__RAW = str
COLADDR_NUMBER__TYPE = str
CAMSYNC_CHN_EN_BIT__RAW = str
LOGGER_PAGE_MSG = int
MCONTR_LINTILE_WRITE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str
SENSOR_FIFO_DELAY__TYPE = str
......@@ -1484,7 +1525,7 @@ SENSI2C_TBL_NBRD = int
CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
MULT_SAXI_STATUS_REG = int
CMPRS_STATUS_REG_BASE__RAW = str
CLKIN_PERIOD_SENSOR__TYPE = str
MEMCLK_IFD_DELAY_VALUE__RAW = str
SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str
......@@ -1531,11 +1572,11 @@ CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
RTC_MASK = int
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
HIST_SAXI_ADDR_REL__TYPE = str
LOGGER_CONFIG__TYPE = str
MCNTRL_TEST01_MASK = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
CMPRS_AFIMUX_EN__RAW = str
......@@ -1576,7 +1617,7 @@ CLKFBOUT_MULT_REF__RAW = str
DLY_LD_MASK__RAW = str
CMDFRAMESEQ_RST_BIT__TYPE = str
LD_DLY_LANE1_ODELAY = int
NUM_CYCLES_28__RAW = str
CMPRS_AFIMUX_MASK__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
......@@ -1585,6 +1626,7 @@ CLKFBOUT_DIV_REF = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
HISPI_IFD_DELAY_VALUE__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
......@@ -1600,7 +1642,7 @@ MCONTR_PHY_0BIT_CMDA_EN = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
MCNTRL_TEST01_CHN4_MODE = int
MAX_TILE_WIDTH = int
HISPI_DQS_BIAS = str
TABLE_FOCUS_INDEX = int
CMPRS_CBIT_RUN_STANDALONE__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
......@@ -1608,7 +1650,6 @@ DFLT_DQ_TRI_OFF_PATTERN__RAW = str
CMPRS_CBIT_DCSUB = int
CMPRS_CBIT_CMODE_JP4DIFF = int
MULT_SAXI_CNTRL_MASK__TYPE = str
SENS_PCLK_PERIOD__TYPE = str
INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
......@@ -1698,6 +1739,7 @@ DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
LOGGER_STATUS_MASK = int
DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str
CONTROL_ADDR_MASK = int
LOGGER_PERIOD = int
MCONTR_BUF0_WR_ADDR = int
......@@ -1709,6 +1751,7 @@ CMDFRAMESEQ_RUN_BIT__TYPE = str
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
SENSI2C_CTRL__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
SENS_CTRL_GP0__RAW = str
MCONTR_BUF2_WR_ADDR__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG1 = int
......@@ -1727,6 +1770,7 @@ MCNTRL_PS_MASK = int
SENSI2C_STATUS__TYPE = str
CMPRS_CSAT_CB_BITS = int
SENSI2C_TBL_NBRD__RAW = str
HISPI_IBUF_DELAY_VALUE = str
SENSI2C_IOSTANDARD = str
GPIO_IOSTANDARD = str
MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
......@@ -1734,7 +1778,7 @@ SENS_SYNC_MINPER__TYPE = str
SENSI2C_CTRL_RADDR__RAW = str
SENS_SYNC_LATE_DFLT__RAW = str
MCONTR_LINTILE_DIS_NEED__RAW = str
SENS_HIGH_PERFORMANCE_MODE = str
MCONTR_LINTILE_WRITE__TYPE = str
CAMSYNC_MASTER_BIT__RAW = str
MEMBRIDGE_STATUS_CNTRL = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
......@@ -1773,6 +1817,7 @@ SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
SS_MODE__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
......@@ -1836,7 +1881,7 @@ DFLT_REFRESH_PERIOD__RAW = str
SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
MAX_TILE_WIDTH__RAW = str
HISPI_DQS_BIAS__RAW = str
FFCLK1_DQS_BIAS = str
MCONTR_LINTILE_WRITE = int
TILE_VSTEP__TYPE = str
......@@ -1844,7 +1889,7 @@ MCONTR_PHY_STATUS_CNTRL__RAW = str
DLY_LANE0_DQS_WLV_IDELAY = long
MCNTRL_SCANLINE_STATUS_CNTRL = int
CMDSEQMUX_MASK__TYPE = str
TILED_STARTY__RAW = str
SENSI2C_CMD_RESET = int
SENSI2C_TBL_NABRD__TYPE = str
NUM_CYCLES_01__RAW = str
WINDOW_HEIGHT__RAW = str
......@@ -1854,6 +1899,7 @@ SENSI2C_CTRL_MASK = int
PHASE_CLK2X_PCLK__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
HISPI_IBUF_LOW_PWR = str
LOGGER_CONF_DBG__TYPE = str
AFI_SIZE64__RAW = str
SENSI2C_TBL_RNWREG = int
......@@ -1861,7 +1907,7 @@ STATUS_PSHIFTER_RDY_MASK = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENS_LENS_C_MASK__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
CMPRS_CSAT_CB__RAW = str
CLKFBOUT_DIV_REF__RAW = str
SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
......@@ -1870,6 +1916,7 @@ CMPRS_AFIMUX_MODE__TYPE = str
DQTRI_FIRST__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
CMPRS_CBIT_CMODE_BITS = int
TEST01_START_FRAME__TYPE = str
MULT_SAXI_CNTRL_ADDR__RAW = str
FFCLK1_IOSTANDARD__TYPE = str
CAMSYNC_TRIG_DELAY2__RAW = str
......@@ -1896,6 +1943,7 @@ SENS_HIGH_PERFORMANCE_MODE__TYPE = str
MCONTR_LINTILE_KEEP_OPEN__TYPE = str
NUM_CYCLES_15__RAW = str
DLY_DQ_IDELAY = long
CLKFBOUT_USE_FINE_PS = int
MCNTRL_TEST01_ADDR__TYPE = str
CMPRS_STATUS_REG_BASE = int
MCONTR_LINTILE_NRESET = int
......@@ -1912,7 +1960,7 @@ MCONTR_LINTILE_SINGLE__TYPE = str
DLY_DQ_IDELAY__RAW = str
SENSOR_CTRL_RADDR__RAW = str
CMPRS_MONO16 = int
CMPRS_CSAT_CB__TYPE = str
REF_JITTER1 = float
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
CLKIN_PERIOD_AXIHP__RAW = str
......@@ -1933,7 +1981,9 @@ SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_31__TYPE = str
HISPI_CAPACITANCE__RAW = str
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
HISPI_DIFF_TERM__RAW = str
BUF_IPCLK_SENS2__TYPE = str
SENS_GAMMA_BUFFER = int
CMDFRAMESEQ_ABS__TYPE = str
......@@ -2015,7 +2065,6 @@ LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
CLKOUT_DIV_AXIHP__RAW = str
CLK_DIV_PHASE__TYPE = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
......@@ -2041,8 +2090,8 @@ MCONTR_SENS_INC__RAW = str
MULT_SAXI_WLOG__RAW = str
TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
MCNTRL_TEST01_MASK = int
RTC_MASK = int
CLKIN_PERIOD_SENSOR = float
MEMCLK_IBUF_DELAY_VALUE__TYPE = str
SENS_GAMMA_CTRL__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
......@@ -2068,6 +2117,7 @@ SENS_GAMMA_MODE_EN__TYPE = str
FRAME_START_ADDRESS__TYPE = str
CLK_MASK = int
MCONTR_BUF4_WR_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR = int
CAMSYNC_MASK = int
COLADDR_NUMBER__RAW = str
STATUS_SEQ_SHFT = int
......@@ -2109,6 +2159,7 @@ MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str
GPIO_DRIVE = int
HISPI_MSB_FIRST__RAW = str
SENS_LENS_SCALES = int
CONTROL_ADDR_MASK__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
......
py393/x393_cmprs.py
View file @ 69b1d30b
......@@ -295,7 +295,7 @@ class X393Cmprs(object):
@param byte32 - 32-byte columns
@param tile_width tile width,
@param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sesnor channels - they can not wait
@param disable_need disable need (preference to sensor channels - they can not wait
"""
tile_vstep = 16
tile_height= 18
......
py393/x393_cmprs_afi.py
View file @ 69b1d30b
......@@ -102,7 +102,8 @@ class X393CmprsAfi(object):
channel,
cirbuf_start = 0x27a00000,
circbuf_len = 0x1000000,
verbose = 1):
verbose = 1,
num_lines_print = 20):
"""
Returns image metadata (start, length,timestamp) or null
@param port_afi - AFI port (0/1), currently only 0
......@@ -140,13 +141,13 @@ class X393CmprsAfi(object):
if img_start < 0:
img_start += circbuf_len
if verbose >0:
for a in range ( img_start, img_start + 0x10, 4):
for a in range ( img_start, img_start + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a)
if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
print("\n...",end="")
for a0 in range ( last_image_chunk - 0x10, last_image_chunk + 0x20, 4):
for a0 in range ( last_image_chunk - (0x10 * num_lines_print), last_image_chunk + 0x20, 4):
a = a0
if (a < 0):
a -=circbuf_len
......
py393/x393_jpeg.py
View file @ 69b1d30b
......@@ -820,6 +820,8 @@ ff d9
"""
"""
Camera compressors testing sequence
cd /usr/local/verilog/; test_mcntrl.py @hargs
#or (for debug)
cd /usr/local/verilog/; test_mcntrl.py @hargs -x -v
Next 2 lines needed to use jpeg functionality if the program was started w/o setup_all_sensors True None 0xf
......@@ -830,7 +832,7 @@ specify_window
measure_all "*DI"
# Run 'measure_all' again (but w/o arguments) to perform full calibration (~10 minutes) and save results.
# Needed after new bitstream
# setup_all_sensors , 3-rd argument - bitmask of sesnors to initialize
# setup_all_sensors , 3-rd argument - bitmask of sensors to initialize
setup_all_sensors True None 0xf
#reset all compressors - NOT NEEDED
......@@ -849,7 +851,7 @@ compressor_control all None None None None None 3
#Gamma 0.57
program_gamma all 0 0.57 0.04
program_gamma all 0 1.0 0.04
#colors - outdoor
write_sensor_i2c all 1 0 0x9035000a
write_sensor_i2c all 1 0 0x902c000e
......@@ -886,7 +888,24 @@ axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#run copmpressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
#color pattern:
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
write_sensor_i2c all 1 0 0x90a00001
write_sensor_i2c all 1 0 0x90a00009
write_sensor_i2c all 1 0 0x90a00019
#running 1:
write_sensor_i2c all 1 0 0x90a00029
...
write_sensor_i2c all 1 0 0x90a00041
#color pattern off:
write_sensor_i2c all 1 0 0x90a00000
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2
jpeg_write "img.jpeg" all
......@@ -898,6 +917,14 @@ compressor_control all 2
jpeg_write "img.jpeg" all 85
-----
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
program_gamma all 0 1.0 0.00
membridge_start
mem_dump 0x2ba00000 0x100
mem_save "/usr/local/verilog/sensor_dump_01" 0x2ba00000 0x2300000
#scp -p root@192.168.0.8:/mnt/mmc/local/verilog/sensor_dump_01 /home/andrey/git/x393/py393/dbg1
setup_membridge_sensor <write_mem=False> <cache_mode=3> <window_width=2592> <window_height=1944> <window_left=0> <window_top=0> <membridge_start=731906048> <membridge_end=768606208> <verbose=1>
setup_membridge_sensor 0 3 2608 1936
......@@ -905,7 +932,6 @@ setup_membridge_sensor <num_sensor=0> <write_mem=False> <cache_mode=3> <wind
setup_membridge_sensor 0 0 3 2608 1936
setup_membridge_sensor 1 0 3 2608 1936
# Trying quadrants @param quadrants - 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] (6'h01), None - no change
# set_sensor_io_ctl <num_sensor> <mrst=None> <arst=None> <aro=None> <mmcm_rst=None> <clk_sel=None> <set_delays=False> <quadrants=None>
......
py393/x393_mcntrl_adjust.py
View file @ 69b1d30b
......@@ -1361,6 +1361,8 @@ class X393McntrlAdjust(object):
y=a*phase+b
y0=y
#find the lowest approximate solution to consider
if (quiet <2):
print("phase= %d, y=%f, variantStep=%f"%(phase,y,variantStep))
if y0 > (-max_dly_err):
while (y0 >= (variantStep-max_dly_err)):
y0 -= variantStep
......@@ -1369,6 +1371,8 @@ class X393McntrlAdjust(object):
while (y0<(-max_dly_err)):
y0 += variantStep
periods += 1
if (quiet <2):
print("y0=%f"%(y0))
dly_min= max(0,int(y0-4.5))
dly_max= min(max_lin_dly,int(y0+5.5))
dly_to_try=[]
......
py393/x393_mcntrl_timing.py
View file @ 69b1d30b
......@@ -88,6 +88,12 @@ class X393McntrlTiming(object):
if phase is None:
phase= vrlg.get_default("DLY_PHASE")
vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1)
if vrlg.CLKFBOUT_USE_FINE_PS:
phase_value = (-vrlg.DLY_PHASE) & ((1<<vrlg.PHASE_WIDTH)-1)
if quiet<2:
print("SET INVERTED CLOCK PHASE=0x%x (actual value is 0x%x)"%(vrlg.DLY_PHASE, phase_value))
self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE, phase_value) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
else:
if quiet<2:
print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
......@@ -106,6 +112,9 @@ class X393McntrlTiming(object):
<wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)
Returns 1 if success, 0 if timeout
"""
if vrlg.CLKFBOUT_USE_FINE_PS:
patt = 0x3000000 | ((-vrlg.DLY_PHASE) & 0xff)
else:
patt = 0x3000000 | vrlg.DLY_PHASE
mask = 0x3000100
if check_phase_value:
......@@ -452,6 +461,9 @@ class X393McntrlTiming(object):
Wait until clock phase shifter is ready
"""
data=self.x393_axi_tasks.read_status(vrlg.MCONTR_PHY_STATUS_REG_ADDR)
expected_phase = vrlg.DLY_PHASE
if (vrlg.CLKFBOUT_USE_FINE_PS):
expected_phase = (-expected_phase) & 0xff;
while (((data & vrlg.STATUS_PSHIFTER_RDY_MASK) == 0) or (((data ^ vrlg.DLY_PHASE) & 0xff) != 0)):
data=self.x393_axi_tasks.read_status(vrlg.MCONTR_PHY_STATUS_REG_ADDR)
if self.DRY_MODE: break
......
py393/x393_sens_cmprs.py
View file @ 69b1d30b
......@@ -470,7 +470,7 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== GAMMA_CTL =========================")
self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sesnor data when everything else is set up
self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sensor data when everything else is set up
num_sensor = num_sensor, # input [1:0] num_sensor; # sensor channel number (0..3)
bayer = 0,
table_page = 0,
......
py393/x393_sensor.py
View file @ 69b1d30b
......@@ -892,14 +892,19 @@ class X393Sensor(object):
):
"""
@brief Calculate gamma table (as array of 257 unsigned short values)
@param gamma - gamma value (1.0 - linear)
@param gamma - gamma value (1.0 - linear), 0 - linear as a special case
@param black - black level, 1.0 corresponds to 256 for 8bit values
@return array of 257 int elements (for a single color), right-shifted to match original 0..0x3ff range
"""
gtable = []
if gamma <= 0: # special case
for i in range (257):
ig = min(i*256, 0xffff)
gtable.append(ig >> rshift)
else:
black256 = max(0.0, min(255, black * 256.0))
k= 1.0 / (256.0 - black256)
gamma =max(0.13, min(gamma, 10.0))
gtable = []
for i in range (257):
x=k * (i - black256)
x = max(x, 0.0)
......
sensor/pxd_single.v
View file @ 69b1d30b
......@@ -38,8 +38,8 @@ module pxd_single#(
output pxd_in, // data output (@posedge ipclk?)
input ipclk, // restored clock from the sensor, phase-shifted
input ipclk2x, // restored clock from the sensor, phase-shifted, twice frequency
input mrst, // reset @ posxedge mclk
input irst, // reset @ posxedge iclk
input mrst, // reset @ posedge mclk
input irst, // reset @ posedge iclk
input mclk, // clock for setting delay values
input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input set_idelay, // mclk synchronous load idelay value
......
sensor/sens_10398.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_10398
* Date:2015-10-15
* Author: andrey
* Description: Top level module for the 10398 SFE (with MT9F002 sensor)
*
* Copyright (c) 2015 Elphel, Inc .
* sens_10398.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_10398.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_10398 #(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
// 6 - delays, 7 - phase
parameter SENSIO_STATUS_REG = 'h21,
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
parameter SENS_CTRL_MRST= 0, // 1: 0
parameter SENS_CTRL_ARST= 2, // 3: 2
parameter SENS_CTRL_ARO= 4, // 5: 4
parameter SENS_CTRL_RST_MMCM= 6, // 7: 6
// parameter SENS_CTRL_EXT_CLK= 8, // 9: 8
parameter SENS_CTRL_IGNORE_EMBED = 8, // 9: 8
parameter SENS_CTRL_LD_DLY= 10, // 10
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
// parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
// parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
// parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT",
// Other (non-HiSPi) sensor I/Os
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT", // 1.8V single-ended
parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4
// ,parameter STATUS_ALIVE_WIDTH = 4
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
// delay control inputs
input mclk,
input mrst,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
input trigger_mode, // running in triggered mode (0 - free running mode)
input trig, // per-sensor trigger input
// I/O pads
input [HISPI_NUMLANES-1:0] sns_dp,
input [HISPI_NUMLANES-1:0] sns_dn,
input sns_clkp, // was TDO on 10359
input sns_clkn, // was TDI on 10359
output sens_ext_clk_p, // sns1_dp[6]
output sens_ext_clk_n, // sns1_dn[6] just to reduce EMI from the clock == gp[2]
inout sns_pgm, // (pullup) SENSPGM
output sns_ctl_tck, // unused on 10398 - TCK
output sns_mrst, // sns_dp[7]
output sns_arst_tms, // sns_dn[7] == gp[3] TMS
output sns_gp0_tdi, // sns_dp[5] == gp[0] TDI (differs from 10353)
output sns_gp1, // sns_dn[5] == gp[1]
input sns_flash_tdo, // sns_dp[4] TDO (differs from 10353)
input sns_shutter_done,// sns_dn[4] DONE (differs from 10353)
output [11:0] pxd,
output hact,
output sof, // @pclk
output eof // @pclk
);
reg [31:0] data_r;
// reg [3:0] set_idelay;
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
reg set_status_r;
reg set_jtag_r;
wire ps_rdy;
wire [7:0] ps_out;
wire locked_pxd_mmcm;
wire clkin_pxd_stopped_mmcm;
wire clkfb_pxd_stopped_mmcm;
// programmed resets to the sensor
reg iaro_soft = 0;
wire iaro;
reg iarst = 0;
reg imrst = 0; // active low
reg rst_mmcm=1; // rst and command - en/dis
reg ld_idelay=0;
reg ignore_embed=0; // do not process sensor data marked as "embedded"
wire [14:0] status;
wire cmd_we;
wire [2:0] cmd_a;
wire [31:0] cmd_data;
wire xfpgadone; // state of the MRST pin ("DONE" pin on external FPGA)
wire xfpgatdo; // TDO read from external FPGA
wire senspgmin;
reg xpgmen=0; // enable programming mode for external FPGA
reg xfpgaprog=0; // PROG_B to be sent to an external FPGA
reg xfpgatck=0; // TCK to be sent to external FPGA
reg xfpgatms=0; // TMS to be sent to external FPGA
reg xfpgatdi=0; // TDI to be sent to external FPGA
reg [1:0] gp_r; // sensor GP0, GP1. For now just software control, later use for something else
reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
assign status = { locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
assign iaro = trigger_mode? ~trig : iaro_soft;
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
always @(posedge mclk) begin
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_idelays <= 0;
else set_idelays <= cmd_we & (cmd_a==(SENSIO_DELAYS+2));
if (mrst) set_iclk_phase <= 0;
else set_iclk_phase <= cmd_we & (cmd_a==(SENSIO_DELAYS+3));
if (mrst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (mrst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (mrst) set_jtag_r <=0;
else set_jtag_r <= cmd_we && (cmd_a== SENSIO_JTAG);
if (mrst) xpgmen <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_PGMEN + 1]) xpgmen <= data_r[SENS_JTAG_PGMEN];
if (mrst) xfpgaprog <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_PROG + 1]) xfpgaprog <= data_r[SENS_JTAG_PROG];
if (mrst) xfpgatck <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TCK + 1]) xfpgatck <= data_r[SENS_JTAG_TCK];
if (mrst) xfpgatms <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TMS + 1]) xfpgatms <= data_r[SENS_JTAG_TMS];
if (mrst) xfpgatdi <= 0;
else if (set_jtag_r && data_r[SENS_JTAG_TDI + 1]) xfpgatdi <= data_r[SENS_JTAG_TDI];
if (mrst) imrst <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_MRST + 1]) imrst <= data_r[SENS_CTRL_MRST];
if (mrst) iarst <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_ARST + 1]) iarst <= data_r[SENS_CTRL_ARST];
if (mrst) iaro_soft <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_MRST + 1]) iaro_soft <= data_r[SENS_CTRL_ARO];
if (mrst) rst_mmcm <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_RST_MMCM + 1]) rst_mmcm <= data_r[SENS_CTRL_RST_MMCM];
if (mrst) ignore_embed <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_IGNORE_EMBED + 1]) ignore_embed <= data_r[SENS_CTRL_IGNORE_EMBED];
if (mrst) ld_idelay <= 0;
else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];
if (mrst) gp_r[0] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 1]) gp_r[0] <= data_r[SENS_CTRL_GP0];
if (mrst) gp_r[1] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 1]) gp_r[1] <= data_r[SENS_CTRL_GP1];
end
// generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
always @(posedge pclk) begin
if (prst || (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
else pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;
// treat MSB separately to make 50% duty cycle
if (prst) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= 0;
else if (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= ~pxd_clk_cntr[PXD_CLK_DIV_BITS-1];
end
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
// .status ({status_alive,status}), // input[25:0]
.status (status), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
sens_hispi12l4 #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi12l4_i (
.pclk (pclk), // input
.prst (prsts), //prst), // input
.sns_dp (sns_dp[3:0]), // input[3:0]
.sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd), // output[11:0] reg
.hact_out (hact), // output
.sof (sof), // output
.eof (eof), // output reg
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r), // input[31:0]
.set_idelay ({4{set_idelays}}), // input[3:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
.rst_mmcm (rst_mmcm), // input
.ignore_embedded (ignore_embed), // input
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pxd_mmcm), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
obufds #(
.CAPACITANCE("DONT_CARE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) obufds_i (
.o (sens_ext_clk_p), // output
.ob (sens_ext_clk_n), // output
.i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input
);
// Probe programmable/ control PROGRAM pin
reg [1:0] xpgmen_d;
reg force_senspgm=0;
// mpullup i_mrst_pullup(mrst);
mpullup i_senspgm_pullup (sns_pgm);
mpullup i_sns_shutter_done_pullup (sns_shutter_done);
always @ (posedge mclk) begin
if (mrst) force_senspgm <= 0;
else if (xpgmen_d[1:0]==2'b10) force_senspgm <= senspgmin;
if (mrst) xpgmen_d <= 0;
else xpgmen_d <= {xpgmen_d[0], xpgmen};
end
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) senspgm_i (
.O (senspgmin), // output -senspgm pin state
.IO (sns_pgm), // inout I/O pad
.I (xpgmen?(~xfpgaprog):force_senspgm), // input
.T (~(xpgmen || force_senspgm)) // input - disable when reading DONE
);
// generate ARO/TCK
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) aro_tck_i (
.O (sns_ctl_tck), // output
.I (xpgmen? xfpgatck : iaro) // input
);
// generate ARST/TMS
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_arst_tms_i (
.O (sns_arst_tms), // output
.I (xpgmen? xfpgatms : iarst) // input
);
// generate MRST
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_mrst_i (
.O (sns_mrst), // output
. I(imrst) // input
);
// generate GP0/TDI
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_gp0_tdi_i (
.O (sns_gp0_tdi), // output
.I (xpgmen? xfpgatdi : gp_r[0]) // input
);
// generate GP1
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_gp1_i (
.O (sns_gp1), // output
.I (gp_r[1]) // input
);
// READ TDO (and flash)
ibuf_ibufg #(
.CAPACITANCE (PXD_CAPACITANCE),
.IBUF_DELAY_VALUE ("0"),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IFD_DELAY_VALUE ("AUTO"),
.IOSTANDARD (PXD_IOSTANDARD)
) sns_flash_tdo_i (
.O(xfpgatdo), // output
.I(sns_flash_tdo) // input
);
// READ DONE (and shutter)
ibuf_ibufg #(
.CAPACITANCE (PXD_CAPACITANCE),
.IBUF_DELAY_VALUE ("0"),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IFD_DELAY_VALUE ("AUTO"),
.IOSTANDARD (PXD_IOSTANDARD)
) sns_shutter_done_i (
.O(xfpgadone), // output
.I(sns_shutter_done) // input
);
endmodule
sensor/sens_hispi12l4.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_hispi12l4
* Date:2015-10-13
* Author: andrey
* Description: Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor
*
* Copyright (c) 2015 Elphel, Inc .
* sens_hispi12l4.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_hispi12l4.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_hispi12l4#(
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT",
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst, // reset @pclk (add sensor reset here)
// I/O pads
input [HISPI_NUMLANES-1:0] sns_dp,
input [HISPI_NUMLANES-1:0] sns_dn,
input sns_clkp,
input sns_clkn,
// output
// output reg [11:0] pxd_out,
output [11:0] pxd_out,
// output reg vact_out,
output hact_out,
output sof, // @pclk
output reg eof, // @pclk
// delay control inputs
input mclk,
input mrst,
input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input set_clk_phase, // mclk synchronous set idealy value
input rst_mmcm,
input ignore_embedded, // ignore lines with embedded data
// input wait_all_lanes, // when 0 allow some lanes missing sync (for easier phase adjustment)
// MMCP output status
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
wire ipclk; // re-generated half HiSPi clock (165 MHz)
wire ipclk2x;// re-generated HiSPi clock (330 MHz)
wire [HISPI_NUMLANES * 4-1:0] sns_d;
localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
localparam FIFO_DEPTH = 4;
reg [HISPI_KEEP_IRST-1:0] irst_r;
wire irst = irst_r[0];
sens_hispi_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi_clock_i (
.mclk (mclk), // input
.mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input
.rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input
.ipclk (ipclk), // output
.ipclk2x (ipclk2x), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pxd_mmcm), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
sens_hispi_din #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi_din_i (
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (dly_data), // input[31:0]
.set_idelay (set_idelay), // input[3:0]
.ld_idelay (ld_idelay), // input
.ipclk (ipclk), // input
.ipclk2x (ipclk2x), // input
.irst (irst), // input
.din_p (sns_dp), // input[3:0]
.din_n (sns_dn), // input[3:0]
.dout (sns_d) // output[15:0]
);
wire [HISPI_NUMLANES * 12-1:0] hispi_aligned;
wire [HISPI_NUMLANES-1:0] hispi_dv;
wire [HISPI_NUMLANES-1:0] hispi_embed;
wire [HISPI_NUMLANES-1:0] hispi_sof;
wire [HISPI_NUMLANES-1:0] hispi_eof;
wire [HISPI_NUMLANES-1:0] hispi_sol;
wire [HISPI_NUMLANES-1:0] hispi_eol;
// TODO - try to make that something will be recorded even if some lanes are bad (to simplify phase adjust
// possibly - extra control bit (wait_all_lanes)
// use earliest SOF
reg vact_ipclk;
reg [1:0] vact_pclk_strt;
wire [HISPI_NUMLANES-1:0] rd_run;
reg rd_line; // combine all lanes
reg rd_line_r;
wire sol_all_dly;
reg [HISPI_NUMLANES-1:0] rd_run_d;
reg sof_pclk;
// wire [HISPI_NUMLANES-1:0] sol_pclk = rd_run & ~rd_run_d;
wire sol_pclk = |(rd_run & ~rd_run_d); // possibly multi-cycle
reg [HISPI_NUMLANES-1:0] good_lanes; // lanes that started active line OK
reg [HISPI_NUMLANES-1:0] fifo_re;
reg [HISPI_NUMLANES-1:0] fifo_re_r;
reg hact_r;
wire [HISPI_NUMLANES * 12-1:0] fifo_out;
wire hact_on;
wire hact_off;
reg ignore_embedded_ipclk;
reg [1:0] vact_pclk;
wire [11:0] pxd_out_pre = ({12 {fifo_re_r[0] & rd_run[0]}} & fifo_out[0 * 12 +:12]) |
({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) |
({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) |
({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]);
assign hact_out = hact_r;
assign sof = sof_pclk;
// async reset
always @ (posedge ipclk or posedge prst) begin
if (prst) irst_r <= {HISPI_KEEP_IRST{1'b1}}; // HISPI_KEEP_IRST-1
else irst_r <= irst_r >> 1;
end
always @(posedge ipclk) begin
// irst_r <= {irst_r[1:0], prst};
if (irst || (|hispi_eof)) vact_ipclk <= 0; // extend output if hact active
else if (|hispi_sof) vact_ipclk <= 1;
ignore_embedded_ipclk <= ignore_embedded;
end
always @(posedge pclk) begin
if (prst || !vact_ipclk) vact_pclk_strt <= 0;
else vact_pclk_strt <= {vact_pclk_strt[0], 1'b1};
rd_run_d <= rd_run;
sof_pclk <= vact_pclk_strt[0] && ! vact_pclk_strt[1];
if (prst || sof_pclk) rd_line <= 0;
else if (sol_pclk) rd_line <= 1;
else rd_line <= rd_line & (&(~good_lanes | rd_run)); // Off when first of the good lanes goes off
rd_line_r <= rd_line;
if (sol_pclk && !rd_line) good_lanes <= ~rd_run_d; // should be off before start
else if (sol_all_dly) good_lanes <= good_lanes & rd_run; // and now they should be on
fifo_re_r <= fifo_re & rd_run; // when data out is ready, mask if not running
// not using HISPI_NUMLANES here - fix? Will be 0 (not possible in hispi) when no data
/* pxd_out <= ({12 {fifo_re_r[0] & rd_run[0]}} & fifo_out[0 * 12 +:12]) |
({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) |
({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) |
({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]); */
if (prst) fifo_re <= 0;
else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else fifo_re <= fifo_re << 1;
// if (prst || (hact_off && (|(good_lanes & ~rd_run)))) hact_r <= 0;
if (prst || (hact_off && (!rd_line || (good_lanes[3] & ~rd_run[3])))) hact_r <= 0;
else if (hact_on) hact_r <= 1;
vact_pclk <= {vact_pclk[0],vact_pclk_strt [0] || hact_r};
eof <= vact_pclk[1] && !vact_pclk[0];
// vact_out <= vact_pclk_strt [0] || hact_r;
end
dly_16 #(
.WIDTH(1)
) dly_16_start_line_i (
.clk (pclk), // input
.rst (1'b0), // input
.dly (WAIT_ALL_LANES), // input[3:0]
.din (rd_line && !rd_line_r), // input[0:0]
.dout (sol_all_dly) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_hact_on_i (
.clk (pclk), // input
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h3), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (sol_pclk), // input[0:0]
.dout (hact_on) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_hact_off_i (
.clk (pclk), // input
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h0), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (fifo_re[HISPI_NUMLANES - 1]), // input[0:0]
.dout (hact_off) // output[0:0]
);
dly_16 #(
.WIDTH(12)
) dly_16_pxd_out_i (
.clk (pclk), // input
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
.dly (4'h0), // input[3:0]
// .dly (4'h1), // input[3:0]
.din (pxd_out_pre), // input[0:0]
.dout (pxd_out) // output[0:0]
);
generate
genvar i;
for (i=0; i < 4; i=i+1) begin: hispi_lane
sens_hispi_lane #(
.HISPI_MSB_FIRST(HISPI_MSB_FIRST)
) sens_hispi_lane_i (
.ipclk (ipclk), // input
.irst (irst), // input
.din (sns_d[4*i +: 4]), // input[3:0]
.dout (hispi_aligned[12*i +: 12]), // output[3:0] reg
.dv (hispi_dv[i]), // output reg
.embed (hispi_embed[i]), // output reg
.sof (hispi_sof[i]), // output reg
.eof (hispi_eof[i]), // output reg
.sol (hispi_sol[i]), // output reg
.eol (hispi_eol[i]) // output reg
);
sens_hispi_fifo #(
.COUNT_START (7),
.DATA_WIDTH (12),
.DATA_DEPTH (FIFO_DEPTH)
) sens_hispi_fifo_i (
.ipclk (ipclk), // input
.irst (irst), // input
.we (hispi_dv[i]), // input
.sol (hispi_sol[i] && !(hispi_embed[i] && ignore_embedded_ipclk)), // input
.eol (hispi_eol[i]), // input
.din (hispi_aligned[12*i +: 12]), // input[11:0]
.pclk (pclk), // input
.prst (prst), // input
.re (fifo_re[i]), // input
.dout (fifo_out[12*i +: 12]), // output[11:0] reg
.run (rd_run[i]) // output
);
end
endgenerate
endmodule
sensor/sens_hispi_clock.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_hispi_clock
* Date:2015-10-13
* Author: andrey
* Description: Recover iclk/iclk2x from the HiSPi differntial clock
*
* Copyright (c) 2015 Elphel, Inc .
* sens_hispi_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_hispi_clock.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_hispi_clock#(
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT"
)(
input mclk,
input mrst,
input [7:0] phase,
input set_phase,
input rst_mmcm,
input clp_p,
input clk_n,
output ipclk, // 165 MHz
output ipclk2x, // 330 MHz
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
wire ipclk_pre;
wire ipclk2x_pre; // output
wire clk_fb;
wire prst = mrst;
wire clk_in;
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_in), // output
.I (clp_p), // input
.IB (clk_n) // input
);
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor)
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (IPCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("TRUE"),
.CLKOUT1_USE_FINE_PS ("TRUE"),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR * 2), // 6 // 8.000),
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR ), // 3 // 4),
.COMPENSATION ("ZHOLD"),
.REF_JITTER1 (SENS_REF_JITTER1),
.REF_JITTER2 (SENS_REF_JITTER2),
.SS_EN (SENS_SS_EN),
.SS_MODE (SENS_SS_MODE),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STARTUP_WAIT ("FALSE")
) mmcm_phase_cntr_i (
.clkin1 (clk_in), // input
.clkin2 (1'b0), // input
.sel_clk2 (1'b0), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.psclk (mclk), // input
.ps_we (set_phase), // input
.ps_din (phase), // input[7:0]
.ps_ready (ps_rdy), // output
.ps_dout (ps_out), // output[7:0] reg
.clkout0 (ipclk_pre), // output
.clkout1 (ipclk2x_pre), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkout6(), // output
.clkout0b(), // output
.clkout1b(), // output
.clkout2b(), // output
.clkout3b(), // output
.clkfbout (clk_fb), // output
.clkfboutb(), // output
.locked (locked_pxd_mmcm),
.clkin_stopped (clkin_pxd_stopped_mmcm), // output
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
// output
);
generate
if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFIO") BUFIO clk1x_i (.O(ipclk), .I(ipclk_pre));
else assign ipclk = ipclk_pre;
endgenerate
generate
if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else assign ipclk2x = ipclk2x_pre;
endgenerate
endmodule
sensor/sens_hispi_din.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_hispi_din
* Date:2015-10-13
* Author: andrey
* Description: Input differential receivers for HiSPi lanes
*
* Copyright (c) 2015 Elphel, Inc .
* sens_hispi_din.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_hispi_din.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_hispi_din #(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT"
)(
input mclk,
input mrst,
input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input ipclk, // 165 MHz
input ipclk2x, // 330 MHz
input irst, // reset @posedge iclk
input [HISPI_NUMLANES-1:0] din_p,
input [HISPI_NUMLANES-1:0] din_n,
output [HISPI_NUMLANES * 4-1:0] dout
);
wire [HISPI_NUMLANES-1:0] din;
wire [HISPI_NUMLANES-1:0] din_dly;
generate
genvar i;
for (i=0; i < HISPI_NUMLANES; i=i+1) begin: din_block
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_idelay[i]),
.ld (ld_idelay),
.delay (dly_data[3 + 8*i +: 5]),
.data_in (din[i]),
.data_out (din_dly[i])
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN ("FALSE"),
.MSB_FIRST (1) // MSB is received first
) iserdes_pxd_i (
.iclk (ipclk2x), // source-synchronous clock
.oclk (ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div (ipclk), // oclk divided by 2, front aligned
.inv_clk_div (1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst (irst), // reset
.d_direct (1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly (din_dly[i]), // serial input from idelay
.dout (dout[4*i +:4]), // parallel data out
.comb_out() // output
);
end
endgenerate
endmodule
sensor/sens_hispi_fifo.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_hispi_fifo
* Date:2015-10-14
* Author: andrey
* Description: cross-clock FIFO with special handling of 'run' output
*
* Copyright (c) 2015 Elphel, Inc .
* sens_hispi_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_hispi_fifo.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_hispi_fifo#(
parameter COUNT_START = 7, // wait these many samples input before starting output
parameter DATA_WIDTH = 12,
parameter DATA_DEPTH = 4 // >=3
) (
input ipclk,
input irst,
input we,
input sol, // start of line - 1 cycle before dv
input eol, // end of line - last dv
input [DATA_WIDTH-1:0] din,
input pclk,
input prst,
input re,
output reg [DATA_WIDTH-1:0] dout, // valid next cycle after re
output run // has latency 1 after last re
);
reg [DATA_WIDTH-1:0] fifo_ram[0 : (1 << DATA_DEPTH) -1];
reg [DATA_DEPTH:0] wa;
reg [DATA_DEPTH:0] ra;
wire line_start_pclk;
reg line_run_ipclk;
reg line_run_pclk;
reg run_r;
assign run = run_r;
// TODO: generate early done by comparing ra with (wa-1) - separate counter
always @ (posedge ipclk) begin
if (irst ||sol) wa <= 0;
else if (we && line_run_ipclk) wa <= wa + 1;
if (we && line_run_ipclk) fifo_ram[wa[DATA_DEPTH-1:0]] <= din;
if (irst || eol) line_run_ipclk <= 0;
else if (sol) line_run_ipclk <= 1;
end
always @(posedge pclk) begin
line_run_pclk <= line_run_ipclk && (line_run_pclk || line_start_pclk);
if (prst) run_r <= 0;
else if (line_start_pclk) run_r <= 1;
else if (!line_run_pclk && (ra == wa)) run_r <= 0;
if (prst ||line_start_pclk) ra <= 0;
else if (re) ra <= ra + 1;
if (re) dout <= fifo_ram[ra[DATA_DEPTH-1:0]];
end
pulse_cross_clock #(
.EXTRA_DLY(0)
) pulse_cross_clock_line_start_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (pclk), // input
.in_pulse (we && (wa == COUNT_START)), // input
.out_pulse (line_start_pclk), // output
.busy() // output
);
endmodule
sensor/sens_hispi_lane.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_hispi_lane
* Date:2015-10-13
* Author: andrey
* Description: Decode a single lane of the HiSPi data assuming packetized-SP protocol
*
* Copyright (c) 2015 Elphel, Inc .
* sens_hispi_lane.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_hispi_lane.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_hispi_lane#(
parameter HISPI_MSB_FIRST = 0
)(
input ipclk, // half HiSPi recovered clock (165 MHz for 660 bps of MT9F002)
input irst, // reset sync to ipclk
input [3:0] din, // @posedge ipclk, din[3] came first
output reg [11:0] dout, // 12-bit data output
output reg dv, // data valid - continuous marks line
output reg embed, // valid @sol and up through all dv
output reg sof, // always before first sol - not instead of
output reg eof, // always after last eol (not instead of)
output reg sol, // start of line - 1 cycle before dv
output reg eol // end of line - last dv
);
localparam [3:0] SYNC_SOF = HISPI_MSB_FIRST ? 4'h3 : 4'hc;
localparam [3:0] SYNC_SOL = HISPI_MSB_FIRST ? 4'h1 : 4'h8;
localparam [3:0] SYNC_EOF = HISPI_MSB_FIRST ? 4'h7 : 4'he;
// localparam [3:0] SYNC_EOL = 6;
localparam [3:0] SYNC_EMBED = HISPI_MSB_FIRST ? 4'h1 : 4'h8; // other nibble (bit 4)
localparam LSB_INDEX = HISPI_MSB_FIRST ? 2 : 0; // nibble number in 12-bit word
localparam MSB_INDEX = HISPI_MSB_FIRST ? 0 : 2; // nibble number in 12-bit word
reg [3:0] d_r; // rehistered input data
wire [2:0] num_trail_0_w; // number of trailing 0-s in the last nibble
wire [2:0] num_lead_0_w; // number of leading 0-s in the last nibble
wire [2:0] num_trail_1_w; // number of trailing 1-s in the last nibble
wire [2:0] num_lead_1_w; // number of leading 1-s in the last nibble
wire zero_after_ones_w;
reg [3:0] num_running_ones;
reg [4:0] num_running_zeros; // after sufficient ones
reg prev4ones; // previous data nibble was 4'hf
reg [1:0] num_first_zeros; // number of zeros in a first nibble after all ones
reg [1:0] shift_val; // barrel shifter select (0 is 4!)
wire got_sync_w = !num_running_zeros[3] && (&num_running_zeros_w[4:3]);
reg got_sync; // Got 24 zeros after >=16 1-s
reg [3:0] barrel;
reg [3:0] sync_decode; // 1-hot decoding of the last sync word
reg got_sof;
reg got_eof;
reg got_sol;
// reg got_eol;
reg got_embed;
reg [2:0] pre_dv;
wire [3:0] dout_w;
wire [4:0] num_running_zeros_w = num_running_zeros + {1'b0, num_lead_0_w};
wire start_line = sync_decode[3] && (got_sol || got_sof);
wire start_line_d; // delayed just to turn on pre_dv;
assign num_trail_0_w = (|din) ? ((|din[2:0]) ? ((|din[1:0]) ? (din[0] ? 3'h0 : 3'h1) : 3'h2) : 3'h3) : 3'h4;
assign num_lead_0_w = (|din) ? ((|din[3:1]) ? ((|din[3:2]) ? (din[3] ? 3'h0 : 3'h1) : 3'h2) : 3'h3) : 3'h4;
assign num_trail_1_w = (&din) ? 3'h4 : ((&din[2:0]) ? 3'h3 : ((&din[1:0]) ? 3'h2 :((&din[0]) ? 3'h1 : 3'h0)));
assign num_lead_1_w = (&din) ? 3'h4 : ((&din[3:1]) ? 3'h3 : ((&din[3:2]) ? 3'h2 :((&din[3]) ? 3'h1 : 3'h0)));
// assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (d_r[3] && !din[0]));
assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (din[3] && !d_r[0]));
always @(posedge ipclk) begin
d_r <= din;
prev4ones <= num_trail_1_w[2];
if (prev4ones && !num_trail_1_w[2]) num_first_zeros <= num_trail_0_w[1:0]; // 4 will be 0
// first stage - get at least 12 consecutive 1-s, expecting many consecutive 0-s after, so any
// 1 after zero should restart counting.
if (irst) num_running_ones <= 0;
else if ((num_running_ones == 0) || !zero_after_ones_w) num_running_ones <= {1'b0,num_trail_1_w};
// keep number of running 1-s saturated to 12 (to prevent roll over). Temporary there could be 13..15
// When running 1-s turn to running zeros, the count will not reset and stay on through counting
// of 0-s (will only reset by 1 after 0)
else num_running_ones <= (&num_running_ones[3:2]) ? 4'hc :
(num_running_ones + {1'b0, num_lead_1_w});
// Now count consecutive 0-s after (>=12) 1-s. Not using zero_after_ones in the middle of the run - will
// rely on the number of running ones being reset in that case
// Saturate number with 24 (5'h18), but only first transition from <24 to >=24 is used for sync
// detection.
if (irst || !num_running_ones[3]) num_running_zeros <= 0;
// else if (!num_running_ones[2]) num_running_zeros <= {2'b0,num_trail_0_w};
else if (prev4ones) num_running_zeros <= {2'b0,num_trail_0_w};
else num_running_zeros <= (&num_running_zeros[4:3])? 5'h18 : num_running_zeros_w;
if (irst) got_sync <= 0;
else got_sync <= got_sync_w;
// got_sync should also abort data run - delayed by 10 clocks
if (irst) shift_val <= 0;
// else if (got_sync) shift_val <= num_first_zeros;
else if (got_sync_w) shift_val <= num_first_zeros;
case (shift_val)
2'h0: barrel <= din;
// 2'h1: barrel <= {d_r[2:0], din[3]};
2'h1: barrel <= {d_r[0], din[3:1]};
2'h2: barrel <= {d_r[1:0], din[3:2]};
// 2'h3: barrel <= {d_r[0], din[3:1]};
2'h3: barrel <= {d_r[2:0], din[3]};
endcase
if (irst) sync_decode <= 0;
else if (got_sync) sync_decode <= 4'h1;
else sync_decode <= sync_decode << 1;
if (got_sync) got_sof <= 0;
else if (sync_decode[LSB_INDEX] && (barrel == SYNC_SOF)) got_sof <= 1;
if (got_sync) got_eof <= 0;
else if (sync_decode[LSB_INDEX] && (barrel == SYNC_EOF)) got_eof <= 1;
if (got_sync) got_sol <= 0;
else if (sync_decode[LSB_INDEX] && (barrel == SYNC_SOL)) got_sol <= 1;
// if (got_sync) got_eol <= 0;
// else if (sync_decode[LSB_INDEX] && (barrel == SYNC_EOL)) got_eol <= 1;
if (got_sync) got_embed <= 0;
else if (sync_decode[1] && (barrel == SYNC_EMBED)) got_embed <= 1;
if (irst) dout[ 3:0] <= 0;
else if (pre_dv[LSB_INDEX]) dout[ 3:0] <= dout_w;
if (irst) dout[ 7:4] <= 0;
else if (pre_dv[1]) dout[ 7:4] <= dout_w;
if (irst) dout[11:8] <= 0;
else if (pre_dv[MSB_INDEX]) dout[11:8] <= dout_w;
if (irst || got_sync) pre_dv <= 0;
else if (start_line_d) pre_dv <= 1;
else pre_dv <= {pre_dv[1:0],pre_dv[2]};
if (irst) dv <= 0;
else dv <= pre_dv[2];
if (irst) sol <= 0;
else sol <= start_line_d;
if (irst) eol <= 0;
else eol <= got_sync && (|pre_dv);
if (irst) sof <= 0;
else sof <= sync_decode[3] && got_sof;
if (irst) eof <= 0;
else eof <= sync_decode[3] && got_eof;
if (irst) embed <= 0;
else if (sync_decode[3]) embed <= got_embed && (got_sof || got_sol);
end
dly_16 #(
.WIDTH(4)
) dly_16_dout_i (
.clk (ipclk), // input
.rst (1'b0), // input
.dly (4'h8), // input[3:0]
.din (HISPI_MSB_FIRST ? barrel :{barrel[0],barrel[1],barrel[2],barrel[3]}), // input[0:0]
.dout (dout_w) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_pre_start_line_i (
.clk (ipclk), // input
.rst (1'b0), // input
.dly (4'h7), // input[3:0]
.din (start_line), // input[0:0]
.dout (start_line_d) // output[0:0]
);
endmodule
sensor/sens_histogram.v
View file @ 69b1d30b
......@@ -19,9 +19,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
// TODO: get rid of pclk2x by doubling memories (making 1 write port and 2 read ones)
// How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
module sens_histogram #(
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter HISTOGRAM_ADDR = 'h33c,
parameter HISTOGRAM_ADDR_MASK = 'h7fe,
parameter HISTOGRAM_LEFT_TOP = 'h0,
......@@ -32,7 +35,6 @@ module sens_histogram #(
`endif
)(
// input rst,
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
......@@ -52,16 +54,12 @@ module sens_histogram #(
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware
// ,output debug_mclk
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
input debug_di // input from the debug ring
`endif
);
`ifdef DEBUG_RING
// assign debug_do = debug_di;
`endif
localparam PXD_2X_LATENCY = 2;
reg hist_bank_pclk;
......@@ -137,11 +135,10 @@ module sens_histogram #(
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
// reg debug_vert_woi_r;
`ifdef DEBUG_RING
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
`endif
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
......@@ -176,16 +173,14 @@ module sens_histogram #(
reg monochrome_pclk;
reg monochrome_2x;
// assign debug_mclk = hist_done_mclk;
// assign debug_mclk = set_width_height_w;
`ifdef DEBUG_RING
always @ (posedge pclk) begin
if (sof) debug_line_cntr <= 0;
else if (line_start_w) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
end
`endif
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
......@@ -212,7 +207,6 @@ module sens_histogram #(
end
// process WOI
// wire eol = !hact && hact_d[0];
always @ (posedge pclk) begin
hact_d <= {hact_d[0],hact};
if (!en) pre_first_line <= 0;
......@@ -226,9 +220,6 @@ module sens_histogram #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
// debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;
// hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0;
......@@ -250,8 +241,6 @@ module sens_histogram #(
else if (hcntr_zero_w && left_margin) hcntr <= width_m1;
else if (left_margin || hor_woi) hcntr <= hcntr - 1;
// if (hor_woi) hist_d <= hist_di;
if (!en) hist_bank_pclk <= 0;
else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;
// hist_xfer_busy to extend en
......@@ -276,13 +265,11 @@ module sens_histogram #(
else if (!hact) bayer_pclk[0] <= XOR_HIST_BAYER[0];
else bayer_pclk[0] <= ~bayer_pclk[0];
//line_start_w
end
always @(posedge pclk2x) begin
monochrome_2x <= monochrome;
hist_en_pclk2x <= hist_en;
// hist_rst_pclk2x <= hist_rst;
pxd_ra_start <= left[3:0];
if (!hist_en_pclk2x || hlstart || !(hor_woi_2x || (|woi))) pclk_sync <= 0;
......@@ -303,8 +290,6 @@ module sens_histogram #(
hist_addr_d2 <= hist_addr_d;
same_addr1 <= monochrome_2x && woi[0] && woi[1] && (hist_addr_d == hist_addr); // reduce hardware if hard-wire to gnd
same_addr2 <= woi[0] && woi[2] && (hist_addr_d2 == hist_addr);
// if (same_addr) to_inc <= inc_r;
// else to_inc <= hist_new;
if (same_addr1) to_inc <= inc_r; // only used in monochrome mode
else if (same_addr2) to_inc <= inc_sat;
else to_inc <= hist_new;
......@@ -314,7 +299,6 @@ module sens_histogram #(
else inc_sat <= {14'b0,inc_r[17:0]};
end
hist_rwen <= (woi[0] & ~pclk_sync) || (woi[2] & pclk_sync);
// hist_regen <= {hist_regen[1:0], woi[0] & ~pclk_sync};
hist_regen <= {hist_regen[0], woi[0] & ~pclk_sync};
hist_we <= woi[2] & pclk_sync;
......@@ -323,35 +307,25 @@ module sens_histogram #(
inc_r <= to_inc + 1;
// if (HISTOGRAM_RAM_MODE != "BUF18") inc_r <= inc_w;
// else if (inc_w[18]) inc_r <= 32'h3fff; // maximal value
// else inc_r <= {14'b0,inc_w[17:0]};
end
// after hist_out was off, require inactive grant before sending rq
reg en_rq_start;
always @ (posedge mclk) begin
en_mclk <= en;
monochrome_pclk <= monochrome;
// monochrome_pclk <= monochrome;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
hist_out_d <= hist_out;
// reset address each time new transfer is started
// if (!en_mclk || (hist_out && !hist_out_d)) hist_raddr <= 0;
if (!hist_out) hist_raddr <= 0;
else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
// if (!en_mclk) hist_rq_r <= 0;
// else if (hist_out && !hist_re) hist_rq_r <= 1;
// hist_rq_r <= en_mclk && hist_out && !(&hist_raddr);
// prevent starting rq if grant is still on (back-to-back)
if (!hist_out) en_rq_start <= 0;
else if (!hist_grant) en_rq_start <= 1;
// hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && ((|hist_raddr[9:0]) || !hist_grant);
hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
if (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;
......@@ -369,6 +343,7 @@ module sens_histogram #(
else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1;
else if (hist_xfer_done) wait_readout <= 0;
monochrome_pclk <= monochrome;
end
`ifdef DEBUG_RING
......@@ -383,27 +358,12 @@ module sens_histogram #(
.debug_di (debug_di), // input
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
// .rd_data ({height_m1[15:0], vcntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.rd_data ({debug_lines[15:0], debug_line_cntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
//debug_lines <= debug_line_cntr
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
`endif
/*
pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (vert_woi && !debug_vert_woi_r), // line_start_w), // input vcntr_zero_w
// .in_pulse (vcntr_zero_w && !debug_vert_woi_r), // line_start_w), // input
.in_pulse (vcntr_zero_w && vert_woi && !debug_vert_woi_r), // line_start_w), // input
.out_pulse (debug_mclk), // output
.busy() // output
);
*/
cmd_deser #(
.ADDR (HISTOGRAM_ADDR),
.ADDR_MASK (HISTOGRAM_ADDR_MASK),
......@@ -471,13 +431,6 @@ module sens_histogram #(
.out_pulse (hist_xfer_done), // output
.busy() // output
);
/*
clk_to_clk2x clk_to_clk2x_i (
.clk (pclk), // input
.clk2x (pclk2x), // input
.clk_sync (pclk_sync) // output
);
*/
//TODO: make it double cycle in timing
// select between 18-bit wide histogram data using a single BRAM or 2 BRAMs having full 32 bits
......
sensor/sens_histogram_snglclk.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sens_histogram_snglclk
* Date:2015-10-21
* Author: Andrey Filippov
* Description: Calculates per-color histogram over the specified rectangular region.
* Modified from the original sens_histogram to avoid using double
* frequency clock
*
* Copyright (c) 2015 Elphel, Inc.
* sens_histogram_snglclk.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_histogram_snglclk.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_histogram_snglclk #(
parameter HISTOGRAM_RAM_MODE = "BUF32", // valid: "NOBUF" (32-bits, no buffering - now is replaced by BUF32), "BUF18", "BUF32"
parameter HISTOGRAM_ADDR = 'h33c,
parameter HISTOGRAM_ADDR_MASK = 'h7fe,
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00// 11 // invert bayer setting
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 // SuppressThisWarning VEditor - not used
`endif
)(
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
// input pclk2x,
input sof,
input eof,
input hact,
input [7:0] hist_di, // 8-bit pixel data
input mclk,
input hist_en, // @mclk - gracefully enable/disable histogram
input hist_rst, // @mclk - immediately disable if true
output hist_rq,
input hist_grant,
output [31:0] hist_do,
output reg hist_dv,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb // strobe (with first byte) for the command a/d
// , input monochrome // NOT supported in this implementation - use software to sum
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
input debug_di // input from the debug ring
`endif
);
localparam HIST_WIDTH = (HISTOGRAM_RAM_MODE == "BUF18") ? 18 : 32;
reg hist_bank_pclk;
reg [8:0] hist_rwaddr_even; // {bayer[1], pixel}
reg [8:0] hist_rwaddr_odd; // {bayer[1], pixel}
reg hist_bank_mclk;
wire set_left_top_w;
wire set_width_height_w;
wire [1:0] pio_addr;
wire [31:0] pio_data;
wire pio_stb;
reg [31:0] lt_mclk; // left+top @ posedge mclk
reg [31:0] wh_mclk; // width+height @ posedge mclk
reg [15:0] width_m1; // @posedge pclk
reg [15:0] height_m1; // @posedge pclk
reg [15:0] left; // @posedge pclk
reg [15:0] top; // @posedge pclk
reg hist_en_pclk; // @pclk - gracefully enable/disable histogram
reg hist_rst_pclk; // @pclk - immediately disable if true
reg en;
reg en_new; // @ pclk - enable new frame
reg en_mclk;
wire set_left_top_pclk;
wire set_width_height_pclk;
// reg pclk_sync; // CE for pclk2x, ~=pclk
reg odd_pix;
reg [1:0] bayer_pclk;
reg [1:0] hact_d;
reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle
wire hist_done_mclk;
reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window
// reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
reg [6:0] hor_woi; // vertically in window and delayed
reg [15:0] vcntr; // vertical (line) counter
reg [15:0] hcntr; // horizontal (pixel) counter
wire vcntr_zero_w; // vertical counter is zero
wire hcntr_zero_w; // horizontal counter is zero
reg hist_out; // some data yet to be sent out
reg hist_out_d;
reg [2:0] hist_re;
reg hist_re_even;
reg hist_re_odd;
reg [9:0] hist_raddr;
reg hist_rq_r;
wire hist_xfer_done_mclk; //@ mclk
wire hist_xfer_done; // @pclk
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
`ifdef DEBUG_RING
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
`endif
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
assign vcntr_zero_w = !(|vcntr);
assign hcntr_zero_w = !(|hcntr);
assign hist_rq = hist_rq_r;
assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en;
wire line_start_w = hact && !hact_d[0]; // // tested active
reg pre_first_line;
reg frame_active; // until done
`ifdef DEBUG_RING
always @ (posedge pclk) begin
if (sof) debug_line_cntr <= 0;
else if (line_start_w) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
end
`endif
always @ (posedge mclk) begin
if (set_left_top_w) lt_mclk <= pio_data;
if (set_width_height_w) wh_mclk <= pio_data;
end
always @ (posedge pclk) begin
if (set_left_top_pclk) {top,left} <= lt_mclk[31:0];
if (set_width_height_pclk) {height_m1,width_m1} <= wh_mclk[31:0];
end
// process WOI
always @ (posedge pclk) begin
hact_d <= {hact_d[0],hact};
if (!en) pre_first_line <= 0;
else if (sof && en_new) pre_first_line <= 1;
else if (hact) pre_first_line <= 0;
if (!en) top_margin <= 0;
else if (sof && en_new) top_margin <= 1;
else if (vcntr_zero_w & line_start_w) top_margin <= 0;
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0;
else if (sof && en_new) frame_active <= 1;
if ((pre_first_line && !hact) || !frame_active) vcntr <= top;
else if (line_start_w) vcntr <= vcntr_zero_w ? height_m1 : (vcntr - 1);
if (!frame_active) left_margin <= 0;
else if (!hact_d[0]) left_margin <= 1;
else if (hcntr_zero_w) left_margin <= 0;
// !hact_d[0] to limit by right margin if window is set wrong
if (!vert_woi || wait_readout || !hact_d[0]) hor_woi[0] <= 0; // postpone WOI if reading out/erasing histogram (no-buffer mode)
else if (hcntr_zero_w) hor_woi[0] <= left_margin && vert_woi;
hor_woi[6:1] <= hor_woi[5:0];
if (!hact_d[0]) hcntr <= left;
else if (hcntr_zero_w && left_margin) hcntr <= width_m1;
else if (left_margin || hor_woi[0]) hcntr <= hcntr - 1;
if (!en) hist_bank_pclk <= 0;
//else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;// NOT applicable in this module
else if (hist_done) hist_bank_pclk <= !hist_bank_pclk;
// hist_xfer_busy to extend en
if (!en) hist_xfer_busy <= 0;
else if (hist_xfer_done) hist_xfer_busy <= 0;
else if (vcntr_zero_w && vert_woi) hist_xfer_busy <= 1;
hist_en_pclk <= hist_en;
hist_rst_pclk <= hist_rst;
if (hist_rst_pclk) en <= 0;
else if (hist_en_pclk) en <= 1;
else if (!top_margin && !vert_woi && !hist_xfer_busy) en <= 0;
en_new <= !hist_rst_pclk && hist_en_pclk;
if (!hact && hact_d[0]) bayer_pclk[1] <= !bayer_pclk[1];
else if (pre_first_line && !hact) bayer_pclk[1] <= XOR_HIST_BAYER[1];
if (!hact) bayer_pclk[0] <= XOR_HIST_BAYER[0];
else bayer_pclk[0] <= ~bayer_pclk[0];
end
// assign hlstart = hcntr_zero_w && left_margin && hact_d[0];
reg [6:0] memen_even;
reg [6:0] memen_odd;
wire set_ra_even = memen_even[0];
wire regen_even = memen_even[2];
wire set_wa_even = memen_even[5];
wire we_even = memen_even[6];
wire set_ra_odd = memen_odd[0];
wire regen_odd = memen_odd[2];
wire set_wa_odd = memen_odd[5];
wire we_odd = memen_odd[6];
reg rwen_even; // re or we
reg rwen_odd; // re or we
wire [7:0] px_d0; // px delayed to match hor_woi (2 cycles)
wire [7:0] px_d2; // px delayed by 2 cycles from px_d0
wire [7:0] px_d4; // px delayed by 2 cycles from px_d2
wire [7:0] px_d5; // px delayed by 1 cycle from px_d4
reg [HIST_WIDTH -1 :0] r0;
reg [HIST_WIDTH -1 :0] r1;
reg r1_sat; // only used in 18-bit mode
reg [HIST_WIDTH -1 :0] r2;
reg [HIST_WIDTH -1 :0] r3;
wire [HIST_WIDTH -1 :0] hist_new_even; // data (to increment) read from the histogram memory, even pixels
wire [HIST_WIDTH -1 :0] hist_new_odd; // data (to increment) read from the histogram memory, odd pixels
reg [3:0] r_load; // load r0-r1-r2-r3 registers
reg r0_sel; // select odd/even for r0 (other option possible)
reg eq_prev_prev; // pixel equals one before previous of the same color
wire eq_prev_prev_d2; // eq_prev_prev delayed by 2 clocks to select r1 source
reg eq_prev; // pixel equals previous of the same color
wire eq_prev_d3; // eq_prev delayed by 3 clocks to select r1 source
// wire start_hor_woi = hcntr_zero_w && left_margin && vert_woi;
// hist_di is 2 cycles ahead of hor_woi
always @(posedge pclk) begin
if (!hist_en_pclk || !(|hor_woi)) odd_pix <= 0;
else odd_pix <= ~odd_pix;
if (!hist_en_pclk || !((XOR_HIST_BAYER[0] ^ left[0])? hor_woi[1] : hor_woi[0])) memen_even[0] <= 0;
else memen_even[0] <= ~memen_even[0];
memen_even[6:1] <= memen_even[5:0];
if (!hist_en_pclk || !((XOR_HIST_BAYER[0] ^ left[0])? hor_woi[0] : hor_woi[1])) memen_odd[0] <= 0;
else memen_odd[0] <= ~memen_odd[0];
memen_odd[6:1] <= memen_odd[5:0];
if (hor_woi[1:0] == 2'b01) hist_rwaddr_even[8] <= bayer_pclk[1];
if (hor_woi[1:0] == 2'b01) hist_rwaddr_odd[8] <= bayer_pclk[1];
if (set_ra_even) hist_rwaddr_even[7:0] <= px_d0;
else if (set_wa_even) hist_rwaddr_even[7:0] <= px_d5;
if (set_ra_odd) hist_rwaddr_odd[7:0] <= px_d0;
else if (set_wa_odd) hist_rwaddr_odd[7:0] <= px_d5;
rwen_even <= memen_even[0] || memen_even[5];
rwen_odd <= memen_odd[0] || memen_odd[5];
r_load <= {r_load[2:0], regen_even | regen_odd};
r0_sel <= regen_odd;
eq_prev_prev <= hor_woi[4] && (px_d4 == px_d0);
eq_prev <= hor_woi[2] && (px_d2 == px_d0);
if (r_load[0]) r0 <= eq_prev_prev_d2 ? r3 : (r0_sel ? hist_new_odd : hist_new_even);
if (r_load[1]) r1 <= eq_prev_d3 ? r2 : r0;
if (r_load[1]) r1_sat <= eq_prev_d3 ? (&r2) : (&r0);
if (r_load[2]) r2 <= ((HISTOGRAM_RAM_MODE != "BUF18") || !r1_sat) ? (r1 + 1) : r1;
if (r_load[3]) r3 <= r2;
end
// after hist_out was off, require inactive grant before sending rq
reg en_rq_start;
always @ (posedge mclk) begin
en_mclk <= en;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
hist_out_d <= hist_out;
// reset address each time new transfer is started
if (!hist_out) hist_raddr <= 0;
else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
// prevent starting rq if grant is still on (back-to-back)
if (!hist_out) en_rq_start <= 0;
else if (!hist_grant) en_rq_start <= 1;
hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
if (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;
else if (hist_grant) hist_re[0] <= 1;
hist_re[2:1] <= hist_re[1:0];
// reg hist_re_even;
// reg hist_re_odd;
if (!hist_out || (&hist_raddr[7:0])) hist_re_even <= 0;
else if (hist_grant && !hist_re[0]) hist_re_even <= !hist_raddr[8];
if (!hist_out || (&hist_raddr[7:0])) hist_re_odd <= 0;
else if (hist_grant && !hist_re[0]) hist_re_odd <= hist_raddr[8];
// if (!hist_out || (&hist_raddr[7:1])) hist_re_even_odd[0] <= 0;
// else if (hist_re[0]) hist_re_even_odd[0] <= ~hist_re_even_odd[0];
// else if (hist_grant) hist_re_even_odd[0] <= 1; // hist_re[0] == 0 here
if (!en_mclk) hist_bank_mclk <= 0;
// else if (hist_xfer_done_mclk && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_mclk <= !hist_bank_mclk; // Not applicable in this module
else if (hist_xfer_done_mclk) hist_bank_mclk <= !hist_bank_mclk;
hist_dv <= hist_re[2];
end
always @ (posedge pclk) begin
if (!en) wait_readout <= 0;
// else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1; // Not applicable in this module
else if (hist_xfer_done) wait_readout <= 0;
end
`ifdef DEBUG_RING
debug_slave #(
.SHIFT_WIDTH (64),
.READ_WIDTH (64),
.WRITE_WIDTH (32),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_slave_i (
.mclk (mclk), // input
.mrst (mrst), // input
.debug_di (debug_di), // input
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
.rd_data ({debug_lines[15:0], debug_line_cntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
`endif
cmd_deser #(
.ADDR (HISTOGRAM_ADDR),
.ADDR_MASK (HISTOGRAM_ADDR_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (2),
.DATA_WIDTH (32),
.ADDR1 (0),
.ADDR_MASK1 (0),
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_histogram_i (
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (pio_addr), // output[15:0]
.data (pio_data), // output[31:0]
.we (pio_stb) // output
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly0_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h2), // input[3:0]
.din (hist_di), // input[0:0]
.dout (px_d0) // output[0:0]
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly2_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h1), // input[3:0]
.din (px_d0), // input[0:0]
.dout (px_d2) // output[0:0]
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly4_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h1), // input[3:0]
.din (px_d2), // input[0:0]
.dout (px_d4) // output[0:0]
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly5_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h0), // input[3:0]
.din (px_d4), // input[0:0]
.dout (px_d5) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_eq_prev_prev_d2_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h1), // input[3:0]
.din (eq_prev_prev), // input[0:0]
.dout (eq_prev_prev_d2) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_eq_prev_d3_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h2), // input[3:0]
.din (eq_prev), // input[0:0]
.dout (eq_prev_d3) // output[0:0]
);
pulse_cross_clock pulse_cross_clock_lt_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_left_top_w), // input
.out_pulse (set_left_top_pclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_wh_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_width_height_w), // input
.out_pulse (set_width_height_pclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hist_done_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (hist_done), // input
.out_pulse (hist_done_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hist_xfer_done_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (hist_xfer_done_mclk), // input
.out_pulse (hist_xfer_done), // output
.busy() // output
);
//TODO: make it double cycle in timing
// select between 18-bit wide histogram data using a single BRAM or 2 BRAMs having full 32 bits
generate
if ((HISTOGRAM_RAM_MODE=="BUF32") || (HISTOGRAM_RAM_MODE=="NOBUF"))// impossible to use a two RAMB18E1 32-bit wide
sens_hist_ram_snglclk_32 sens_hist_ram_snglclk_32_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2), // input[31:0]
.data_out_a_even (hist_new_even), // output[31:0]
.data_out_a_odd (hist_new_odd), // output[31:0]
.en_a_even (rwen_even), // input
.en_a_odd (rwen_odd), // input
.regen_a_even (regen_even), // input
.regen_a_odd (regen_odd), // input
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_even (hist_re_even), // input
.re_odd (hist_re_odd) // input
);
else if (HISTOGRAM_RAM_MODE=="BUF18")
sens_hist_ram_snglclk_18 sens_hist_ram_snglclk_18_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2[17:0]), // input[31:0]
.data_out_a_even (hist_new_even[17:0]), // output[31:0]
.data_out_a_odd (hist_new_odd[17:0]), // output[31:0]
.en_a_even (rwen_even), // input
.en_a_odd (rwen_odd), // input
.regen_a_even (regen_even), // input
.regen_a_odd (regen_odd), // input
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_even (hist_re_even), // input
.re_odd (hist_re_odd) // input
);
endgenerate
endmodule
module sens_hist_ram_snglclk_32(
input pclk,
input [9:0] addr_a_even,
input [9:0] addr_a_odd,
input [31:0] data_in_a,
output [31:0] data_out_a_even,
output [31:0] data_out_a_odd,
input en_a_even,
input en_a_odd,
input regen_a_even,
input regen_a_odd,
input we_a_even,
input we_a_odd,
input mclk,
input [9:0] addr_b,
output reg [31:0] data_out_b,
input re_even,
input re_odd
);
reg re_even_d;
reg re_odd_d;
reg odd;
wire [31:0] data_out_b_w_even;
wire [31:0] data_out_b_w_odd;
always @(posedge mclk) begin
re_even_d <= re_even;
re_odd_d <= re_odd;
odd <= re_odd;
data_out_b <= odd ? data_out_b_w_odd : data_out_b_w_even;
end
ramt_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(5),
.LOG2WIDTH_B(5),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_even_i (
.clk_a (pclk), // input
.addr_a (addr_a_even), // input[10:0]
.en_a (en_a_even), // input
.regen_a (regen_a_even), // input
.we_a (we_a_even), // input
.data_out_a (data_out_a_even), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_even), // input
.regen_b (re_even_d), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_even), // output[15:0]
.data_in_b (32'b0) // input[15:0]
);
ramt_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(5),
.LOG2WIDTH_B(5),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_odd_i (
.clk_a (pclk), // input
.addr_a (addr_a_odd), // input[10:0]
.en_a (en_a_odd), // input
.regen_a (regen_a_odd), // input
.we_a (we_a_odd), // input
.data_out_a (data_out_a_odd), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_odd), // input
.regen_b (re_odd_d), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_odd), // output[15:0]
.data_in_b (32'b0) // input[15:0]
);
endmodule
module sens_hist_ram_snglclk_18(
input pclk,
input [9:0] addr_a_even,
input [9:0] addr_a_odd,
input [17:0] data_in_a,
output [17:0] data_out_a_even,
output [17:0] data_out_a_odd,
input en_a_even,
input en_a_odd,
input regen_a_even,
input regen_a_odd,
input we_a_even,
input we_a_odd,
input mclk,
input [9:0] addr_b,
output reg [31:0] data_out_b,
input re_even,
input re_odd
);
reg re_even_d;
reg re_odd_d;
reg odd;
wire [17:0] data_out_b_w_even;
wire [17:0] data_out_b_w_odd;
always @(posedge mclk) begin
re_even_d <= re_even;
re_odd_d <= re_odd;
odd <= re_odd;
data_out_b <= {14'b0,(odd ? data_out_b_w_odd : data_out_b_w_even)};
end
ram18tp_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(4),
.LOG2WIDTH_B(4),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_even_i (
.clk_a (pclk), // input
.addr_a (addr_a_even), // input[10:0]
.en_a (en_a_even), // input
.regen_a (regen_a_even), // input
.we_a (we_a_even), // input
.data_out_a (data_out_a_even), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_even), // input
.regen_b (re_even_d), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_even), // output[15:0]
.data_in_b (18'b0) // input[15:0]
);
ram18tp_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(4),
.LOG2WIDTH_B(4),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_odd_i (
.clk_a (pclk), // input
.addr_a (addr_a_odd), // input[10:0]
.en_a (en_a_odd), // input
.regen_a (regen_a_odd), // input
.we_a (we_a_odd), // input
.data_out_a (data_out_a_odd), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_odd), // input
.regen_b (re_odd_d), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_odd), // output[15:0]
.data_in_b (18'b0) // input[15:0]
);
endmodule
module sens_histogram_snglclk_dummy(
output hist_rq,
output [31:0] hist_do,
output hist_dv
`ifdef DEBUG_RING
, output debug_do,
input debug_di
`endif
);
assign hist_rq = 0;
assign hist_do = 0;
assign hist_dv = 0;
`ifdef DEBUG_RING
assign debug_do = debug_di;
`endif
endmodule
\ No newline at end of file
sensor/sens_parallel12.v
View file @ 69b1d30b
......@@ -59,9 +59,10 @@ module sens_parallel12 #(
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
......@@ -71,7 +72,7 @@ module sens_parallel12 #(
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
......@@ -82,6 +83,7 @@ module sens_parallel12 #(
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input mclk_rst,
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
output irst,
output ipclk, // re-generated sensor output clock (regional clock to drive external fifo)
......@@ -139,7 +141,9 @@ module sens_parallel12 #(
reg set_ctrl_r;
reg set_status_r;
reg [1:0] set_width_r; // to make double-cycle subtract
wire set_width_ipclk; //re-clocked to pclk
wire set_width_ipclk_w; //re-clocked to ipclk
reg set_width_ipclk_r; // copy from mclk domain when reset is off
wire set_width_ipclk = set_width_ipclk_w || set_width_ipclk_r; //re-clocked to ipclk
reg set_jtag_r;
reg [LINE_WIDTH_BITS-1:0] line_width_m1; // regenerated HACT duration;
......@@ -203,6 +207,12 @@ module sens_parallel12 #(
reg hact_alive;
reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3];
assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
......@@ -212,8 +222,17 @@ module sens_parallel12 #(
assign iaro = trigger_mode? ~trig : iaro_soft;
assign irst=irst_r[2];
always @ (posedge ipclk) begin
irst_r <= {irst_r[1:0], prst};
// irst_r <= {irst_r[1:0], prst};
irst_r <= {irst_r[1:0], prsts}; // extended reset that includes sensor reset and rst_mmcm
set_width_ipclk_r <= irst_r[2] && !irst_r[1];
end
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
always @(posedge mclk) begin
......@@ -357,7 +376,7 @@ module sens_parallel12 #(
.src_clk (mclk), // input
.dst_clk (ipclk), // input
.in_pulse (set_width_r[1]), // input
.out_pulse (set_width_ipclk), // output
.out_pulse (set_width_ipclk_w), // output
.busy() // output
);
......@@ -642,7 +661,7 @@ module sens_parallel12 #(
// received from the sensor (may need to reset MMCM after resetting sensor)
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (SENS_PCLK_PERIOD),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR), // SENS_PCLK_PERIOD), assuming both sources have the same frequency!
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), //8
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
......
sensor/sensor_channel.v
View file @ 69b1d30b
......@@ -43,7 +43,7 @@ module sensor_channel#(
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
......@@ -136,11 +136,20 @@ module sensor_channel#(
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
......@@ -149,7 +158,9 @@ module sensor_channel#(
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
......@@ -173,11 +184,12 @@ module sensor_channel#(
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// sens_parallel12 other parameters
......@@ -189,43 +201,87 @@ module sensor_channel#(
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`else
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`endif
parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT"
`endif
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
) (
// input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
// I/O pads, pin names match circuit diagram
inout [7:0] sns_dp,
inout [7:0] sns_dn,
`ifdef HISPI
input sns_clkp,
input sns_clkn,
`else
inout sns_clkp,
inout sns_clkn,
`endif
inout sns_scl,
inout sns_sda,
`ifdef HISPI
output sns_ctl,
`else
inout sns_ctl,
`endif
inout sns_pg,
// programming interface
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
......@@ -268,9 +324,11 @@ module sensor_channel#(
assign debug_ring[DEBUG_RING_LENGTH] = debug_di;
`endif
localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware)
`ifdef USE_PCLK2X
localparam HIST_MONOCHROME = 1'b0; // TODO:make it configurable (at expense of extra hardware).
// No, will not use it - monochrome is rare, can combine
// 4 (color) histograms by the software.
`endif
localparam SENSOR_BASE_ADDR = (SENSOR_GROUP_ADDR + SENSOR_NUMBER * SENSOR_BASE_INC);
localparam SENSI2C_STATUS_REG = (SENSI2C_STATUS_REG_BASE + SENSOR_NUMBER * SENSI2C_STATUS_REG_INC + SENSI2C_STATUS_REG_REL);
......@@ -297,16 +355,16 @@ module sensor_channel#(
wire [7:0] sens_i2c_status_ad;
wire sens_i2c_status_rq;
wire sens_i2c_status_start;
wire [7:0] sens_par12_status_ad;
wire sens_par12_status_rq;
wire sens_par12_status_start;
wire [7:0] sens_phys_status_ad;
wire sens_phys_status_rq;
wire sens_phys_status_start;
`ifndef HISPI
wire ipclk; // Use in FIFO
// wire ipclk2x; // Use in FIFO?
wire [11:0] pxd_to_fifo;
wire vact_to_fifo; // frame active @posedge ipclk
wire hact_to_fifo; // line active @posedge ipclk
`endif
// data from FIFO
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
wire hact; // line active @posedge ipclk
......@@ -358,6 +416,7 @@ module sensor_channel#(
wire trig;
reg sof_out_r;
reg eof_out_r;
wire prsts; // @pclk - includes sensor reset and sensor PLL reset
// TODO: insert vignetting and/or flat field, pixel defects before gamma_*_in
assign lens_pxd_in = {pxd[11:0],4'b0};
......@@ -464,9 +523,9 @@ module sensor_channel#(
.db_in0 (sens_i2c_status_ad), // input[7:0]
.rq_in0 (sens_i2c_status_rq), // input
.start_in0 (sens_i2c_status_start), // output
.db_in1 (sens_par12_status_ad), // input[7:0]
.rq_in1 (sens_par12_status_rq), // input
.start_in1 (sens_par12_status_start), // output
.db_in1 (sens_phys_status_ad), // input[7:0]
.rq_in1 (sens_phys_status_rq), // input
.start_in1 (sens_phys_status_start), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
......@@ -536,74 +595,67 @@ module sensor_channel#(
.sda (sns_sda) // inout
);
// wire [3:0] debug_hist_mclk;
wire irst; // @ posedge ipclk
localparam STATUS_ALIVE_WIDTH = 8;
wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive;
// debug_hist_mclk is never active, alive_hist0_rq == 0
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
`ifndef HISPI
reg hact_r; // hact delayed by 1 cycle to generate start pulse
reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge
reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge
reg hist_rq0_r;
reg hist_gr0_r;
wire sol_mclk;
wire sof_mclk;
wire eof_mclk;
reg hist_rq0_r;
reg hist_gr0_r;
wire alive_hist0_rq = hist_rq[0] && !hist_rq0_r;
wire alive_hist0_gr = hist_gr[0] && !hist_gr0_r;
// sof_out_mclk - already exists
reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge
reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge
wire dout_valid_1cyc_mclk;
wire last_in_line_1cyc_mclk;
// debug_hist_mclk is never active, alive_hist0_rq == 0
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
/*
sof, hact are tested to be active
.sof (gamma_sof_out), // input
.hact (gamma_hact_out), // input
// wire [3:0] debug_hist_mclk;
wire irst; // @ posedge ipclk
localparam STATUS_ALIVE_WIDTH = 8;
wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive;
assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq,
sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
always @ (posedge mclk) begin
hist_rq0_r <= hist_rq[0];
hist_gr0_r <= hist_gr[0];
end
*/
always @ (posedge pclk) begin
// hact_r <= hact;
hact_r <= gamma_hact_out;
dout_valid_d_pclk <= dout_valid;
last_in_line_d_pclk <= last_in_line;
end
always @ (posedge mclk) begin
// hist_rq0_r <= en_mclk & (hist_rq[0] ^ hist_rq0_r);
hist_rq0_r <= hist_rq[0];
hist_gr0_r <= hist_gr[0];
end
/*
.hist_rq (hist_rq[0]), // output
.hist_grant (hist_gr[0]), // input
*/
// for debug/test alive
// for debug/test alive
pulse_cross_clock pulse_cross_clock_sol_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (hact && !hact_r), // input
// .in_pulse (hact && !hact_r), // input
.in_pulse (gamma_hact_out && !hact_r), // input
.out_pulse (sol_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_sof_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (sof), // input
// .in_pulse (sof), // input
.in_pulse (gamma_sof_out), // input
.out_pulse (sof_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (eof), // input
......@@ -612,7 +664,8 @@ module sensor_channel#(
);
pulse_cross_clock pulse_cross_clock_dout_valid_1cyc_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (dout_valid && !dout_valid_d_pclk), // input
......@@ -621,7 +674,8 @@ module sensor_channel#(
);
pulse_cross_clock pulse_cross_clock_last_in_line_1cyc_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (last_in_line && !last_in_line_d_pclk), // input
......@@ -629,7 +683,103 @@ module sensor_channel#(
.busy() // output
);
`endif
`ifdef HISPI
sens_10398 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS)
) sens_10398_i (
.pclk (pclk), // input
.prst (prst), // input
.prsts (prsts), // output
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start), // input
.trigger_mode (trigger_mode), // input
.trig (trig), // input
.sns_dp (sns_dp[3:0]), // input[3:0]
.sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.sens_ext_clk_p (sns_dp[6]), // output
.sens_ext_clk_n (sns_dn[6]), // output
.sns_pgm (sns_pg), // inout
.sns_ctl_tck (sns_ctl), // output
.sns_mrst (sns_dp[7]), // output
.sns_arst_tms (sns_dn[7]), // output
.sns_gp0_tdi (sns_dp[5]), // output
.sns_gp1 (sns_dn[5]), // output
.sns_flash_tdo (sns_dp[4]), // input
.sns_shutter_done (sns_dn[4]), // input
.pxd (pxd), // output[11:0]
.hact (hact), // output
.sof (sof), // output
.eof (eof) // output
);
`else
sens_parallel12 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -662,8 +812,9 @@ module sensor_channel#(
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
......@@ -682,6 +833,7 @@ module sensor_channel#(
.pclk (pclk), // input
.mclk_rst (mrst), // input
.prst (prst), // input
.prsts (prsts), // output
.irst (irst), // output
.ipclk (ipclk), // output
.ipclk2x (), // ipclk2x), // output
......@@ -703,9 +855,9 @@ module sensor_channel#(
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (sens_par12_status_ad), // output[7:0]
.status_rq (sens_par12_status_rq), // output
.status_start (sens_par12_status_start) // input
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start) // input
);
sensor_fifo #(
......@@ -713,10 +865,12 @@ module sensor_channel#(
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY)
) sensor_fifo_i (
// .rst (rst), // input
// .rst (rst), // input
.iclk (ipclk), // input
.pclk (pclk), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.irst (irst), // input
.pxd_in (pxd_to_fifo), // input[11:0]
.vact (vact_to_fifo), // input
......@@ -726,7 +880,7 @@ module sensor_channel#(
.sof (sof), // output @posedge pclk
.eof (eof) // output @posedge pclk
);
`endif
sens_sync #(
.SENS_SYNC_ADDR (SENS_SYNC_ADDR),
.SENS_SYNC_MASK (SENS_SYNC_MASK),
......@@ -741,7 +895,8 @@ module sensor_channel#(
.pclk (pclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.en (en_pclk), // input @pclk
.sof_in (sof), // input
.eof_in (eof), // input
......@@ -785,7 +940,8 @@ module sensor_channel#(
.SENS_LENS_A_WIDTH (19),
.SENS_LENS_B_WIDTH (21)
) lens_flat393_i (
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -823,7 +979,8 @@ module sensor_channel#(
// .rst (rst), // input
.pclk (pclk), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pxd_in (gamma_pxd_in), // input[15:0]
.hact_in (gamma_hact_in), // input
.sof_in (gamma_sof_in), // input
......@@ -842,19 +999,19 @@ module sensor_channel#(
// TODO: Use generate to generate 1-4 histogram modules
generate
if (HISTOGRAM_ADDR0 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
`endif
) sens_histogram_0_i (
.mrst (mrst), // input
.prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -872,45 +1029,88 @@ module sensor_channel#(
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[0])
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_0_i (
.hist_rq (hist_rq[0]), // output
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_di (debug_ring[1]) // input
`endif
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[0] = debug_ring[1]; // just bypass
// assign tmp1 = debug_ring[1]; // just bypass
//`endif
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_0_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[0]), // input
.hist_rst (!hist_nrst[0]), // input
.hist_rq (hist_rq[0]), // output
.hist_grant (hist_gr[0]), // input
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_0_i (
.hist_rq (hist_rq[0]), // output
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_di (debug_ring[1]) // input
`endif
);
// `ifdef USE_PCLK2X
`endif
endgenerate
generate
if (HISTOGRAM_ADDR1 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR1),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
`endif
) sens_histogram_1_i (
.mrst (mrst), // input
.prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -927,30 +1127,73 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[1])
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[2]) // input
`endif
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_1_i (
.hist_rq (hist_rq[1]), // output
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_di (debug_ring[2]) // input
`endif
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[1] = debug_ring[2]; // just bypass
//`endif
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR1),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_1_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[1]), // input
.hist_rst (!hist_nrst[1]), // input
.hist_rq (hist_rq[1]), // output
.hist_grant (hist_gr[1]), // input
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[2]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_1_i (
.hist_rq (hist_rq[1]), // output
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_di (debug_ring[2]) // input
`endif
);
// `ifdef USE_PCLK2X
`endif
endgenerate
generate
if (HISTOGRAM_ADDR2 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR2),
......@@ -960,10 +1203,9 @@ module sensor_channel#(
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
) sens_histogram_2_i (
.mrst (mrst), // input
.prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -980,7 +1222,6 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[2])
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // input
......@@ -988,7 +1229,51 @@ module sensor_channel#(
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_di (debug_ring[3]) // input
`endif
);
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR2),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_2_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[2]), // input
.hist_rst (!hist_nrst[2]), // input
.hist_rq (hist_rq[2]), // output
.hist_grant (hist_gr[2]), // input
.hist_do (hist_do2), // output[31:0]
.hist_dv (hist_dv[2]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[3]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
......@@ -997,25 +1282,25 @@ module sensor_channel#(
.debug_di (debug_ring[3]) // input
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[2] = debug_ring[3]; // just bypass
//`endif
// `ifdef USE_PCLK2X
`endif
endgenerate
generate
if (HISTOGRAM_ADDR3 >=0)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR3),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_i (
// .rst (rst), // input
`endif
) sens_histogram_3_i (
.mrst (mrst), // input
.prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -1032,26 +1317,68 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
// ,.debug_mclk(debug_hist_mclk[3])
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
`endif
`endif
);
else
sens_histogram_dummy sens_histogram_dummy_i (
sens_histogram_dummy sens_histogram_3_i (
.hist_rq(hist_rq[3]), // output
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_di (debug_ring[4]) // input
`endif
`endif
);
//`ifdef DEBUG_RING
// assign debug_ring[3] = debug_ring[4]; // just bypass
//`endif
// `ifdef USE_PCLK2X
`else
// `ifdef USE_PCLK2X
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR3),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_3_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[3]), // input
.hist_rst (!hist_nrst[3]), // input
.hist_rq (hist_rq[3]), // output
.hist_grant (hist_gr[3]), // input
.hist_do (hist_do3), // output[31:0]
.hist_dv (hist_dv[3]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_3_i (
.hist_rq(hist_rq[3]), // output
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_di (debug_ring[4]) // input
`endif
);
`endif
endgenerate
sens_histogram_mux sens_histogram_mux_i (
......
sensor/sensor_fifo.v
View file @ 69b1d30b
......@@ -23,7 +23,7 @@
module sensor_fifo #(
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
parameter SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
)(
// input rst,
input iclk, // input -synchronous clock
......
sensor/sensors393.v
View file @ 69b1d30b
......@@ -35,7 +35,7 @@ module sensors393 #(
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
......@@ -136,11 +136,20 @@ module sensors393 #(
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
......@@ -149,7 +158,9 @@ module sensors393 #(
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
......@@ -173,10 +184,12 @@ module sensors393 #(
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
......@@ -206,15 +219,29 @@ module sensors393 #(
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`endif
// parameter BUF_IPCLK = "BUFR",
// parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
......@@ -231,11 +258,23 @@ module sensors393 #(
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT"
`endif
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
......@@ -244,7 +283,9 @@ module sensors393 #(
// input rst,
// will generate it here
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input ref_clk, // IODELAY calibration
input dly_rst,
input mrst, // @posedge mclk, sync reset
......@@ -262,11 +303,21 @@ module sensors393 #(
// I/O pads, pin names match circuit diagram (each sensor)
inout [31:0] sns_dp,
inout [31:0] sns_dn,
`ifdef HISPI
inout [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
inout [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`else
inout [3:0] sns_clkp,
inout [3:0] sns_clkn,
`endif
inout [3:0] sns_scl,
inout [3:0] sns_sda,
`ifdef HISPI
inout [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode
`else
inout [3:0] sns_ctl,
`endif
inout [3:0] sns_pg,
// Memory interface (4 channels)
......@@ -453,11 +504,20 @@ module sensors393 #(
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
......@@ -465,7 +525,9 @@ module sensors393 #(
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
......@@ -477,14 +539,15 @@ module sensors393 #(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.SENSI2C_DRIVE (SENSI2C_DRIVE),
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifndef HISPI
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
`endif
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
......@@ -493,9 +556,15 @@ module sensors393 #(
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
......@@ -508,13 +577,26 @@ module sensors393 #(
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
`endif
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sensor_channel_i (
// .rst (rst), // input
.pclk (pclk), // input
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.mrst (mrst), // input
.prst (prst), // input
......
simulation_modules/par12_hispi_psp4l.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: par12_hispi_psp4l
* Date:2015-10-11
* Author: andrey
* Description: Convertp parallel 12bit to HiSPi packetized-SP 4 lanes
*
* Copyright (c) 2015 Elphel, Inc .
* par12_hispi_psp4l.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* par12_hispi_psp4l.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module par12_hispi_psp4l#(
parameter FULL_HEIGHT = 0, // number of lines in a frame. If 0 - wait to the VACT end, if > 0 - output immediately
parameter CLOCK_MPY = 10,
parameter CLOCK_DIV = 3,
parameter LANE0_DLY = 1.3,
parameter LANE1_DLY = 2.7,
parameter LANE2_DLY = 0.2,
parameter LANE3_DLY = 1.8,
parameter CLK_DLY = 2.3,
parameter EMBED_LINES = 2, // number of first lines containing embedded (non-image) data
parameter MSB_FIRST = 0,
parameter FIFO_LOGDEPTH = 12 // line FIFO address bits (includes sync+latency overhead)
)(
input pclk,
input rst,
input [11:0] pxd,
input vact,
input hact_in, // should be multiple of 4 pixels
output [3:0] lane_p,
output [3:0] lane_n,
output clk_p,
output clk_n
);
localparam FIFO_DEPTH = 1 << FIFO_LOGDEPTH;
localparam [3:0] SYNC_SOF = 3;
localparam [3:0] SYNC_SOL = 1;
localparam [3:0] SYNC_EOF = 7;
localparam [3:0] SYNC_EOL = 6;
// localparam SYNC_EMBED = 4;
integer lines_left; // number of lines left in a frame
integer pre_lines; // Number of lines left with "embedded" (not image) data
reg [ 1:0] lane_pcntr; // count input pixels to extend hact to 4*n if needed
wire hact = hact_in || (|lane_pcntr);
reg image_lines;
reg vact_d;
reg [47:0] pxd_d;
reg [48:0] fifo_di; // msb: 0 - data,1 sync
reg fifo_we;
reg hact_d;
reg next_sof;
reg next_line_pclk; // triggers serial output of a line (generated at SOL and EOF, wait full line)
reg next_frame_pclk; // start of a new frame on input
wire pre_fifo_we_eof_w = (FULL_HEIGHT > 0) ? (next_line_pclk && (lines_left == 0)) : (vact_d && !vact);
// wire pre_fifo_we_sof_sol_w = vact_d && ((FULL_HEIGHT > 0) ? ((next_sof && hact && !hact_d) || (hact_d && ! hact && (lines_left > 1)))
wire pre_fifo_we_sof_sol_w = vact_d && ((FULL_HEIGHT > 0) ? ((next_sof && hact && !hact_d) || (next_line_pclk && (lines_left != 0)))
: (hact && !hact_d));
wire pre_fifo_we_data_w = vact_d && hact_d && (lane_pcntr == 0);
wire pre_fifo_we_w = pre_fifo_we_eof_w || pre_fifo_we_sof_sol_w || pre_fifo_we_data_w;
always @(posedge pclk) begin
if (!vact) lines_left <= FULL_HEIGHT;
else if (hact_d && ! hact) lines_left <= lines_left - 1;
end
always @(posedge pclk) begin
vact_d <= vact;
hact_d <= hact;
// pxd_d <= {pxd_d[35:0],pxd};
pxd_d <= {pxd, pxd_d[47:12]};
if (!vact) lane_pcntr <= 0;
else if (hact) lane_pcntr <= lane_pcntr + 1;
if (!vact) pre_lines <= EMBED_LINES;
else if (!image_lines && hact_d && !hact) pre_lines <= pre_lines - 1;
if (!vact) image_lines <= (EMBED_LINES != 0);
else if (!image_lines && hact_d && !hact && (pre_lines == 1)) image_lines <= 1;
if (!vact) next_sof <= 1;
else if (hact_d) next_sof <= 0;
if (!vact_d) next_line_pclk <= 0;
else next_line_pclk <= (FULL_HEIGHT >0)? (hact_d && !hact): (!vact || (hact && !hact_d && !next_sof));
next_frame_pclk <= vact_d && hact && !hact_d && next_sof;
fifo_we <= pre_fifo_we_w;
if (!pre_fifo_we_w) fifo_di <= 'bx;
else if (pre_fifo_we_data_w) fifo_di <= {1'b0,pxd_d};
else if (pre_fifo_we_sof_sol_w) fifo_di <= {1'b1,{4 {{ 7'b0, ~image_lines, next_sof?SYNC_SOF:SYNC_SOL}}}};
else if (pre_fifo_we_eof_w) fifo_di <= {1'b1,{4 {{7'b0, 1'b0, SYNC_EOF}}}};
end
reg [48:0] fifo_ram [0 : FIFO_DEPTH - 1];
reg [FIFO_LOGDEPTH - 1:0] fifo_wa;
always @ (posedge pclk) begin
if (rst) fifo_wa <= 0;
else if (fifo_we) fifo_wa <= fifo_wa + 1;
if (fifo_we) fifo_ram[fifo_wa] <= fifo_di;
end
// generate output clock (normally multiplier first, but in simulation there will be less calculations if division is first)
wire oclk;
// wire int_clk;
wire next_line_oclk;
wire next_frame_oclk ;
reg orst_r = 1;
wire orst = rst || orst_r;
simul_clk_mult_div #(
.MULTIPLIER(CLOCK_MPY),
.DIVISOR(CLOCK_DIV),
.SKIP_FIRST(5)
) simul_clk_div_mult_i (
.clk_in(pclk), // input
.en(1'b1), // input
.clk_out(oclk) // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) pulse_cross_clock_sof_sol_i (
.rst (rst), // input
.src_clk (pclk), // input
.dst_clk (oclk), // input
.in_pulse (next_line_pclk), // input
.out_pulse (next_line_oclk), // output
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) pulse_cross_clock_sof_i (
.rst (rst), // input
.src_clk (pclk), // input
.dst_clk (oclk), // input
.in_pulse (next_frame_pclk), // input
.out_pulse (next_frame_oclk), // output
.busy() // output
);
always @ (oclk) begin
orst_r <= rst;
end
wire [3:0] rdy ; // all lanes operate at the same time, only one rdy bit is used
wire [3:0] sdata;
wire [3:0] sdata_dly;
reg [FIFO_LOGDEPTH - 1:0] fifo_ra;
wire [48:0] fifo_out = fifo_ram[fifo_ra];
wire fifo_dav;
// wire next_line;
wire sof_sol_sent;
reg [1:0] lines_available; // number of lines ready in FIFO
wire line_available = |lines_available;
generate
genvar i;
for (i=0; i < 4; i=i+1) begin: cmprs_channel_block
par12_hispi_psp4l_lane #(
.SYNC_SOF (SYNC_SOF),
.SYNC_SOL (SYNC_SOL),
.SYNC_EOF (SYNC_EOF),
.SYNC_EOL (SYNC_EOL),
.IDL (12'h800),
.MSB_FIRST (MSB_FIRST)
) par12_hispi_psp4l_lane_i (
.clk (oclk), // input
.rst (orst), // input
.din ({fifo_out[48], fifo_out[i * 12 +: 12]}), // input[12:0]
.dav (fifo_dav), // input
.next_line (line_available), // input
.sof_sol_sent (sof_sol_sent), // output reg
.rdy (rdy[i]), // output
.sout (sdata[i]) // output reg
);
// TODO: Add delays and diff out here?
end
endgenerate
reg [1:0] frames_open; // number of frames that are already started on input, but not yet finished on output //next_frame_oclk
wire eof_sent = rdy[0] && fifo_dav && fifo_out[48] && (fifo_out[2:0] == SYNC_EOF[2:0]);
assign fifo_dav = (|frames_open) && !(fifo_out[48] && (fifo_out[2:0] == SYNC_SOF[2:0]) && !line_available);
always @(posedge oclk) begin
if (orst) lines_available <= 0;
else if ( next_line_oclk && !sof_sol_sent) lines_available <= lines_available + 1;
else if (!next_line_oclk && sof_sol_sent) lines_available <= lines_available - 1;
if (orst) frames_open <= 0;
else if ( next_frame_oclk && !eof_sent) frames_open <= frames_open + 1;
else if (!next_frame_oclk && eof_sent) frames_open <= frames_open - 1;
if (orst) fifo_ra <= fifo_wa;
else if (fifo_dav && rdy[0]) fifo_ra <= fifo_ra + 1;
end
sim_frac_clk_delay #(
.FRAC_DELAY (LANE0_DLY),
.SKIP_FIRST (5)
) sim_frac_clk_delay0_i (
.clk (oclk), // input
.din (sdata[0]), // input
.dout (sdata_dly[0]) // output
);
sim_frac_clk_delay #(
.FRAC_DELAY (LANE1_DLY),
.SKIP_FIRST (5)
) sim_frac_clk_delay1_i (
.clk (oclk), // input
.din (sdata[1]), // input
.dout (sdata_dly[1]) // output
);
sim_frac_clk_delay #(
.FRAC_DELAY (LANE2_DLY),
.SKIP_FIRST (5)
) sim_frac_clk_delay2_i (
.clk (oclk), // input
.din (sdata[2]), // input
.dout (sdata_dly[2]) // output
);
sim_frac_clk_delay #(
.FRAC_DELAY (LANE3_DLY),
.SKIP_FIRST (5)
) sim_frac_clk_delay3_i (
.clk (oclk), // input
.din (sdata[3]), // input
.dout (sdata_dly[3]) // output
);
reg clk_pn;
wire clk_pn_dly;
always @ (posedge oclk) begin
if (orst) clk_pn <= 0;
else clk_pn <= ~clk_pn;
end
sim_frac_clk_delay #(
.FRAC_DELAY (CLK_DLY),
.SKIP_FIRST (5)
) sim_frac_clk_delay_clk_i (
.clk (oclk), // input
.din (clk_pn), // input
.dout (clk_pn_dly) // output
);
assign lane_p = sdata_dly;
assign lane_n = ~sdata_dly;
assign clk_p = clk_pn_dly;
assign clk_n = ~clk_pn_dly;
endmodule
module par12_hispi_psp4l_lane#(
parameter [3:0] SYNC_SOF = 3,
parameter [3:0] SYNC_SOL = 1,
parameter [3:0] SYNC_EOF = 7,
parameter [3:0] SYNC_EOL = 6,
parameter [11:0] IDL = 12'h800,
parameter MSB_FIRST = 0
)(
input clk,
input rst,
input [12:0] din,
input dav,
input next_line, // enable to continue seq_eol_sol
output reg sof_sol_sent, // SOL sent
output rdy,
output reg sout
);
reg [11:0] sr;
reg [11:0] sr_in;
reg sr_in_av; //
reg [ 3:0] bcntr;
reg [ 3:0] seq_sof;
reg [ 3:0] seq_eof;
reg [ 7:0] seq_eol_sol;
reg embed;
wire dav_rdy = dav && rdy;
wire is_sync = din[12];
wire [11:0] din_filt = (din[11:1] == 11'h0)? 12'h001 : din[11:0];
// wire pause = seq_eol_sol[4] && !next_line;
wire pause = seq_eol_sol[3] && !next_line;
assign rdy = !sr_in_av;
always @ (posedge clk) begin
if (rst || (bcntr == 11)) bcntr <= 0;
else bcntr <= bcntr + 1;
if (rst) sr <= 'bx;
else if (bcntr == 0) sr <= (sr_in_av && !pause) ? sr_in : IDL;
else sr <= MSB_FIRST ? {sr[10:0],1'b0} : {1'b0,sr[11:1]};
sout <= MSB_FIRST ? sr[11] : sr[0];
if (rst) embed <= 0;
else if (dav_rdy && is_sync) embed <= din[4];
if (rst) seq_sof <= 0;
else if (dav_rdy && is_sync && (din[3:0] == SYNC_SOF )) seq_sof <= 8;
else if (bcntr == 0) seq_sof <= seq_sof >> 1;
if (rst) seq_eof <= 0;
else if (dav_rdy && is_sync && (din[2:0] == SYNC_EOF[2:0] )) seq_eof <= 8;
else if (bcntr == 0) seq_eof <= seq_eof >> 1;
if (rst) seq_eol_sol <= 0;
else if (dav_rdy && is_sync && (din[3:0] == SYNC_SOL )) seq_eol_sol <= 'h80;
else if ((bcntr == 0) && !pause) seq_eol_sol <= seq_eol_sol >> 1;
if (dav_rdy) sr_in <= is_sync ? 12'hfff : din_filt;
else if ((bcntr == 0) && !pause) begin
if (seq_sof[3] || seq_eof[3] || seq_eol_sol[7] || seq_eol_sol[3]) sr_in <= 12'h0;
else if (seq_eol_sol[4]) sr_in <= 12'hfff;
else if (seq_sof[1]) sr_in <= {7'b0, embed, SYNC_SOF};
else if (seq_eof[1]) sr_in <= {7'b0, 1'b0, SYNC_EOF};
else if (seq_eol_sol[5]) sr_in <= {7'b0, 1'b0, SYNC_EOL};
else if (seq_eol_sol[1]) sr_in <= {7'b0, embed, SYNC_SOL};
end
if (rst) sr_in_av <= 0;
else if (dav_rdy) sr_in_av <= 1;
// else if (bcntr == 0) sr_in_av <= (|seq_sof[3:1]) || (|seq_eof[3:1]) || ((|seq_eol_sol[7:1]) && !pause);
else if (bcntr == 0) sr_in_av <= (|seq_sof[3:1]) || (|seq_eof[3:1]) || (|seq_eol_sol[7:1]);
sof_sol_sent <= (bcntr == 0) && (seq_sof[1] || seq_eol_sol[1]);
end
endmodule
simulation_modules/sim_clk_div.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sim_clk_div
* Date:2015-10-11
* Author: andrey
* Description: Divide clock frequency by integer number
*
* Copyright (c) 2015 Elphel, Inc .
* sim_clk_div.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sim_clk_div.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sim_clk_div#(
parameter DIVISOR = 5
) (
input clk_in,
input en,
output clk_out
);
integer cntr = 0;
reg clk_out_r = 0;
assign clk_out = (DIVISOR == 1) ? clk_in: clk_out_r;
always @(clk_in) if (en) begin
if (cntr == 0) begin
cntr = DIVISOR - 1;
clk_out_r = !clk_out_r;
end else begin
cntr = cntr - 1;
end
end
endmodule
simulation_modules/sim_frac_clk_delay.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: sim_frac_clk_delay
* Date:2015-10-11
* Author: andrey
* Description: Delay clock-synchronous signal by fractional number of periods
*
* Copyright (c) 2015 Elphel, Inc .
* sim_frac_clk_delay.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sim_frac_clk_delay.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sim_frac_clk_delay #(
parameter FRAC_DELAY = 2.3, // periods of clock > 0.5
parameter SKIP_FIRST = 5 // skip first clock pulses
) (
input clk,
input din,
output dout
);
localparam integer INT_DELAY = $rtoi (FRAC_DELAY);
// localparam [0:0] HALF_DELAY = $rtoi(2.0 *(FRAC_DELAY - INT_DELAY));
localparam [0:0] HALF_DELAY = (FRAC_DELAY - INT_DELAY) >= 0.5;
localparam RDELAY = (FRAC_DELAY - INT_DELAY) - 0.5 * HALF_DELAY;
integer num_period = 0;
reg en = 0;
real phase;
real prev_phase = 0.0;
real frac_period = 0.0;
// measure period
always @ (posedge clk) begin
phase = $realtime;
if (num_period >= SKIP_FIRST) begin
frac_period = RDELAY* (phase - prev_phase);
en = 1;
end
prev_phase = phase;
if (!en) num_period = num_period + 1;
end
reg [INT_DELAY:0] sr = 0;
reg [INT_DELAY:0] sr_fract = 0;
wire [INT_DELAY+1:0] taps = {sr,din};
wire [INT_DELAY+1:0] taps_fract = {sr_fract,din};
reg dly_half;
// reg dly_int;
always @(posedge clk) if (en) begin
sr <= taps[INT_DELAY:0];
// #frac_period sr_fract <= taps[INT_DELAY:0];
#frac_period sr_fract <= sr;
end
always @(negedge clk) if (en) begin
#frac_period dly_half = taps[INT_DELAY];
end
// assign dout = dly_half;
// assign dout = HALF_DELAY ? dly_half : taps[INT_DELAY];
// assign #frac_period dout = HALF_DELAY ? dly_half : taps[INT_DELAY];
assign dout = HALF_DELAY ? dly_half : taps_fract[INT_DELAY];
// assign #(RDELAY*period) dout = HALF_DELAY ? dly_half : taps[INT_DELAY];
endmodule
simulation_modules/simul_clk_div_mult.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: simul_clk_div_mult
* Date:2015-10-12
* Author: andrey
* Description: Simulation clock rational multiplier
*
* Copyright (c) 2015 Elphel, Inc .
* simul_clk_div_mult.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_clk_div_mult.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module simul_clk_div_mult#(
parameter MULTIPLIER = 3,
parameter DIVISOR = 5,
parameter SKIP_FIRST = 5
) (
input clk_in,
input en,
output clk_out
);
wire clk_int;
generate
if (DIVISOR > 1)
sim_clk_div #(
.DIVISOR (DIVISOR)
) sim_clk_div_i (
.clk_in (clk_in), // input
.en (en), // input
.clk_out (clk_int) // output
);
else
assign clk_int = clk_in;
endgenerate
generate
if (MULTIPLIER > 1)
simul_clk_mult #(
.MULTIPLIER (MULTIPLIER),
.SKIP_FIRST (SKIP_FIRST)
) simul_clk_mult_i (
.clk_in (clk_int), // input
.en (en), // input
.clk_out (clk_out) // output
);
else
assign clk_out = clk_int;
endgenerate
endmodule
simulation_modules/simul_clk_mult.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: simul_clk_mult
* Date:2015-10-10
* Author: andrey
* Description: Clock multiplier
*
* Copyright (c) 2015 Elphel, Inc .
* simul_clk_mult.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_clk_mult.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module simul_clk_mult#(
parameter MULTIPLIER = 3,
parameter SKIP_FIRST = 5
) (
input clk_in,
input en,
output clk_out
);
real phase;
real prev_phase = 0.0;
real out_half_period = 0.0;
integer num_period = 0;
reg en1 = 0;
reg clk_out_r = 0;
assign clk_out = (MULTIPLIER == 1)? clk_in: clk_out_r;
always @ (posedge clk_in) begin
phase = $realtime;
if (num_period >= SKIP_FIRST) begin
out_half_period = (phase - prev_phase) / (2 * MULTIPLIER);
en1 = 1;
end
prev_phase = phase;
num_period = num_period + 1;
end
always @ (posedge clk_in) if (en && en1) begin
clk_out_r = 1;
repeat (MULTIPLIER - 1) begin
#out_half_period clk_out_r = 0;
#out_half_period clk_out_r = 1;
end
#out_half_period clk_out_r = 0;
end
endmodule
simulation_modules/simul_clk_mult_div.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: simul_clk_mult_div
* Date:2015-10-12
* Author: andrey
* Description: Simulation clock rational multiplier
*
* Copyright (c) 2015 Elphel, Inc .
* simul_clk_mult_div.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_clk_mult_div.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module simul_clk_mult_div#(
parameter MULTIPLIER = 3,
parameter DIVISOR = 5,
parameter SKIP_FIRST = 5
) (
input clk_in,
input en,
output clk_out
);
wire clk_int;
generate
if (MULTIPLIER > 1)
simul_clk_mult #(
.MULTIPLIER (MULTIPLIER),
.SKIP_FIRST (SKIP_FIRST)
) simul_clk_mult_i (
.clk_in (clk_in), // input
.en (en), // input
.clk_out (clk_int) // output
);
else
assign clk_int = clk_in;
endgenerate
generate
if (DIVISOR > 1)
sim_clk_div #(
.DIVISOR (DIVISOR)
) sim_clk_div_i (
.clk_in (clk_int), // input
.en (en), // input
.clk_out (clk_out) // output
);
else
assign clk_out = clk_int;
endgenerate
endmodule
simulation_modules/simul_sensor12bits.v
View file @ 69b1d30b
......@@ -20,6 +20,7 @@
*******************************************************************************/
module simul_sensor12bits # (
parameter SENSOR_IMAGE_TYPE = "NORM", // "RUN1",
parameter lline = 192, // 1664;// line duration in clocks
parameter ncols = 66, //58; //56; // 129; //128; //1288;
parameter nrows = 18, // 16; // 1032;
......@@ -134,6 +135,7 @@ initial begin
//parameter nrows = 16; // 1032;
$display ("sensor parameters");
$display (" -- image type = %s",SENSOR_IMAGE_TYPE);
$display (" -- ramp = %d (0 - random, 1 - ramp)",ramp);
$display (" -- lline = %d (line duration in clocks)",lline);
$display (" -- ncols = %d (numer of clocks in HACT)",ncols);
......@@ -143,7 +145,12 @@ initial begin
$display (" -- new_bayer = %d ",new_bayer);
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh("input_data/sensor.dat",sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh("input_data/sensor_run1.dat",sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh("input_data/sensor.dat",sensor_data);
end
c=0;
// {ibpf,ihact,ivact}=0;
stopped=1;
......
system_defines.vh
View file @ 69b1d30b
......@@ -2,7 +2,24 @@
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
// `define sg15E 1
// `define sg187E 1
`define den4096Mb 1
`define MCLK_VCO_MULT 16
// `define MCLK_VCO_MULT 18
// `define MCLK_VCO_MULT 20
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
`ifdef IVERILOG
......
timing/camsync393.v
View file @ 69b1d30b
......@@ -570,7 +570,7 @@ module camsync393 #(
end
// Why was it local_got_pclk? Also, it is a multi-bit vector
// rcv_done_rq <= start_en && ((ts_external_pclk && local_got_pclk) || (rcv_done_rq && rcv_run));
// TODO: think of disabling receiving sync if sesnor is not ready yet (not done with a previous frame)
// TODO: think of disabling receiving sync if sensor is not ready yet (not done with a previous frame)
rcv_done_rq <= start_en && ((ts_external_pclk && (rcv_run && !rcv_run_d)) || (rcv_done_rq && rcv_run));
//
rcv_done_rq_d <= rcv_done_rq;
......
util_modules/clocks393.v
View file @ 69b1d30b
......@@ -40,20 +40,22 @@ module clocks393#(
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter BUF_CLK1X_PCLK = "BUFG",
`ifdef USE_PCLK2X
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
`endif
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter BUF_CLK1X_XCLK = "BUFG",
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
`endif
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
......@@ -101,9 +103,13 @@ module clocks393#(
output aclk, // global clock 50 MHz (used for maxi0)
output hclk, // global clock 150MHz (used for afi*, saxi*)
output pclk, // global clock for sensors (now 96MHz), based on external clock generator
`ifdef USE_PCLK2X
output pclk2x, // global clock for sennors, 2x frequency (now 192MHz)
`endif
output xclk, // global clock for compressor (now 100MHz)
`ifdef USE_XCLK2X
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
`endif
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
input [1:0] extra_status, // just extra two status bits from the top module
......@@ -203,16 +209,24 @@ module clocks393#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_PCLK),
.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.BUF_CLK1X (BUF_CLK1X_PCLK)
`ifdef USE_PCLK2X
,.CLKOUT_DIV_CLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_PCLK),
.BUF_CLK1X (BUF_CLK1X_PCLK),
.BUF_CLK2X (BUF_CLK1X_PCLK2X)
`else
,.BUF_CLK2X ("NONE")
`endif
) dual_clock_pclk_i (
.rst (async_rst || reset_clk[1]), // input
.clk_in (ffclk0), // input
.pwrdwn (pwrdwn_clk[1]), // input
.clk1x (pclk), // output
`ifdef USE_PCLK2X
.clk2x (pclk2x), // output
`else
.clk2x (), // output not connected
`endif
.locked (locked[1]) // output
);
......@@ -221,16 +235,24 @@ module clocks393#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_XCLK),
.BUF_CLK1X (BUF_CLK1X_XCLK),
`ifdef USE_XCLK2X
.CLKOUT_DIV_CLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_XCLK),
.BUF_CLK1X (BUF_CLK1X_XCLK),
.BUF_CLK2X (BUF_CLK1X_XCLK2X)
`else
.BUF_CLK2X ("NONE")
`endif
) dual_clock_xclk_i (
.rst (async_rst || reset_clk[2]), // input
.clk_in (aclk), // input
.pwrdwn (pwrdwn_clk[2]), // input
.clk1x (xclk), // output
`ifdef USE_XCLK2X
.clk2x (xclk2x), // output
`else
.clk2x (), // output
`endif
.locked (locked[2]) // output
);
......
util_modules/fifo_1cycle.v
View file @ 69b1d30b
......@@ -30,7 +30,7 @@ module fifo_1cycle
(
input rst, // reset, active high
input clk, // clock - positive edge
input srst, // sync reset
input sync_rst, // sync reset
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
......@@ -61,20 +61,20 @@ module fifo_1cycle
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (srst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill;
if (rst) wa <= 0;
else if (srst) wa <= 0;
else if (sync_rst) wa <= 0;
else if (we) wa <= wa+1;
if (rst) ra <= 0;
else if (srst) ra <= 0;
else if (sync_rst) ra <= 0;
else if (re) ra <= ra+1;
else if (fill==0) ra <= wa; // Just recover from bit errors
if (rst) nempty <= 0;
else if (srst) nempty <= 0;
else if (sync_rst) nempty <= 0;
else nempty <= (next_fill!=0);
......
util_modules/fifo_cross_clocks.v
View file @ 69b1d30b
......@@ -82,12 +82,13 @@ module fifo_cross_clocks
end
always @ (posedge rclk or posedge rst) begin
if (rst) raddr <= 0;
else if (rrst) raddr <= 0;
// making rrst set FIFO to empty regardless of current waddr (write should be stopped)
if (rst) raddr <= waddr; // 0;
else if (rrst) raddr <= waddr; // 0;
else if (re) raddr <= raddr_plus1;
if (rst) raddr_gray_top3 <= 0;
else if (rrst) raddr_gray_top3 <= 0;
if (rst) raddr_gray_top3 <= waddr[DATA_DEPTH-1 -: 3] ^ {1'b0,waddr[DATA_DEPTH-1 -: 2]}; // 0;
else if (rrst) raddr_gray_top3 <= waddr[DATA_DEPTH-1 -: 3] ^ {1'b0,waddr[DATA_DEPTH-1 -: 2]}; // 0;
else if (re) raddr_gray_top3 <= raddr_plus1_gray_top3;
end
......
util_modules/fifo_same_clock.v
View file @ 69b1d30b
......@@ -55,7 +55,7 @@ module fifo_same_clock
reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa;
wire [DATA_DEPTH-1:0] next_fill;
// wire [DATA_DEPTH-1:0] next_fill;
reg wem;
wire rem;
reg out_full=0; //output register full
......@@ -63,7 +63,7 @@ module fifo_same_clock
reg ram_nempty;
assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
// assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
......@@ -75,7 +75,9 @@ module fifo_same_clock
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill;
// else fill <= next_fill;
else if ( wem && ~rem) fill <= fill + 1;
else if (~wem && rem) fill <= fill - 1;
if (rst) wem <= 0;
else if (sync_rst) wem <= 0;
......@@ -83,7 +85,9 @@ module fifo_same_clock
if (rst) ram_nempty <= 0;
else if (sync_rst) ram_nempty <= 0;
else ram_nempty <= (next_fill != 0);
// else ram_nempty <= (next_fill != 0);
// else ram_nempty <= wem || (|fill[DATA_DEPTH-1:1]) || (fill[0] && !rem);
else ram_nempty <= (|fill[DATA_DEPTH-1:1]) || (fill[0] && wem) || ((fill[0] || wem) && !rem) ;
if (rst) wa <= 0;
else if (sync_rst) wa <= 0;
......
util_modules/status_router16.v
View file @ 69b1d30b
......@@ -84,7 +84,9 @@ module status_router16(
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 status_router2_top_i (
status_router2 #(
.FIFO_TYPE ("TWO_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
) status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
......
util_modules/status_router2.v
View file @ 69b1d30b
......@@ -22,7 +22,9 @@
`timescale 1ns/1ps
`include "system_defines.vh"
//`define DEBUG_FIFO 1
module status_router2 (
module status_router2 #(
parameter FIFO_TYPE = "ONE_CYCLE" // "TWO_CYCLE"
)(
input rst,
input clk,
input srst, // sync reset
......@@ -99,26 +101,28 @@ module status_router2 (
end
/* fifo_same_clock has currently latency of 2 cycles, use smth. faster here? - fifo_1cycle (but it has unregistered data output) */
generate
if (FIFO_TYPE == "ONE_CYCLE") begin
fifo_1cycle #(
.DATA_WIDTH(9),
.DATA_DEPTH(4) // 16
) fifo_in0_i (
.rst (1'b0), // rst), // input
.clk (clk), // input
.srst (srst), // input
.sync_rst (srst), // input
.we (start_rcv[0] || rcv_rest_r[0]), // input
.re (fifo_re[0]), // input
.data_in ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
.data_out ({fifo_last_byte[0],fifo0_out}), // output[8:0]
.nempty (fifo_nempty_pre[0]), // output
.nempty (fifo_nempty_pre[0]), // output reg
.half_full (fifo_half_full[0]) // output reg
`ifdef DEBUG_FIFO
`ifdef DEBUG_FIFO
,.under(), // output reg
.over(), // output reg
.wcount(), // output[3:0] reg
.rcount(), // output[3:0] reg
.num_in_fifo() // output[3:0]
`endif
`endif
);
fifo_1cycle #(
......@@ -127,21 +131,67 @@ module status_router2 (
) fifo_in1_i (
.rst (1'b0), // rst), // input
.clk (clk), // input
.srst (srst), // input
.sync_rst (srst), // input
.we (start_rcv[1] || rcv_rest_r[1]), // input
.re (fifo_re[1]), // input
.data_in ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
.data_out ({fifo_last_byte[1],fifo1_out}), // output[8:0]
.nempty (fifo_nempty_pre[1]), // output
.nempty (fifo_nempty_pre[1]), // output reg
.half_full (fifo_half_full[1]) // output reg
`ifdef DEBUG_FIFO
`ifdef DEBUG_FIFO
,.under(), // output reg
.over(), // output reg
.wcount(), // output[3:0] reg
.rcount(), // output[3:0] reg
.num_in_fifo() // output[3:0]
`endif
`endif
);
end else begin
fifo_same_clock #(
.DATA_WIDTH(9),
.DATA_DEPTH(4) // 16
) fifo_in0_i (
.rst (1'b0), // rst), // input
.clk (clk), // input
.sync_rst (srst), // input
.we (start_rcv[0] || rcv_rest_r[0]), // input
.re (fifo_re[0]), // input
.data_in ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
.data_out ({fifo_last_byte[0],fifo0_out}), // output[8:0]
.nempty (fifo_nempty_pre[0]), // output reg
.half_full (fifo_half_full[0]) // output reg
`ifdef DEBUG_FIFO
,.under(), // output reg
.over(), // output reg
.wcount(), // output[3:0] reg
.rcount(), // output[3:0] reg
.num_in_fifo() // output[3:0]
`endif
);
fifo_same_clock #(
.DATA_WIDTH(9),
.DATA_DEPTH(4) // 16
) fifo_in1_i (
.rst (1'b0), // rst), // input
.clk (clk), // input
.sync_rst (srst), // input
.we (start_rcv[1] || rcv_rest_r[1]), // input
.re (fifo_re[1]), // input
.data_in ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
.data_out ({fifo_last_byte[1],fifo1_out}), // output[8:0]
.nempty (fifo_nempty_pre[1]), // output reg
.half_full (fifo_half_full[1]) // output reg
`ifdef DEBUG_FIFO
,.under(), // output reg
.over(), // output reg
.wcount(), // output[3:0] reg
.rcount(), // output[3:0] reg
.num_in_fifo() // output[3:0]
`endif
);
end
endgenerate
// one car per green (round robin priority)
// start sending out with with one cycle latency - now 2 cycles because of the FIFO
......
util_modules/status_router4.v
View file @ 69b1d30b
......@@ -47,7 +47,9 @@ module status_router4(
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 status_router2_top_i (
status_router2 #(
.FIFO_TYPE ("TWO_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
) status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
......
util_modules/status_router8.v
View file @ 69b1d30b
......@@ -59,7 +59,9 @@ module status_router8(
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 status_router2_top_i (
status_router2 #(
.FIFO_TYPE ("ONE_CYCLE") //= "ONE_CYCLE" // higher latency, but easier timing - use on some levels (others - default "ONE_CYCLE")
) status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.srst (srst), // input
......
util_modules/sync_resets.v
View file @ 69b1d30b
......@@ -32,7 +32,8 @@ module sync_resets#(
);
reg en_locked=0; // mostly for simulation, locked[0] is 1'bx until the first clock[0] pulse
wire [WIDTH-1:0] rst_w; // resets matching input clocks
wire rst_early_master;
wire rst_early_master_w;
reg rst_early_master;
assign rst = rst_w;
reg mrst = 1;
always @ (posedge arst or posedge clk[0]) begin
......@@ -43,13 +44,16 @@ module sync_resets#(
if (arst) mrst <= 1;
else mrst <= ~(locked[0] && en_locked);
end
always @(posedge clk[0]) begin
rst_early_master <= rst_early_master_w;
end
level_cross_clocks #(
.WIDTH (1),
.REGISTER (REGISTER)
) level_cross_clocks_mrst_i (
.clk (clk[0]), // input
.d_in (mrst), // input[0:0]
.d_out (rst_early_master) // output[0:0]
.d_out (rst_early_master_w) // output[0:0]
);
generate
......@@ -57,7 +61,7 @@ module sync_resets#(
for (i = 1; i < WIDTH; i = i + 1) begin: rst_block
level_cross_clocks #(
.WIDTH (1),
.REGISTER (REGISTER)
.REGISTER ((i==5) ? 1: REGISTER) // disable for aclk
) level_cross_clocks_rst_i (
.clk (clk[i]), // input
.d_in (mrst || rst_early_master || ~locked[i] ), // input[0:0]
......
wrap/ddr3_wrap.v
View file @ 69b1d30b
......@@ -276,7 +276,8 @@ module ddr3_wrap#(
assign #(DQS_IN_DELAY_H) DQSU = en_dqs_in[1]? DQSU_DH3: 1'bz;
assign #(DQS_IN_DELAY_H) NDQSU = en_dqs_in[1]? NDQSU_DH3: 1'bz;
ddr3 #(
ddr3
/*#(
.TCK_MIN (2500),
.TJIT_PER (100),
.TJIT_CC (200),
......@@ -444,7 +445,8 @@ module ddr3_wrap#(
.DIFF_GROUP (2'd2),
.SIMUL_500US (5),
.SIMUL_200US (2)
) ddr3_i (
) */
ddr3_i (
.rst_n (SDRST_D), // input
.ck (SDCLK_D), // input
.ck_n (SDNCLK_D), // input
......
wrap/iserdes_mem.v
View file @ 69b1d30b
......@@ -23,7 +23,8 @@
module iserdes_mem #
(
parameter DYN_CLKDIV_INV_EN="FALSE",
parameter IOBDELAY = "IFD" // "NONE", "IBUF", "IFD", "BOTH"
parameter IOBDELAY = "IFD", // "NONE", "IBUF", "IFD", "BOTH"
parameter MSB_FIRST = 0 // 0 - lowest bit is received first, 1 - highest is received first
) (
input iclk, // source-synchronous clock
input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
......@@ -35,7 +36,8 @@ module iserdes_mem #
output [3:0] dout,
output comb_out // combinatorial output copies selected input to be used in the fabric
);
wire [3:0] dout_le;
assign dout = MSB_FIRST ? {dout_le[0], dout_le[1], dout_le[2], dout_le[3]} : dout_le;
`ifndef OPEN_SOURCE_ONLY // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )
ISERDESE2 #(
.DATA_RATE ("DDR"),
......@@ -60,10 +62,10 @@ module iserdes_mem #
iserdes_i
(
.O (comb_out),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q1 (dout_le[3]),
.Q2 (dout_le[2]),
.Q3 (dout_le[1]),
.Q4 (dout_le[0]),
.Q5 (),
.Q6 (),
.Q7 (),
......@@ -111,10 +113,10 @@ module iserdes_mem #
iserdes_i
(
.O (comb_out),
.Q1 (dout[3]),
.Q2 (dout[2]),
.Q3 (dout[1]),
.Q4 (dout[0]),
.Q1 (dout_le[3]),
.Q2 (dout_le[2]),
.Q3 (dout_le[1]),
.Q4 (dout_le[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
......
wrap/mmcm_adv.v
View file @ 69b1d30b
......@@ -62,7 +62,7 @@ module mmcm_adv#(
// EXTERNAL - external to the FPGA network is being compensated
// BUF_IN - no compensation when clock input is driveen by BUFG/BUFH/BUFR or GT
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
......
wrap/mmcm_phase_cntr.v
View file @ 69b1d30b
......@@ -63,7 +63,7 @@ module mmcm_phase_cntr#(
// EXTERNAL - external to the FPGA network is being compensated
// BUF_IN - no compensation when clock input is driveen by BUFG/BUFH/BUFR or GT
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
......
wrap/obufds.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: obufds
* Date:2015-10-15
* Author: andrey
* Description: Wrapper for OBUFDS primitive
*
* Copyright (c) 2015 Elphel, Inc .
* obufds.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* obufds.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module obufds #(
parameter CAPACITANCE = "DONT_CARE",
parameter IOSTANDARD = "DEFAULT",
parameter SLEW = "SLOW"
)(
output o,
output ob,
input i
);
OBUFDS #(
.CAPACITANCE (CAPACITANCE),
.IOSTANDARD (IOSTANDARD),
.SLEW(SLEW)
) OBUFDS_i (
.O (o), // output
.OB (ob), // output
.I (i) // input
);
endmodule
wrap/ram18t_var_w_var_r.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: ram18t_var_w_var_r
* Date:2015-05-29
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Does not use parity bits to increase total data width, width down to 1 are valid.
*
* Copyright (c) 2015 Elphel, Inc.
* ram18t_var_w_var_r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ram18t_var_w_var_r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ram18t_var_w_var_r
#(
parameter integer REGISTERS_A = 0, // 1 - registered output
parameter integer REGISTERS_B = 0, // 1 - registered output
parameter integer LOG2WIDTH_A = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_B = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [13-LOG2WIDTH_A:0] addr_a, // address port A
input en_a, // enable port A (read and write)
input regen_a, // output register enable port A
input we_a, // write port enable port A
output [(1 << LOG2WIDTH_A)-1:0] data_out_a,// data out port A
input [(1 << LOG2WIDTH_A)-1:0] data_in_a, // data in port A
input clk_b, // clock for port BA
input [13-LOG2WIDTH_B:0] addr_b, // address port B
input en_b, // read enable port B
input regen_b, // output register enable port B
input we_b, // write port enable port B
output [(1 << LOG2WIDTH_B)-1:0] data_out_b,// data out port B
input [(1 << LOG2WIDTH_B)-1:0] data_in_b // data in port B
);
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
localparam WIDTH_B = 1 << LOG2WIDTH_B;
wire [15:0] data_out16_a;
assign data_out_a=data_out16_a[WIDTH_A-1:0];
wire [15:0] data_out16_b;
assign data_out_b=data_out16_b[WIDTH_B-1:0];
wire [WIDTH_A+15:0] data_in_ext_a = {16'b0,data_in_a[WIDTH_A-1:0]};
wire [15:0] data_in16_a = data_in_ext_a[15:0];
wire [WIDTH_B+15:0] data_in_ext_b = {16'b0,data_in_b[WIDTH_B-1:0]};
wire [15:0] data_in16_b = data_in_ext_b[15:0];
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS_A), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS_B), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A (WRITE_MODE_A), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B (WRITE_MODE_B), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB18E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out16_a), // Port A data/LSB data[15:0], output
.DOPADOP (), // Port A parity/LSB parity[1:0], output
.DIADI (data_in16_a), // Port A data/LSB data[15:0], input
.DIPADIP (2'b0), // Port A parity/LSB parity[1:0], input
.ADDRARDADDR ({addr_a,{LOG2WIDTH_A{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (clk_a), // Port A (read port in SDP) clock, input
.ENARDEN (en_a), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen_a), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA ({2{we_a}}), // Port A (read port in SDP) Write Enable[1:0], input
// Port B
.DOBDO (data_out16_b), // Port B data/MSB data[31:0], output
.DOPBDOP (), // Port B parity/MSB parity[3:0], output
.DIBDI (data_in16_b), // Port B data/MSB data[31:0], input
.DIPBDIP (2'b0), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (read port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (clk_b), // Port B (write port in SDP) clock, input
.ENBWREN (en_b), // Port B (write port in SDP) Enable, input
.REGCEB (regen_b), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE ({4{we_b}}) // Port B (write port in SDP) Write Enable[3:0], input
);
endmodule
wrap/ram18tp_var_w_var_r.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: ram18tp_var_w_var_r
* Date:2015-10-21
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB18E1. Same R/W widths in each port.
* Uses parity bits to increase total data width. Widths down to 9 are valid.
*
* Copyright (c) 2015 Elphel, Inc.
* ram18tp_var_w_var_r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ram18tp_var_w_var_r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ram18tp_var_w_var_r
#(
parameter integer REGISTERS_A = 0, // 1 - registered output
parameter integer REGISTERS_B = 0, // 1 - registered output
parameter integer LOG2WIDTH_A = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_B = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [13-LOG2WIDTH_A:0] addr_a, // address port A
input en_a, // enable port A (read and write)
input regen_a, // output register enable port A
input we_a, // write port enable port A
output [(9 << (LOG2WIDTH_A-3))-1:0] data_out_a,// data out port A
input [(9 << (LOG2WIDTH_A-3))-1:0] data_in_a, // data in port A
input clk_b, // clock for port BA
input [13-LOG2WIDTH_B:0] addr_b, // address port B
input en_b, // read enable port B
input regen_b, // output register enable port B
input we_b, // write port enable port B
output [(9 << (LOG2WIDTH_B-3))-1:0] data_out_b,// data out port B
input [(9 << (LOG2WIDTH_B-3))-1:0] data_in_b // data in port B
);
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
localparam WIDTH_AP = 1 << (LOG2WIDTH_A-3);
localparam WIDTH_B = 1 << LOG2WIDTH_B;
localparam WIDTH_BP = 1 << (LOG2WIDTH_B-3);
wire [15:0] data_out16_a;
wire [ 1:0] datap_out2_a;
assign data_out_a={datap_out2_a[WIDTH_AP-1:0], data_out16_a[WIDTH_A-1:0]};
wire [15:0] data_out16_b;
wire [ 1:0] datap_out2_b;
assign data_out_b={datap_out2_b[WIDTH_BP-1:0], data_out16_b[WIDTH_B-1:0]};
wire [WIDTH_A+15:0] data_in_ext_a = {16'b0,data_in_a[WIDTH_A-1:0]};
wire [15:0] data_in16_a = data_in_ext_a[15:0];
wire [WIDTH_AP+1:0] datap_in_ext_a = {2'b0,data_in_a[WIDTH_A+:WIDTH_AP]};
wire [1:0] datap_in2_a= datap_in_ext_a[1:0];
wire [WIDTH_B+15:0] data_in_ext_b = {16'b0,data_in_b[WIDTH_B-1:0]};
wire [15:0] data_in16_b = data_in_ext_b[15:0];
wire [WIDTH_BP+1:0] datap_in_ext_b = {2'b0,data_in_b[WIDTH_B+:WIDTH_BP]};
wire [1:0] datap_in2_b= datap_in_ext_b[1:0];
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS_A), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS_B), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A (WRITE_MODE_A), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B (WRITE_MODE_B), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB18E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out16_a), // Port A data/LSB data[15:0], output
.DOPADOP (datap_out2_a), // Port A parity/LSB parity[1:0], output
.DIADI (data_in16_a), // Port A data/LSB data[15:0], input
.DIPADIP (datap_in2_a), // Port A parity/LSB parity[1:0], input
.ADDRARDADDR ({addr_a,{LOG2WIDTH_A{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (clk_a), // Port A (read port in SDP) clock, input
.ENARDEN (en_a), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen_a), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA ({2{we_a}}), // Port A (read port in SDP) Write Enable[1:0], input
// Port B
.DOBDO (data_out16_b), // Port B data/MSB data[31:0], output
.DOPBDOP (datap_out2_b), // Port B parity/MSB parity[3:0], output
.DIBDI (data_in16_b), // Port B data/MSB data[31:0], input
.DIPBDIP (datap_in2_b), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (read port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (clk_b), // Port B (write port in SDP) clock, input
.ENBWREN (en_b), // Port B (write port in SDP) Enable, input
.REGCEB (regen_b), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE ({4{we_b}}) // Port B (write port in SDP) Write Enable[3:0], input
);
endmodule
x393.v
View file @ 69b1d30b
......@@ -196,12 +196,14 @@ module x393 #(
//TODO: Create missing clocks
wire pclk; // global clock, sensor pixel rate (96 MHz)
`ifdef USE_PCLK2X
wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
`endif
// compressor pixel rate can be adjusted independently
wire xclk; // global clock, compressor pixel rate (100 MHz)?
`ifdef USE_XCLK2X
wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
`endif
wire camsync_clk; // global clock used for external synchronization. 96MHz in x353.
// Make it independent of pixel, compressor and mclk so it can be frozen
wire logger_clk; // global clock for the event logger. Use 100 MHz, shared with camsync_clk
......@@ -413,6 +415,8 @@ module x393 #(
wire [3:0] sens_buf_rd; // (), // input
wire [255:0] sens_buf_dout; // (), // output[63:0]
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
// TODO: Add counter(s) to count sens_xfer_skipped pulses
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0]
......@@ -436,7 +440,7 @@ module x393 #(
wire [3:0] cmprs_page_ready; // input
wire [3:0] cmprs_next_page; // output
// per-channel master (sesnor)/slave (compressor) synchronization (compressor wait until sesnor provided data)
// per-channel master (sensor)/slave (compressor) synchronization (compressor wait until sensor provided data)
wire [3:0] cmprs_frame_start_dst; // output - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
......@@ -1022,6 +1026,7 @@ assign axi_grst = axi_rst_pre;
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
......@@ -1090,6 +1095,7 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.RSEL (RSEL),
.WSEL (WSEL)
......@@ -1130,7 +1136,7 @@ assign axi_grst = axi_rst_pre;
.sens_buf_rd (sens_buf_rd), // output[3:0]
.sens_buf_dout (sens_buf_dout), // input[255:0]
.sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer
.sens_xfer_skipped (sens_xfer_skipped), // output reg
// compressor interface
.cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0]
.cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0]
......@@ -1487,11 +1493,20 @@ assign axi_grst = axi_rst_pre;
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
......@@ -1499,7 +1514,9 @@ assign axi_grst = axi_rst_pre;
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
......@@ -1515,9 +1532,11 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifndef HISPI
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
`endif
.HIST_SAXI_ADDR_MASK (HIST_SAXI_ADDR_MASK),
.HIST_SAXI_MODE_WIDTH (HIST_SAXI_MODE_WIDTH),
.HIST_SAXI_EN (HIST_SAXI_EN),
......@@ -1538,9 +1557,15 @@ assign axi_grst = axi_rst_pre;
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
......@@ -1559,13 +1584,26 @@ assign axi_grst = axi_rst_pre;
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
`endif
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sensors393_i (
// .rst (axi_rst), // input
.pclk (pclk), // input
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // input
`endif
.ref_clk (ref_clk), // input
.dly_rst (idelay_ctrl_reset), // input
.mrst (mrst), // input
......@@ -1778,9 +1816,10 @@ assign axi_grst = axi_rst_pre;
`endif
) compressor393_i (
// .rst (axi_rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
......@@ -2132,18 +2171,22 @@ assign axi_grst = axi_rst_pre;
.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_PCLK (CLKOUT_DIV_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
`ifdef USE_PCLK2X
.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
.BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X),
`endif
.CLKIN_PERIOD_XCLK (CLKIN_PERIOD_XCLK),
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_XCLK (CLKOUT_DIV_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
`ifdef USE_XCLK2X
.CLKOUT_DIV_XCLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X_XCLK (PHASE_CLK2X_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
.BUF_CLK1X_XCLK2X (BUF_CLK1X_XCLK2X),
`endif
.CLKIN_PERIOD_SYNC (CLKIN_PERIOD_SYNC),
.DIVCLK_DIVIDE_SYNC (DIVCLK_DIVIDE_SYNC),
.CLKFBOUT_MULT_SYNC (CLKFBOUT_MULT_SYNC),
......@@ -2186,9 +2229,13 @@ assign axi_grst = axi_rst_pre;
.aclk (axi_aclk), // output
.hclk (hclk), // output
.pclk (pclk), // output
`ifdef USE_PCLK2X
.pclk2x (pclk2x), // output
`endif
.xclk (xclk), // output
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // output
`endif
.sync_clk (camsync_clk), // output
.time_ref (time_ref), // output
.extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0]
......
x393_no_pclk2x_timing.xdc 0 → 100644
View file @ 69b1d30b
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
#Clock Period Waveform Attributes Sources
#axi_aclk 10.00000 {0.00000 5.00000} P {bufg_axi_aclk_i/O}
#clk_fb 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
#sdclk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
#clk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
#clk_div_pre 5.00000 {0.00000 2.50000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
#mclk_pre 5.00000 {1.25000 3.75000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
#Each list contains 2 elements - warning later in DRC
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Not available initially
#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
# try use first from list - seems that 2 are created from the same name
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
# lindex is not supported in xdc
#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
### Version used with eddr3
###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
x393_nox2_timing.xdc 0 → 100644
View file @ 69b1d30b
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
#Clock Period Waveform Attributes Sources
#axi_aclk 10.00000 {0.00000 5.00000} P {bufg_axi_aclk_i/O}
#clk_fb 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
#sdclk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
#clk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
#clk_div_pre 5.00000 {0.00000 2.50000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
#mclk_pre 5.00000 {1.25000 3.75000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
#Each list contains 2 elements - warning later in DRC
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Not available initially
#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
# try use first from list - seems that 2 are created from the same name
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
# lindex is not supported in xdc
#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
### Version used with eddr3
###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
x393_testbench02.sav
View file @ 69b1d30b
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Oct 10 04:26:57 2015
[*] Tue Nov 3 01:32:22 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151009220220129.fst"
[dumpfile_mtime] "Sat Oct 10 04:26:01 2015"
[dumpfile_size] 96721857
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151102172822765.fst"
[dumpfile_mtime] "Tue Nov 3 01:03:38 2015"
[dumpfile_size] 173188638
[savefile] "/home/andrey/git/x393/x393_testbench02.sav"
[timestart] 65911000
[timestart] 101932300
[size] 1823 1180
[pos] 1922 0
*-17.835970 66537388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 2 0
*-14.369095 101958000 111045900 99486000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench02.
[treeopen] x393_testbench02.compressor_control.
[treeopen] x393_testbench02.simul_axi_hp1_wr_i.
......@@ -25,15 +25,20 @@
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.genblk9.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.genblk9.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_cmd_decode_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_out_fifo_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.byte_fifo_block[0].
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.i_end_burst.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.i_end_burst.bit_block[0].
......@@ -54,7 +59,9 @@
[treeopen] x393_testbench02.x393_i.mcntrl393_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
......@@ -67,8 +74,7 @@
[treeopen] x393_testbench02.x393_i.sensors393_i.histogram_saxi_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk7.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd_block[2].
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_fifo_i.hact_dly_16_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_fifo_i.hact_dly_16_i.bit_block[0].
......@@ -88,9 +94,8 @@
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk7.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk7.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.status_router16_top_i.
[treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.
[treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].
[treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.
......@@ -98,8 +103,8 @@
[treeopen] x393_testbench02.x393_i.timing393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i.
[sst_width] 312
[signals_width] 388
[sst_width] 366
[signals_width] 355
[sst_expanded] 1
[sst_vpaned_height] 611
@820
......@@ -191,7 +196,7 @@ x393_testbench02.TEST_TITLE[639:0]
-
@1401200
-debug_ring
@c00200
@800200
-PX1
@28
x393_testbench02.simul_sensor12bits_i.MRST
......@@ -223,7 +228,7 @@ x393_testbench02.simul_sensor12bits_i.ARO
x393_testbench02.simul_sensor12bits_i.DCLK
@28
x393_testbench02.simul_sensor12bits_i.OFST
@1401200
@1000200
-PX1
@c00200
-PX2
......@@ -272,8 +277,15 @@ x393_testbench02.simul_sensor12bits_4_i.DCLK
-PX4
@c00200
-sensor_channel
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.prst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.prsts
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.irst
@200
-parallel12
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.irst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.ipclk
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.data_r[31:0]
@800028
......@@ -281,6 +293,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.set_width_r[1:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.set_width_r[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.set_width_ipclk
@1001200
-group_end
@c00022
......@@ -666,10 +679,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.comp
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.component_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.component_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.component_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_ren
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.fifo_ren
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.fifo_ren
......@@ -995,7 +1004,6 @@ x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lsw13_zero
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mclk
@22
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mem_page_left[7:0]
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mode_reg[11:0]
@28
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mrst
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.msw_zero
......@@ -1236,8 +1244,24 @@ x393_testbench02.x393_i.membridge_i.status_generate_i.wd[7:0]
@1401200
-membridge_status
-membridge
@c00200
@800200
-compressor0
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_nodc[9:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_start
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_out[12:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.pre_first_out
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_out[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.endv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.dv
@200
-
@c00200
-func_compressor_control
@22
x393_testbench02.func_compressor_control.bayer[31:0]
......@@ -1251,8 +1275,6 @@ x393_testbench02.func_compressor_control.run_mode[31:0]
x393_testbench02.func_compressor_control.tmp[31:0]
@1401200
-func_compressor_control
@200
-
@800200
-compressor_control
@22
......@@ -1274,6 +1296,61 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmpr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_cmd_decode_i.cmprs_standalone
@1000200
-compressor_control
@800200
-xdct
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.clk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.start
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.xin[9:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.last_in
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.pre_first_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.dv
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.d_out[12:0]
@200
-
@800200
-stage1
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.start
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.xin[9:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.we
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.wr_cntr[6:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.z_out[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.page
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage1.done
@200
-
@1000200
-stage1
@800200
-stage2
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.page
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.rd_cntr[6:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.ren
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.regen
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.tdin[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.endv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.dv
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.dct2_out[12:0]
@200
-
@1000200
-stage2
-xdct
@c00200
-write_control_register_0
@22
......@@ -1281,7 +1358,7 @@ x393_testbench02.write_contol_register.data[31:0]
x393_testbench02.write_contol_register.reg_addr[29:0]
@1401200
-write_control_register_0
@800200
@c00200
-cmprs_frame_sync
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_standalone
......@@ -1295,9 +1372,9 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fram
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_standalone
@200
-
@1000200
@1401200
-cmprs_frame_sync
@800200
@c00200
-quantizer
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.ds
......@@ -1318,37 +1395,15 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quan
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.i_coring_table.raddr[11:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.tdco[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.qdo[12:0]
@1000200
@1401200
-quantizer
@200
-
@c00200
-huffman
@800200
-huff_fifo
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.synci
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.ds
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.ds1
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.sync_we
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.dav
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.wa[9:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.diff_a[9:0]
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
@c00028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r
@1401200
-group_end
-group_end
......@@ -1358,127 +1413,127 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_hu
-huff_fifo
@c00200
-varlen_encode
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.clk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel0[1:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel1[1:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel2[1:0]
@1401200
-varlen_encode
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o
@1401200
-group_end
@200
-
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps
@1401200
-group_end
@200
-
-
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta
@1401200
-group_end
-huffman
@c00200
-huffman_snglclk
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.di[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.cycles[2:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.ds
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.d1[11:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.d[11:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.dl[4:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.do27[26:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.dv
@800200
-merge
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.in_valid
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.l[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.l_late[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.q0[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.q[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.huff_code[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.huff_code_len[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.literal[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.literal_len[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.out_bits[26:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.out_len[4:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this0
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this1
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this2
@1401200
-varlen_encode
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.out_valid
@1000200
-merge
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.xclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.xclk2x
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(11)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(12)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(13)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(14)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(15)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_or_full
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.last_block
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.test_lbw
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.stuffer_was_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.will_read
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.want_read
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_or_full
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.eob
@200
-
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_re_r
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC
@800028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC
@800028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.en2x
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotRLL
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.read_next
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotEOB
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotLastBlock
@200
-
-huffman_fifo
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tser_a_not_d
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tser_we
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tdi[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.xclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotLastWord
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.we
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.re
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
@1001200
-group_end
@1401200
-huffman_snglclk
@200
-
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(11)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(12)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(13)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(14)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(15)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(16)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(17)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(18)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(19)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(20)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(21)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(22)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.twe
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tdi[15:0]
@1401200
-huffman
@c00200
-table_ad_transmit
@200
......@@ -1518,7 +1573,7 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.tabl
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.we_r
@1401200
-table_ad_transmit
@800200
@c00200
-encoder_DCAC
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.encoderDCAC393_i.lasti
......@@ -1575,63 +1630,12 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enco
-group_end
@200
-
@1000200
@1401200
-encoder_DCAC
@800200
@c00200
-stuffer
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_pre_stb
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_data[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.clk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.stb_start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_rstb
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_dout[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.was_trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_end
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_end_delayed
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.will_flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.force_flush
@c00028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.vsync_late
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.sec_r[31:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.usec_r[19:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_time_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_size_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_sizeout
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_count[23:0]
@200
-other_module
@28
......@@ -1641,42 +1645,12 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmpr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.aborted_frame
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.reading_frame_r
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.qv
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
@800200
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
@c00200
-timestamp_fifo
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.aclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.advance
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.advance_r[1:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.arst
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.din[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.dout[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.pre_stb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rcv
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rpntr[3:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rrst
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rstb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.sclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.snd
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.snd_d
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.srst
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr
@1401200
-group_end
@1000200
-timestamp_fifo
@200
-other
......@@ -1686,10 +1660,8 @@ x393_testbench02.x393_i.timing393_i.ts_stb_chn0
x393_testbench02.x393_i.timing393_i.ts_stb[3:0]
@200
-
@1000200
@1401200
-stuffer
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.page_ready_chn
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.next_page_chn
......@@ -1700,22 +1672,42 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmpr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_cmd_decode_i.cmprs_run_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.sigle_frame_buf
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.suspend
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush_hclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
@800200
-huffman_stuffer_meta
@200
-caller module
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
[color] 2
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[31:0]
[color] 2
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_word_number
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flushing
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastWord
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
[color] 2
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
@200
-
@800200
-escape
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.flush_in
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.flush_out
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.fifo_byte_pntr[1:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.in_stb
@200
-
@1000200
-escape
-huffman_stuffer_meta
@c00200
-compressor0_other
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.bayer_phase[1:0]
@22
......@@ -1770,7 +1762,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written_xclk2xn
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_count[7:0]
@28
......@@ -1787,7 +1778,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.firs
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_block_dct
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_block_quant
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_mb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush_hclk
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.focus_do[12:0]
......@@ -1811,11 +1801,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hfc_
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hifreq[31:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hrst
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff_dl[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff_do[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff_dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ignore_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.jp4_dc_improved
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.last_mb
......@@ -1880,14 +1865,10 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stat
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.status_data[2:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.status_rq
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.status_start
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.subtract_dc
......@@ -1908,10 +1889,8 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.tser
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.tser_qe
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xclk2x
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xfer_reset_page_rd
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xrst
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xrst2xn
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yaddrw[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_avr[8:0]
......@@ -1920,7 +1899,273 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_n
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_pre_first_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ywe
@1401200
-compressor0_other
@800200
-csconvert18
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.use_cr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pre_first_in
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pre_first_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe_r
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.use_cr
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult2[9:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmulto[17:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmultr[10:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sub_y
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcr[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.q[8:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe
@200
-
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pdc[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.yaddr[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sel_cbcrmult1
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sub_y
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.mm1[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.mm2[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.mm3[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y1[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y2[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y3[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.pre_y[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.y[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.signed_y_r[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cbcrmult1[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sel_cbcrmult1
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.sub_y
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ystrt
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe_r
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.nxtline
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.yaddr[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.use_cr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.strt
@200
-outputs
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.ywe
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.yaddr[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.signed_y[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.caddr_r[6:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.caddr[6:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.q[8:0]
@200
-
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe0
@29
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.i_csconvert18.cwe_r
@1000200
-csconvert18
@c00200
-buf_average
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.yaddrw[7:0]
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_y[8:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.ywe
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.caddrw[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.signed_c[8:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.cwe
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.pre_first_in
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.pre_first_mb
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.do[9:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.ds
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.first
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.first_mb_in
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.pre_first_mb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.raddr_updateBlock
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.ccv_out_start
@200
-y-buf
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.we
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.waddr[10:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.ren
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_y_buff.raddr[10:0]
@1401200
-group_end
@200
-CbCr-buf
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.we
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.waddr[10:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.ren
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.raddr[10:0]
@1401200
-group_end
@200
-
@1401200
-buf_average
@1000200
-compressor0
@800200
-status_routers
@c00200
-start_top
@28
x393_testbench02.x393_i.status_router16_top_i.start_in0
x393_testbench02.x393_i.status_router16_top_i.start_in1
x393_testbench02.x393_i.status_router16_top_i.start_in2
x393_testbench02.x393_i.status_router16_top_i.start_in3
x393_testbench02.x393_i.status_router16_top_i.start_in4
x393_testbench02.x393_i.status_router16_top_i.start_in5
x393_testbench02.x393_i.status_router16_top_i.start_in6
x393_testbench02.x393_i.status_router16_top_i.start_in7
x393_testbench02.x393_i.status_router16_top_i.start_in8
x393_testbench02.x393_i.status_router16_top_i.start_in9
x393_testbench02.x393_i.status_router16_top_i.start_in10
x393_testbench02.x393_i.status_router16_top_i.start_in11
x393_testbench02.x393_i.status_router16_top_i.start_in12
x393_testbench02.x393_i.status_router16_top_i.start_in13
x393_testbench02.x393_i.status_router16_top_i.start_in14
x393_testbench02.x393_i.status_router16_top_i.start_in15
@1401200
-start_top
@28
x393_testbench02.x393_i.status_router16_top_i.start_int[1:0]
x393_testbench02.x393_i.status_router16_top_i.start_out
@200
-top_router_2
@28
x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.clk
@800028
x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.rq_in[1:0]
@28
(0)x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.rq_in[1:0]
(1)x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.rq_in[1:0]
@1001200
-group_end
@200
-
@28
x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.start_in0
x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.start_in1
x393_testbench02.x393_i.status_router16_top_i.status_router2_top_i.start_out
@1000200
-status_routers
@c00200
-mcontr_seq
@800028
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@28
(0)x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
(1)x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
(2)x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@1001200
-group_end
@22
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause_cntr[9:0]
@28
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_fetch
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_nop
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ren0
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ren1
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk_pre
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div_pre
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_pre
@200
-
@1401200
-mcontr_seq
@c00200
-sim_cmprs_output
@22
......@@ -2901,60 +3146,16 @@ x393_testbench02.simul_saxi_gp0_wr_i.sim_wr_valid
@200
-hist-out OK
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.rq
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq_r
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@800200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re
@1001200
-group_end
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(7)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(8)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(9)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(10)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(11)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(12)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(13)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(14)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(15)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(16)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(17)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(18)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(19)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(20)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(21)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(22)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(23)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(24)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(25)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(26)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(27)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(28)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(29)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(30)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(31)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
@1401200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
@c00200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do
@1401200
-group_end
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.burst0[2:0]
@28
......@@ -3535,124 +3736,29 @@ x393_testbench02.x393_i.sensors393_i.histogram_saxi_i.wr_attr
-histogram_saxi
@c00200
-histogram01
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out_d
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vert_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_busy
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.monochrome
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.monochrome_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pre_first_line
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
@800200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d
@1001200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en_pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.wait_readout
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.line_start_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.sof
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_di[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pre_first_line
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.width_m1[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.height_m1[15:0]
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(7)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(8)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(9)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(10)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(11)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(12)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(13)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(14)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(15)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
@1401200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vert_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.frame_active
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_we
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwen
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwaddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.to_inc[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.same_addr1
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.same_addr2
@c00200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr
@1401200
-group_end
@200
-
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@c00200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi
@1401200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa_woi[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_ra[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pulse_cross_clock_hlstart_start_i.in_pulse
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hlstart
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_2x[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi_2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk_sync
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_rq[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_request
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.en
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@800200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re
@1001200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq_r
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
@200
-
@c00200
......@@ -3716,87 +3822,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-hist_mux
@200
-
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.bayer_2x[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.cmd_ad[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.cmd_stb
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_new
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.frame_active
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.height_m1[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_addr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_addr_d2[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_addr_d[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_di[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en_pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_new[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out_d
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_regen[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq_r
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rst_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwaddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwen
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_we
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_busy
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hlstart
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi_2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.inc_r[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.line_start_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.lt_mclk[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mrst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk_sync
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pio_addr[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pio_data[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pio_stb
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pre_first_line
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.prst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_2x[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_ra[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_ra_start[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa_woi[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_left_top_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_left_top_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_width_height_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_width_height_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.sof
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.to_inc[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vert_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.wait_readout
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.wh_mclk[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.width_m1[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@1401200
-histogram01
@c00200
......@@ -3847,7 +3872,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hact_to_fifo
@200
-
@800200
@c00200
-sens_i2c_io
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.cmd_ad[7:0]
......@@ -3907,7 +3932,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.se
-chn3
@200
-
@800200
@c00200
-sens_i2c_selected
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk
......@@ -3956,12 +3981,12 @@ x393_testbench02.set_sensor_i2c_command.tmp[31:0]
-task_set_sensor_i2c_cmd
@200
-
@1000200
@1401200
-sens_i2c_selected
@800200
-sens_i2c
-i2c_prot_sel
@c00200
-i2c_prot_sel
-chn1
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_start
......@@ -4137,7 +4162,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sel_sr_in[1:0]
@1000200
@1401200
-i2c_prot_sel
@c00200
-sensor_i2c_prot
......@@ -4227,8 +4252,9 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.unused
@1401200
-sensor_i2c_prot
@800200
@c00200
-scl_sda_selected
@800200
-chn1
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.i2c_dly[7:0]
......@@ -4258,14 +4284,14 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_r
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
@800023
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
@29
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
@1001201
@1001200
-group_end
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.first_cyc
......@@ -4314,9 +4340,9 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
@1001200
-group_end
@1000200
@1401200
-scl_sda_selected
@800200
@c00200
-scl_sda
@200
-
......@@ -4373,7 +4399,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.start_w
@1000200
@1401200
-scl_sda
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.active_cmd
......@@ -4470,6 +4496,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage_wr[3:0]
@1000200
-sens_i2c
@1401200
-sens_i2c_io
@c00200
-sensor_fifo
......
x393_testbench02.tf
View file @ 69b1d30b
......@@ -1296,6 +1296,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
......@@ -1978,6 +1979,7 @@ simul_axi_hp_wr #(
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE0),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -1996,7 +1998,7 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.new_bayer (0) // was 1 SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_i (
.MCLK (PX1_MCLK), // input
.MRST (PX1_MRST), // input
......@@ -2016,6 +2018,7 @@ simul_axi_hp_wr #(
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE1),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2034,7 +2037,7 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
.MRST (PX2_MRST), // input
......@@ -2053,6 +2056,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE2),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2070,8 +2074,8 @@ simul_axi_hp_wr #(
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.ramp (0), // SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input
......@@ -2090,6 +2094,7 @@ simul_axi_hp_wr #(
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE3),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
.ncols (FULL_WIDTH), // (SENSOR12BITS_NCOLS),
`ifdef PF
......@@ -2107,8 +2112,8 @@ simul_axi_hp_wr #(
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.ramp (0),// SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input
......@@ -2387,8 +2392,8 @@ task setup_sensor_channel;
setup_compressor_channel(
num_sensor, // sensor channel number (0..3)
// 0, // qbank; // [6:3] quantization table page - 100% quality
1, // qbank; // [6:3] quantization table page - 85%? quality
0, // qbank; // [6:3] quantization table page - 100% quality
// 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC
CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
......@@ -2405,7 +2410,7 @@ task setup_sensor_channel;
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
0, // input [31:0] bayer; // [20:18] // Bayer shift
3, // 0, // input [31:0] bayer; // [20:18] // Bayer shift
0, // input [31:0] focus_mode; // [23:21] Set focus mode
3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1
......@@ -2477,10 +2482,10 @@ task setup_sensor_channel;
num_sensor,
0, // num_sub_sensor
// add mode "DIRECT", "ASAP", "RELATIVE", "ABSOLUTE" and frame number
19'h20000, // 0, // input [18:0] AX;
19'h20000, // 0, // input [18:0] AY;
21'h180000, //0, // input [20:0] BX;
21'h180000, //0, // input [20:0] BY;
19'h0, // 19'h20000, // 0, // input [18:0] AX;
19'h0, // 19'h20000, // 0, // input [18:0] AY;
21'h0, // 21'h180000, //0, // input [20:0] BX;
21'h0, // 21'h180000, //0, // input [20:0] BY;
'h8000, // input [18:0] C;
32768, // input [16:0] scales0;
32768, // input [16:0] scales1;
......
x393_testbench03.sav 0 → 100644
View file @ 69b1d30b
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_testbench03.tf 0 → 100644
View file @ 69b1d30b
This source diff could not be displayed because it is too large. You can view the blob instead.
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