Commit 642b83c6 authored by Andrey Filippov's avatar Andrey Filippov

verified hardware to work with the new i2c sequencer, compatible with SMIA sensors

parent a6281669
...@@ -62,42 +62,42 @@ ...@@ -62,42 +62,42 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150923220008330.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150923220435209.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
parameter FPGA_VERSION = 32'h0393003a; parameter FPGA_VERSION = 32'h03930042;
\ No newline at end of file \ No newline at end of file
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...@@ -937,4 +937,33 @@ compressor_control all None 1 ...@@ -937,4 +937,33 @@ compressor_control all None 1
compressor_control all None 0 compressor_control all None 0
mem_save "/usr/local/verilog/memdump_chn0" 0x27a00000 0x01001000 mem_save "/usr/local/verilog/memdump_chn0" 0x27a00000 0x01001000
write_sensor_i2c 0 1 0 0x91900004
read_sensor_i2c 0
set_sensor_i2c_table_reg_wr 0 0x00 0x48 3 100 1
set_sensor_i2c_table_reg_wr 0 0x90 0x48 3 100 1
set_sensor_i2c_table_reg_rd 0 0x01 0 2 100 1
set_sensor_i2c_table_reg_rd 0 0x91 0 2 100 1
========
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl 0 None None None None None 0 0x4
set_sensor_io_ctl 1 None None None None None 0 0xe
set_sensor_io_ctl 2 None None None None None 0 0x4
set_sensor_io_ctl 3 None None None None None 0 0xe
compressor_control all None None None None None 3
program_gamma all 0 0.57 0.04
write_sensor_i2c all 1 0 0x90350009
write_sensor_i2c all 1 0 0x902c000f
write_sensor_i2c all 1 0 0x902d000a
write_sensor_i2c all 1 0 0x90040a23
axi_write_single_w 0x696 0x079800a3
axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
r
""" """
...@@ -734,20 +734,56 @@ class X393SensCmprs(object): ...@@ -734,20 +734,56 @@ class X393SensCmprs(object):
self.x393Sensor.print_status_sensor_i2c (num_sensor = num_sensor) self.x393Sensor.print_status_sensor_i2c (num_sensor = num_sensor)
if verbose >0 : if verbose >0 :
print ("===================== AFI_MUX_SETUP =========================") print ("===================== I2C_SETUP =========================")
self.x393Sensor.set_sensor_i2c_command ( self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor, num_sensor = num_sensor,
rst_cmd = True) rst_cmd = True,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_command ( self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor, num_sensor = num_sensor,
active_sda = True,
early_release_0 = True,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0,
slave_addr = 0x48,
rah = 0,
num_bytes = 3, num_bytes = 3,
dly = 100, # ??None, # 20 ns per 1 of cycle duration. Standard i2c - dly = 125 bit_delay = 100,
scl_ctl = None, verbose = verbose)
sda_ctl = None)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 1,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
# aliases for indices 0x90 and 0x91
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0x90,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 0x91,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
# Turn off reset (is it needed?)
self.x393Sensor.set_sensor_i2c_command ( self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor, num_sensor = num_sensor,
rst_cmd = False) rst_cmd = False)
# Turn on sequencer
self.x393Sensor.set_sensor_i2c_command ( self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor, num_sensor = num_sensor,
run_cmd = True) run_cmd = True)
......
This diff is collapsed.
...@@ -147,8 +147,11 @@ module sensor_i2c_io#( ...@@ -147,8 +147,11 @@ module sensor_i2c_io#(
.I (sda_out), // input .I (sda_out), // input
.T (!sda_en) // input .T (!sda_en) // input
); );
// So simulation will show different when SDA is not driven
`ifndef SIMULATION
mpullup i_scl_pullup(scl); mpullup i_scl_pullup(scl);
mpullup i_sda_pullup(sda); mpullup i_sda_pullup(sda);
`endif
endmodule endmodule
...@@ -101,7 +101,7 @@ module sensor_i2c_prot#( ...@@ -101,7 +101,7 @@ module sensor_i2c_prot#(
// wire i2c_next_byte; // wire i2c_next_byte;
reg [ 2:0] mem_re; reg [ 2:0] mem_re;
reg mem_valid; reg mem_valid;
reg [ 3:0] table_re; reg [ 2:0] table_re;
// reg read_mem_msb; // reg read_mem_msb;
// wire decode_reg_rd = &seq_rd[7:4]; // wire decode_reg_rd = &seq_rd[7:4];
...@@ -146,9 +146,10 @@ module sensor_i2c_prot#( ...@@ -146,9 +146,10 @@ module sensor_i2c_prot#(
wire pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1]; wire pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1];
reg rnw; // last command was read (not write) - do not increment bytes_left_send reg rnw; // last command was read (not write) - do not increment bytes_left_send
// wire dout_stb; // rvalid
assign seq_mem_re = mem_re[1:0]; assign seq_mem_re = mem_re[1:0];
// assign rvalid = dout_stb && run_reg_rd[1];
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0; if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0;
else if (start_rd_seq_w) rnw <= 1; else if (start_rd_seq_w) rnw <= 1;
...@@ -171,7 +172,7 @@ module sensor_i2c_prot#( ...@@ -171,7 +172,7 @@ module sensor_i2c_prot#(
else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open; else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open;
table_re <= {table_re[2:0], pre_table_re}; // start_wr_seq_w}; table_re <= {table_re[1:0], pre_table_re}; // start_wr_seq_w};
if (table_re[2]) begin if (table_re[2]) begin
reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; //[ 7:0]; // MSB of the register address (instead of the byte 2) reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; //[ 7:0]; // MSB of the register address (instead of the byte 2)
......
...@@ -32,7 +32,7 @@ module sensor_i2c_scl_sda( ...@@ -32,7 +32,7 @@ module sensor_i2c_scl_sda(
input snd9, input snd9,
input rcv, // receive mode (valid with snd9) - master receives, slave - sends input rcv, // receive mode (valid with snd9) - master receives, slave - sends
input [ 8:0] din, input [ 8:0] din,
output [ 8:0] dout, // output reg [ 8:0] dout, //
output reg dout_stb, // dout contains valid data output reg dout_stb, // dout contains valid data
output reg scl, // i2c SCL signal output reg scl, // i2c SCL signal
input sda_in, // i2c SDA signal form I/O pad input sda_in, // i2c SDA signal form I/O pad
...@@ -63,17 +63,21 @@ module sensor_i2c_scl_sda( ...@@ -63,17 +63,21 @@ module sensor_i2c_scl_sda(
reg first_cyc; // first clock cycle for the delay interval - update SCL/SDA outputs reg first_cyc; // first clock cycle for the delay interval - update SCL/SDA outputs
reg active_sda_r; // registered @ snd9, disable in rcv mode reg active_sda_r; // registered @ snd9, disable in rcv mode
reg active_sda_was_0; // only use active SDA if previous bit was 0 or it is receive mode reg active_sda_was_0; // only use active SDA if previous bit was 0 or it is receive mode
reg early_release_r; // to enable it only for LSB before ACKN during send
reg rcv_r; reg rcv_r;
wire busy_w = busy_r && ! done_r; wire busy_w = busy_r && ! done_r;
// wire pre_dout_stb = dly_over && seq_bit[0] && (bits_left == 0);
// assign ready = !busy_r; // assign ready = !busy_r;
assign ready = !busy_w; assign ready = !busy_w;
assign is_open = is_open_r; assign is_open = is_open_r;
assign dout = sr; // assign dout = sr;
always @ (posedge mclk) begin always @ (posedge mclk) begin
active_sda_was_0 <= !sda || rcv_r; active_sda_was_0 <= !sda || rcv_r;
if (snd9_w) rcv_r <= rcv; if (snd9_w) rcv_r <= rcv;
early_release_r <= early_release_0 && !rcv_r && (bits_left == 1); // only before ACN during master send
// disable active_sda in send messages for the last (ACKN) bit, for the receive - all but ACKN // disable active_sda in send messages for the last (ACKN) bit, for the receive - all but ACKN
if (snd9_w) active_sda_r <= active_sda && !rcv; if (snd9_w) active_sda_r <= active_sda && !rcv;
else if (snd_start_w || snd_stop_w) active_sda_r <= active_sda; else if (snd_start_w || snd_stop_w) active_sda_r <= active_sda;
...@@ -123,7 +127,10 @@ module sensor_i2c_scl_sda( ...@@ -123,7 +127,10 @@ module sensor_i2c_scl_sda(
if (snd9_w) sr <= din; if (snd9_w) sr <= din;
else if (dly_over && seq_bit[0]) sr <= {sr[7:0], sda_r}; else if (dly_over && seq_bit[0]) sr <= {sr[7:0], sda_r};
dout_stb <= dly_over && seq_bit[0] && (bits_left == 0); dout_stb <= dly_over && seq_bit[0] && (bits_left == 0) && rcv_r;
// dout_stb <= pre_dout_stb;
// if (pre_dout_stb) dout <= {sr[7:0],sda_r};
if (done_r) dout <= {sr[7:0],sda_r};
if (rst) is_open_r <= 0; if (rst) is_open_r <= 0;
else if (dly_over && seq_start_restart[0]) is_open_r <= 1; else if (dly_over && seq_start_restart[0]) is_open_r <= 1;
...@@ -153,7 +160,8 @@ module sensor_i2c_scl_sda( ...@@ -153,7 +160,8 @@ module sensor_i2c_scl_sda(
(|seq_start_restart[1:0]) || (|seq_start_restart[1:0]) ||
(|seq_stop[2:1]) || (|seq_stop[2:1]) ||
(!sr[8] && (|seq_bit[3:1])) || (!sr[8] && (|seq_bit[3:1])) ||
(!sr[8] && seq_bit[0] && (!early_release_0 || !sr[7]))); // (!sr[8] && seq_bit[0] && (!early_release_0 || !sr[7])));
(!sr[8] && seq_bit[0] && (!early_release_r || !sr[7])));
bus_busy <= busy_r; bus_busy <= busy_r;
end end
......
This diff is collapsed.
...@@ -2910,7 +2910,9 @@ task test_i2c_353; ...@@ -2910,7 +2910,9 @@ task test_i2c_353;
set_sensor_i2c_command (chn, 0, 3, 0, 0, 0); // run i2c set_sensor_i2c_command (chn, 0, 3, 0, 0, 0); // run i2c
write_sensor_i2c (chn, 1, 0,'h90050922); write_sensor_i2c (chn, 1, 0,'h90050922);
for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 0, i+ 'h12); for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 0, i+ 'h12);
write_sensor_i2c (chn, 1, 0,'h91901234); write_sensor_i2c (chn, 1, 0,'h91900004);
//write_sensor_i2c 0 1 0 0x91900004
//read_sensor_i2c 0
write_sensor_i2c ( write_sensor_i2c (
chn, // input [1:0] num_sensor; chn, // input [1:0] num_sensor;
......
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