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Commit 642b83c6 authored by Andrey Filippov's avatar Andrey Filippov
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verified hardware to work with the new i2c sequencer, compatible with SMIA sensors

parent a6281669
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Showing with 67148 additions and 67187 deletions
.project
View file @ 642b83c6
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150923220008330.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150923220435209.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
fpga_version.vh
View file @ 642b83c6
parameter FPGA_VERSION = 32'h0393003a;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930042;
\ No newline at end of file
py393/dbg/x393_mcntrl.pickle
View file @ 642b83c6
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/vrlg.py
View file @ 642b83c6
......@@ -158,7 +158,6 @@ TABLE_CORING_INDEX = int
DQSTRI_LAST = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
STATUS_2LSB_SHFT__TYPE = str
SENS_SS_EN__TYPE = str
MEMBRIDGE_LEN64__TYPE = str
TABLE_QUANTIZATION_INDEX__TYPE = str
LOGGER_CONF_EN__RAW = str
......@@ -198,12 +197,14 @@ DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_LOAD__RAW = str
WINDOW_Y0__RAW = str
CMPRS_STATUS_CNTRL = int
SENSI2C_CMD_ACIVE_SDA__RAW = str
CLK_STATUS_REG_ADDR__RAW = str
CMPRS_CSAT_CB_BITS__TYPE = str
SENSI2C_SLEW__TYPE = str
MEMBRIDGE_WIDTH64__RAW = str
LOGGER_CONF_MSG_BITS__RAW = str
SENS_GAMMA_MODE_REPET = int
SENSI2C_TBL_DLY__RAW = str
CLKFBOUT_MULT_REF = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC = int
......@@ -230,16 +231,17 @@ RTC_SET_USEC = int
RTC_BITC_PREDIV__TYPE = str
LD_DLY_CMDA = int
DLY_SET__RAW = str
DFLT_REFRESH_ADDR__RAW = str
SENSI2C_CMD_TABLE = int
MCNTRL_PS_ADDR__RAW = str
NUM_FRAME_BITS__RAW = str
SENSI2C_CMD_ACIVE__RAW = str
LOGGER_CONF_GPS__TYPE = str
HIST_SAXI_EN__RAW = str
SENSOR_16BIT_BIT__RAW = str
HIST_SAXI_AWCACHE__TYPE = str
SENSI2C_CMD_RUN_PBITS__TYPE = str
LOGGER_CONF_SYN_BITS__TYPE = str
SENS_LENS_FAT0_OUT__RAW = str
GPIO_ADDR__TYPE = str
CAMSYNC_TRIG_SRC = int
CLKOUT_DIV_PCLK__TYPE = str
LOGGER_PAGE_IMU = int
......@@ -270,9 +272,11 @@ DLY_DQS_IDELAY__TYPE = str
CLK_PHASE = float
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCONTR_SENS_STATUS_BASE__TYPE = str
SENSI2C_CMD_TAND__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str
MAX_TILE_HEIGHT = int
BUF_CLK1X_PCLK = str
......@@ -301,13 +305,11 @@ SENS_SYNC_MULT__TYPE = str
NUM_CYCLES_27__RAW = str
SENSI2C_IOSTANDARD__RAW = str
SCANLINE_EXTRA_PAGES__TYPE = str
MCONTR_SENS_BASE__RAW = str
CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_AFIMUX_MASK__TYPE = str
MCONTR_SENS_INC = int
CAMSYNC_TRIG_PERIOD__TYPE = str
DFLT_DQS_PATTERN = int
SENSI2C_CMD_SCL__TYPE = str
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
SLEW_CLK = str
......@@ -359,6 +361,7 @@ LD_DLY_LANE1_IDELAY = int
SENS_SYNC_MASK = int
DIVCLK_DIVIDE = int
CMD_PAUSE_BITS__RAW = str
SENSI2C_TBL_DLY_BITS = int
IDELAY_VALUE__RAW = str
MCONTR_CMPRS_STATUS_BASE = int
BUFFER_DEPTH32 = int
......@@ -377,7 +380,6 @@ LOGGER_CONF_SYN_BITS__RAW = str
CAMSYNC_ADDR__TYPE = str
DIVCLK_DIVIDE_AXIHP__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
SENSI2C_CMD_SCL__RAW = str
MULT_SAXI_BSLOG1__TYPE = str
LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_ADDR = int
......@@ -399,7 +401,6 @@ NUM_CYCLES_20 = int
NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
SENSI2C_CMD_BYTES_PBITS__TYPE = str
CMDFRAMESEQ_REL__TYPE = str
PICKLE = str
AFI_SIZE64__TYPE = str
......@@ -439,8 +440,7 @@ CMPRS_CORING_MODE = int
DIVCLK_DIVIDE_SYNC__TYPE = str
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
SENSI2C_CMD_SCL_WIDTH = int
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
FFCLK1_IOSTANDARD = str
MCNTRL_TILED_MASK = int
SENSIO_JTAG__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
......@@ -452,8 +452,9 @@ LOGGER_CONF_DBG_BITS__RAW = str
FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
CLKFBOUT_MULT_SYNC = int
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long
GPIO_PORTEN__RAW = str
SENS_LENS_C = int
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
......@@ -462,6 +463,7 @@ TABLE_HUFFMAN_INDEX = int
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
SENSI2C_TBL_RNWREG__RAW = str
RTC_SEC_USEC_ADDR = int
LOGGER_CONF_DBG = int
CAMSYNC_EN_BIT__TYPE = str
......@@ -472,7 +474,7 @@ MCLK_PHASE__TYPE = str
DIVCLK_DIVIDE_XCLK__RAW = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
GPIO_SET_STATUS = int
MCONTR_BUF2_WR_ADDR__TYPE = str
GPIO_SLEW__TYPE = str
SENS_LENS_BX__RAW = str
TEST_INITIAL_BURST = int
......@@ -523,7 +525,6 @@ SENSOR_FIFO_DELAY__RAW = str
DLY_SET = int
CMDFRAMESEQ_CTRL__TYPE = str
NUM_CYCLES_12 = int
SENSI2C_CMD_DLY = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str
NUM_CYCLES_11 = int
......@@ -551,12 +552,14 @@ NUM_CYCLES_16 = int
NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int
GPIO_PORTEN__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
CLKFBOUT_DIV_REF__RAW = str
CMD_PAUSE_BITS = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
SENSIO_STATUS_REG_REL = int
SENSI2C_TBL_SA__TYPE = str
BUF_IPCLK_SENS3__TYPE = str
MCNTRL_TILED_MODE = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
......@@ -569,10 +572,9 @@ MCONTR_PHY_0BIT_CKE_EN__RAW = str
NUM_CYCLES_26__TYPE = str
PICKLE__RAW = str
DQSTRI_LAST__RAW = str
SENSI2C_CMD_DLY_PBITS__TYPE = str
WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int
GPIO_IOSTANDARD__TYPE = str
MULT_SAXI_CNTRL_ADDR = int
FFCLK1_IBUF_LOW_PWR = str
HIST_SAXI_ADDR_REL__RAW = str
CMPRS_CBIT_CMODE_MONO4__TYPE = str
......@@ -597,6 +599,7 @@ MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
SENS_REFCLK_FREQUENCY__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
MULT_SAXI_ADV_WR__RAW = str
LOGGER_PAGE_GPS = int
......@@ -615,6 +618,7 @@ PXD_DRIVE__TYPE = str
HIST_SAXI_NRESET = int
MULT_SAXI_HALF_BRAM_IN__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
DFLT_DQM_PATTERN__RAW = str
GPIO_SET_STATUS__RAW = str
......@@ -665,7 +669,6 @@ SENS_LENS_FAT0_OUT_MASK__TYPE = str
SENSI2C_ABS_RADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
WBUF_DLY_WLV__TYPE = str
SENS_JTAG_TMS__TYPE = str
MEMBRIDGE_WIDTH64__TYPE = str
MCONTR_TOP_16BIT_CHN_EN = int
BUF_IPCLK2X_SENS1__TYPE = str
......@@ -675,6 +678,7 @@ MULT_SAXI_AWCACHE = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__RAW = str
SENSI2C_TBL_RAH__RAW = str
CMPRS_CSAT_CR_BITS__TYPE = str
NUM_CYCLES_05 = int
NUM_CYCLES_06 = int
......@@ -691,17 +695,17 @@ MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
SENS_SYNC_LBITS = int
STATUS_DEPTH__RAW = str
NUM_CYCLES_25__TYPE = str
SENSI2C_CMD_DLY_PBITS__RAW = str
MCONTR_LINTILE_REPEAT = int
CHNBUF_READ_LATENCY = int
SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str
TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
SENSI2C_CMD_RESET__RAW = str
REFRESH_OFFSET = int
MCNTRL_PS_EN_RST = int
MCNTRL_TILED_TILE_WHS = int
MCONTR_SENS_BASE__RAW = str
SENS_GAMMA_ADDR_MASK__TYPE = str
CMPRS_CSAT_CR = int
CMPRS_CBIT_RUN_ENABLE = int
......@@ -721,12 +725,12 @@ BUF_CLK1X_SYNC__RAW = str
SENS_JTAG_PGMEN__TYPE = str
MEMBRIDGE_LEN64__RAW = str
MCONTR_LINTILE_EN = int
DFLT_REFRESH_ADDR__RAW = str
GPIO_N = int
MCONTR_ARBIT_ADDR_MASK__TYPE = str
SENS_CTRL_MRST__TYPE = str
FFCLK0_IBUF_LOW_PWR__TYPE = str
FFCLK1_DQS_BIAS__TYPE = str
SENSI2C_CMD_SDA_WIDTH = int
SENS_GAMMA_RADDR = int
NUM_CYCLES_14__RAW = str
CMPRS_AFIMUX_MASK__RAW = str
......@@ -738,7 +742,7 @@ MCONTR_CMPRS_BASE__TYPE = str
TEST01_SUSPEND__TYPE = str
SENS_LENS_POST_SCALE = int
LOGGER_STATUS_REG_ADDR__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
SS_MODE = str
MCONTR_CMD_WR_ADDR__RAW = str
CMDFRAMESEQ_CTRL = int
DLY_LD__TYPE = str
......@@ -763,6 +767,7 @@ SENS_LENS_AY = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
HISTOGRAM_RAM_MODE__RAW = str
SENS_LENS_AX_MASK__RAW = str
SENSI2C_TBL_SA_BITS = int
CMPRS_FRMT_MBCM1__TYPE = str
SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR = int
......@@ -777,6 +782,7 @@ CMPRS_FRMT_LMARG_BITS = int
CMDSEQMUX_ADDR = int
CLKOUT_DIV_AXIHP = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR = int
DLY_DQS_IDELAY__RAW = str
CONTROL_RBACK_ADDR_MASK__TYPE = str
MCONTR_BUF4_WR_ADDR = int
......@@ -786,7 +792,8 @@ CMPRS_CBIT_DCSUB_BITS = int
MCONTR_TOP_16BIT_ADDR_MASK = int
PXD_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_REPEAT__TYPE = str
GPIO_ADDR__TYPE = str
HIST_SAXI_MODE_WIDTH__TYPE = str
SENS_LENS_FAT0_OUT__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
......@@ -801,6 +808,7 @@ MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
TILE_HEIGHT__RAW = str
MEMBRIDGE_MODE__RAW = str
SENSI2C_TBL_SA_BITS__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
READ_BLOCK_OFFSET__RAW = str
HISTOGRAM_LEFT_TOP__TYPE = str
......@@ -820,13 +828,12 @@ SENSIO_CTRL__TYPE = str
SENSIO_WIDTH__RAW = str
CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
SENSI2C_CMD_SDA_WIDTH__TYPE = str
MCNTRL_PS_STATUS_CNTRL = int
CLKOUT_DIV_SYNC = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
MCONTR_BUF4_RD_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
T_RFC__TYPE = str
MCONTR_LINTILE_NRESET__TYPE = str
SENS_NUM_SUBCHN__RAW = str
......@@ -838,6 +845,7 @@ READ_PATTERN_OFFSET__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
MAX_TILE_WIDTH__TYPE = str
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
REF_JITTER1 = float
CMDSEQMUX_STATUS = int
TILE_WIDTH = int
......@@ -855,13 +863,13 @@ LOGGER_CONF_EN__TYPE = str
LOGGER_PAGE_IMU__RAW = str
SENS_SYNC_MINPER__RAW = str
CMPRS_AFIMUX_MODE__RAW = str
SENSI2C_TBL_RAH_BITS = int
SENS_SYNC_LATE__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
CHNBUF_READ_LATENCY__TYPE = str
CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str
RTC_MHZ__RAW = str
SENSI2C_CMD_BYTES_PBITS__RAW = str
TEST_INITIAL_BURST__TYPE = str
NUM_CYCLES_19__RAW = str
MCNTRL_PS_MASK__RAW = str
......@@ -888,7 +896,7 @@ MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
SS_EN__TYPE = str
SENS_GAMMA_MODE_BAYER__TYPE = str
SENSI2C_TBL_RNWREG__TYPE = str
FRAME_START_ADDRESS_INC = int
TILED_STARTY = int
MEMBRIDGE_MODE__TYPE = str
......@@ -902,6 +910,8 @@ LD_DLY_LANE0_ODELAY = int
FFCLK1_IBUF_DELAY_VALUE__RAW = str
CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
SENSI2C_CMD_TAND = int
MEMBRIDGE_SIZE64 = int
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int
......@@ -935,6 +945,7 @@ CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CBIT_RUN__RAW = str
SENS_GAMMA_RADDR__RAW = str
SENS_CTRL_EXT_CLK = int
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
GPIO_SET_PINS__RAW = str
......@@ -989,19 +1000,20 @@ CMPRS_CBIT_RUN__TYPE = str
SENS_LENS_FAT0_OUT = int
MCNTRL_SCANLINE_FRAME_SIZE = int
STATUS_DEPTH = int
SENSI2C_CMD_SCL = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
BUF_CLK1X_XCLK2X__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
SENSI2C_CMD_BYTES = int
HIST_SAXI_MODE_WIDTH__TYPE = str
SENSI2C_TBL_NBRD__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
MCONTR_CMPRS_INC__RAW = str
CMPRS_HIFREQ_REG_INC__RAW = str
SENSOR_DATA_WIDTH__RAW = str
SENSI2C_TBL_DLY_BITS__TYPE = str
MEMBRIDGE_MASK = int
SENSI2C_TBL_NBWR_BITS__TYPE = str
DLY_SET__TYPE = str
CMPRS_STATUS_REG_INC = int
FFCLK0_CAPACITANCE__TYPE = str
......@@ -1016,6 +1028,7 @@ IPCLK2X_PHASE = float
CMPRS_CBIT_FOCUS_BITS = int
LOGGER_CONF_SYN__RAW = str
CMPRS_COLOR20 = int
SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
......@@ -1042,7 +1055,7 @@ STATUS_2LSB_SHFT = int
CMPRS_CBIT_CMODE_JP4DC = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENS_SYNC_MINBITS = int
MCNTRL_SCANLINE_WINDOW_STARTXY = int
BUF_IPCLK_SENS2__RAW = str
......@@ -1055,11 +1068,10 @@ SENSIO_DELAYS__RAW = str
CMDFRAMESEQ_RUN_BIT = int
SENS_SYNC_MINPER = int
CMPRS_FRMT_MBRM1__RAW = str
DFLT_CHN_EN__TYPE = str
MCONTR_SENS_BASE__TYPE = str
LOGGER_BIT_HALF_PERIOD = int
CMPRS_CBIT_CMODE_JP4 = int
CAMSYNC_TRIGGERED_BIT = int
SENSI2C_CMD_SDA__TYPE = str
LOGGER_PAGE_IMU__TYPE = str
LOGGER_PAGE_GPS__RAW = str
SENS_PHASE_WIDTH__TYPE = str
......@@ -1092,7 +1104,7 @@ TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
SENS_PCLK_PERIOD__RAW = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
GPIO_SET_PINS = int
......@@ -1118,7 +1130,7 @@ DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
CAMSYNC_TRIG_PERIOD__RAW = str
SENS_BANDWIDTH__RAW = str
SENSI2C_CMD_DLY_PBITS = int
SENS_SS_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
LOGGER_PERIOD__TYPE = str
WSEL = int
......@@ -1153,6 +1165,7 @@ DLY_LANE1_ODELAY__TYPE = str
CMPRS_AFIMUX_WIDTH__TYPE = str
TILE_VSTEP__RAW = str
CMPRS_CBIT_QBANK = int
SENSI2C_TBL_RAH_BITS__TYPE = str
CMPRS_AFIMUX_WIDTH = int
HISTOGRAM_ADDR_MASK__TYPE = str
HISTOGRAM_RADDR3__TYPE = str
......@@ -1162,6 +1175,7 @@ CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str
CMPRS_CBIT_BAYER__RAW = str
DFLT_DQS_TRI_OFF_PATTERN = int
......@@ -1178,6 +1192,7 @@ SENSOR_MODE_WIDTH = int
RTC_BITC_PREDIV__RAW = str
CMPRS_CORING_BITS__TYPE = str
STATUS_DEPTH__TYPE = str
SENSI2C_TBL_RAH__TYPE = str
CMPRS_AFIMUX_CYCBITS__TYPE = str
SENS_SS_EN__RAW = str
SENS_LENS_ADDR_MASK = int
......@@ -1265,6 +1280,7 @@ BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
FFCLK0_IFD_DELAY_VALUE = str
SENSI2C_TBL_NABRD = int
SLEW_CMDA__TYPE = str
NUM_CYCLES_19__TYPE = str
CMPRS_CORING_MODE__RAW = str
......@@ -1288,7 +1304,6 @@ AXI_RD_ADDR_BITS = int
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
TEST01_START_FRAME__TYPE = str
SENSI2C_CMD_SCL_WIDTH__TYPE = str
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
RTC_SEC_USEC_ADDR__TYPE = str
......@@ -1345,11 +1360,13 @@ SLEW_DQS = str
MCONTR_WR_MASK = int
CMPRS_FRMT_MBCM1 = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str
CMPRS_FRMT_LMARG = int
FFCLK0_IBUF_DELAY_VALUE__TYPE = str
CMPRS_TIMEOUT__RAW = str
MEMCLK_IBUF_LOW_PWR__RAW = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENSI2C_CMD_FIFO_RD__RAW = str
CMPRS_STATUS_REG_INC__TYPE = str
RTC_ADDR__TYPE = str
SENSI2C_ABS_RADDR = int
......@@ -1363,6 +1380,7 @@ CMDSEQMUX_ADDR__RAW = str
DLY_DM_ODELAY__TYPE = str
SENSIO_CTRL = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
CLKIN_PERIOD_SYNC__RAW = str
SENS_PCLK_PERIOD = float
SCANLINE_STARTY__RAW = str
......@@ -1379,8 +1397,8 @@ SENSOR_FIFO_DELAY__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
IDELAY_VALUE__TYPE = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
SENSI2C_CMD_SDA = int
PICKLE__TYPE = str
SENSI2C_TBL_NBWR__RAW = str
TABLE_FOCUS_INDEX__RAW = str
SENSOR_MODE_WIDTH__TYPE = str
MCONTR_LINTILE_WRITE__RAW = str
......@@ -1393,12 +1411,11 @@ CMPRS_MONO8__TYPE = str
NUM_CYCLES_00__RAW = str
IPCLK_PHASE__RAW = str
SENSI2C_CTRL = int
SENSI2C_CMD_DLY__RAW = str
MEMCLK_IBUF_DELAY_VALUE__RAW = str
SENS_SYNC_MULT = int
CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
MCNTRL_TILED_TILE_WHS = int
CLKOUT_DIV_XCLK__RAW = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
......@@ -1408,7 +1425,6 @@ CMDFRAMESEQ_ADDR_BASE = int
CMPRS_AFIMUX_RADDR1 = int
CMPRS_AFIMUX_RADDR0 = int
CMPRS_FRMT_MBCM1_BITS__RAW = str
SENSI2C_CMD_SDA__RAW = str
CMPRS_AFIMUX_REG_ADDR1__TYPE = str
CMPRS_CBIT_FRAMES__TYPE = str
MCONTR_TOP_0BIT_ADDR = int
......@@ -1464,6 +1480,7 @@ MULT_SAXI_CNTRL_ADDR__TYPE = str
MULT_SAXI_STATUS_REG__TYPE = str
MEMCLK_IOSTANDARD__TYPE = str
NUM_CYCLES_27__TYPE = str
SENSI2C_TBL_NBRD = int
CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
MULT_SAXI_STATUS_REG = int
......@@ -1514,6 +1531,7 @@ CLK_STATUS__TYPE = str
CMPRS_COLOR20__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
RTC_MASK = int
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
HIST_SAXI_ADDR_REL__TYPE = str
......@@ -1572,6 +1590,7 @@ GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
RTC_SET_CORR__RAW = str
SENSI2C_TBL_RAH_BITS__RAW = str
TILED_STARTY__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
DFLT_DQM_PATTERN__TYPE = str
......@@ -1581,7 +1600,6 @@ MCONTR_PHY_0BIT_CMDA_EN = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
MCNTRL_TEST01_CHN4_MODE = int
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
MAX_TILE_WIDTH = int
TABLE_FOCUS_INDEX = int
CMPRS_CBIT_RUN_STANDALONE__RAW = str
......@@ -1595,7 +1613,6 @@ INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
SENSI2C_CMD_BYTES_PBITS = int
CAMSYNC_TRIG_DST__RAW = str
CLKIN_PERIOD_XCLK__TYPE = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
......@@ -1607,7 +1624,7 @@ HIST_SAXI_MODE_ADDR_REL__RAW = str
CLKOUT_DIV_XCLK2X__TYPE = str
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
SENSI2C_STATUS_REG_BASE = int
SENSI2C_TBL_NBWR_BITS = int
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS0 = str
......@@ -1624,12 +1641,13 @@ MULT_SAXI_HALF_BRAM__TYPE = str
SENSOR_CTRL_ADDR_MASK = int
NUM_CYCLES_16__TYPE = str
DIVCLK_DIVIDE_XCLK__TYPE = str
SS_MODE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
CMDFRAMESEQ_MASK__RAW = str
SENS_CTRL_LD_DLY__TYPE = str
MCONTR_TOP_16BIT_ADDR__TYPE = str
PXD_SLEW = str
MCONTR_CMPRS_BASE__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
TEST01_SUSPEND = int
NUM_FRAME_BITS = int
LOGGER_STATUS_REG_ADDR__RAW = str
......@@ -1637,12 +1655,13 @@ CMPRS_CBIT_FRAMES_BITS__RAW = str
MCNTRL_TILED_MASK__TYPE = str
DEBUG_MASK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN = int
SENSI2C_CMD_ACIVE = int
CMPRS_FRMT_LMARG__TYPE = str
SENSI2C_TBL_NBRD_BITS = int
SENSIO_JTAG = int
DLY_LD = int
CMPRS_CBIT_FRAMES_SINGLE = int
SENS_SYNC_LATE = int
CMPRS_TABLES__RAW = str
CMDFRAMESEQ_CTRL__RAW = str
SENSIO_DELAYS = int
MCONTR_BUF0_RD_ADDR__TYPE = str
......@@ -1682,18 +1701,20 @@ DFLT_DQ_TRI_ON_PATTERN__RAW = str
CONTROL_ADDR_MASK = int
LOGGER_PERIOD = int
MCONTR_BUF0_WR_ADDR = int
SENSI2C_CMD_SCL_WIDTH__RAW = str
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
LOGGER_STATUS_MASK__RAW = str
RTC_ADDR__RAW = str
CMPRS_CBIT_FOCUS_BITS__RAW = str
CMDFRAMESEQ_RUN_BIT__TYPE = str
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
SENSI2C_CTRL__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
MCONTR_BUF2_WR_ADDR__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG1 = int
MULT_SAXI_BSLOG2 = int
MULT_SAXI_BSLOG3 = int
MCONTR_BUF4_RD_ADDR__RAW = str
SENS_SS_MOD_PERIOD = int
DQSTRI_FIRST = int
SENS_REF_JITTER2__RAW = str
......@@ -1705,6 +1726,7 @@ DIVCLK_DIVIDE_PCLK = int
MCNTRL_PS_MASK = int
SENSI2C_STATUS__TYPE = str
CMPRS_CSAT_CB_BITS = int
SENSI2C_TBL_NBRD__RAW = str
SENSI2C_IOSTANDARD = str
GPIO_IOSTANDARD = str
MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
......@@ -1756,16 +1778,16 @@ NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
CLKOUT_DIV_SYNC__TYPE = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
SENSIO_RADDR__RAW = str
MCONTR_SENS_BASE__TYPE = str
DFLT_CHN_EN__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCLK_PHASE = float
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
BUF_CLK1X_XCLK__TYPE = str
SENSI2C_CMD_DLY__TYPE = str
MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
......@@ -1823,6 +1845,7 @@ DLY_LANE0_DQS_WLV_IDELAY = long
MCNTRL_SCANLINE_STATUS_CNTRL = int
CMDSEQMUX_MASK__TYPE = str
TILED_STARTY__RAW = str
SENSI2C_TBL_NABRD__TYPE = str
NUM_CYCLES_01__RAW = str
WINDOW_HEIGHT__RAW = str
GPIO_IBUF_LOW_PWR = str
......@@ -1833,7 +1856,9 @@ MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
LOGGER_CONF_DBG__TYPE = str
AFI_SIZE64__RAW = str
SENSI2C_TBL_RNWREG = int
STATUS_PSHIFTER_RDY_MASK = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENS_LENS_C_MASK__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
CMPRS_CSAT_CB__RAW = str
......@@ -1865,6 +1890,7 @@ SENSIO_WIDTH = int
MCONTR_PHY_0BIT_DLY_RST__RAW = str
BUF_CLK1X_PCLK2X__RAW = str
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
SENSI2C_TBL_RAH = int
SENSI2C_ADDR_MASK__RAW = str
SENS_HIGH_PERFORMANCE_MODE__TYPE = str
MCONTR_LINTILE_KEEP_OPEN__TYPE = str
......@@ -1887,6 +1913,7 @@ DLY_DQ_IDELAY__RAW = str
SENSOR_CTRL_RADDR__RAW = str
CMPRS_MONO16 = int
CMPRS_CSAT_CB__TYPE = str
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
CLKIN_PERIOD_AXIHP__RAW = str
SENS_LENS_BX_MASK = int
......@@ -1894,7 +1921,7 @@ DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
FFCLK1_IOSTANDARD = str
SENS_JTAG_TMS__TYPE = str
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
......@@ -1906,7 +1933,6 @@ SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_31__TYPE = str
SENSI2C_CMD_BYTES__RAW = str
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
BUF_IPCLK_SENS2__TYPE = str
SENS_GAMMA_BUFFER = int
......@@ -1936,11 +1962,13 @@ DLY_DQS_ODELAY = long
SENSOR_CHN_EN_BIT__RAW = str
SENS_SS_MODE__TYPE = str
CAMSYNC_TRIG_SRC__TYPE = str
SENSI2C_CMD_FIFO_RD = int
LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
PHASE_CLK2X_XCLK__RAW = str
SS_EN = str
CLKFBOUT_MULT_XCLK = int
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
......@@ -1955,7 +1983,6 @@ NUM_CYCLES_11__RAW = str
FFCLK1_CAPACITANCE__RAW = str
SENSI2C_DRIVE__RAW = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENS_LENS_C = int
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int
......@@ -1970,23 +1997,25 @@ SCANLINE_STARTY__TYPE = str
SENS_LENS_SCALES_MASK = int
LOGGER_PAGE_MSG__TYPE = str
CAMSYNC_MASK__RAW = str
SENSOR_BASE_INC__TYPE = str
RTC_MHZ__TYPE = str
MEMBRIDGE_START64 = int
MEMBRIDGE_LO_ADDR64 = int
CMPRS_AFIMUX_EN__TYPE = str
CMPRS_BASE_INC__TYPE = str
SENSI2C_CMD_ACIVE__TYPE = str
NUM_FRAME_BITS__TYPE = str
CLKFBOUT_MULT_SENSOR__TYPE = str
CLKFBOUT_MULT_REF__TYPE = str
SENSI2C_TBL_SA = int
SENSI2C_CTRL_MASK__RAW = str
CLK_CNTRL = int
SENSI2C_TBL_NABRD__RAW = str
BUF_CLK1X_AXIHP__RAW = str
LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
CLKOUT_DIV_AXIHP__RAW = str
SENS_PCLK_PERIOD__RAW = str
CLK_DIV_PHASE__TYPE = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
......@@ -2012,7 +2041,7 @@ MCONTR_SENS_INC__RAW = str
MULT_SAXI_WLOG__RAW = str
TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
RTC_MASK = int
SENSI2C_CMD_ACIVE_EARLY0 = int
MCNTRL_TEST01_MASK = int
MEMCLK_IBUF_DELAY_VALUE__TYPE = str
SENS_GAMMA_CTRL__TYPE = str
......@@ -2022,6 +2051,7 @@ LD_DLY_LANE1_IDELAY__RAW = str
MEMBRIDGE_STATUS_REG__RAW = str
CMDFRAMESEQ_DEPTH__RAW = str
SENS_LENS_BX_MASK__RAW = str
SENSI2C_TBL_NBWR_BITS__RAW = str
WRITE_BLOCK_OFFSET__RAW = str
FFCLK0_DQS_BIAS__RAW = str
MCONTR_LINTILE_SINGLE__RAW = str
......@@ -2033,7 +2063,7 @@ MCNTRL_PS_MASK__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
MCONTR_LINTILE_BYTE32__TYPE = str
FFCLK1_IFD_DELAY_VALUE = str
MULT_SAXI_CNTRL_ADDR = int
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
FRAME_START_ADDRESS__TYPE = str
CLK_MASK = int
......@@ -2045,6 +2075,7 @@ SENS_GAMMA_BUFFER__RAW = str
MULT_SAXI_AWCACHE__TYPE = str
NUM_CYCLES_05__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR__TYPE = str
AXI_WR_ADDR_BITS = int
CLKFBOUT_MULT_XCLK__TYPE = str
FFCLK1_IBUF_LOW_PWR__RAW = str
......@@ -2066,10 +2097,9 @@ SENS_LENS_AY__RAW = str
MULT_SAXI_WLOG = int
DLY_CMDA_ODELAY__RAW = str
SENSOR_GROUP_ADDR__TYPE = str
SENSI2C_CMD_SDA_WIDTH__RAW = str
MCONTR_BUF2_RD_ADDR = int
MCNTRL_TILED_FRAME_SIZE = int
MCONTR_BUF2_WR_ADDR__TYPE = str
GPIO_SET_STATUS = int
CLKOUT_DIV_PCLK2X = int
MULT_SAXI_ADDR = int
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
......@@ -2082,7 +2112,7 @@ GPIO_DRIVE = int
SENS_LENS_SCALES = int
CONTROL_ADDR_MASK__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
SENSI2C_CMD_BYTES__TYPE = str
SENSOR_BASE_INC__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
SENS_DIVCLK_DIVIDE__TYPE = str
LOGGER_CONF_MSG_BITS = int
......
py393/x393_jpeg.py
View file @ 642b83c6
......@@ -937,4 +937,33 @@ compressor_control all None 1
compressor_control all None 0
mem_save "/usr/local/verilog/memdump_chn0" 0x27a00000 0x01001000
write_sensor_i2c 0 1 0 0x91900004
read_sensor_i2c 0
set_sensor_i2c_table_reg_wr 0 0x00 0x48 3 100 1
set_sensor_i2c_table_reg_wr 0 0x90 0x48 3 100 1
set_sensor_i2c_table_reg_rd 0 0x01 0 2 100 1
set_sensor_i2c_table_reg_rd 0 0x91 0 2 100 1
========
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl 0 None None None None None 0 0x4
set_sensor_io_ctl 1 None None None None None 0 0xe
set_sensor_io_ctl 2 None None None None None 0 0x4
set_sensor_io_ctl 3 None None None None None 0 0xe
compressor_control all None None None None None 3
program_gamma all 0 0.57 0.04
write_sensor_i2c all 1 0 0x90350009
write_sensor_i2c all 1 0 0x902c000f
write_sensor_i2c all 1 0 0x902d000a
write_sensor_i2c all 1 0 0x90040a23
axi_write_single_w 0x696 0x079800a3
axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
r
"""
py393/x393_sens_cmprs.py
View file @ 642b83c6
......@@ -734,20 +734,56 @@ class X393SensCmprs(object):
self.x393Sensor.print_status_sensor_i2c (num_sensor = num_sensor)
if verbose >0 :
print ("===================== AFI_MUX_SETUP =========================")
print ("===================== I2C_SETUP =========================")
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = True)
rst_cmd = True,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
active_sda = True,
early_release_0 = True,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
dly = 100, # ??None, # 20 ns per 1 of cycle duration. Standard i2c - dly = 125
scl_ctl = None,
sda_ctl = None)
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 1,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
# aliases for indices 0x90 and 0x91
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = 0x90,
slave_addr = 0x48,
rah = 0,
num_bytes = 3,
bit_delay = 100,
verbose = verbose)
self.x393Sensor.set_sensor_i2c_table_reg_rd (
num_sensor = num_sensor,
page = 0x91,
two_byte_addr = 0,
num_bytes_rd = 2,
bit_delay = 100,
verbose = verbose)
# Turn off reset (is it needed?)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = False)
# Turn on sequencer
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
run_cmd = True)
......
py393/x393_sensor.py
View file @ 642b83c6
......@@ -37,9 +37,10 @@ import x393_axi_control_status
import x393_utils
#import time
import time
import vrlg
import x393_mcntrl
class X393Sensor(object):
DRY_MODE= True # True
DEBUG_MODE=1
......@@ -190,55 +191,80 @@ class X393Sensor(object):
def func_sensor_i2c_command (self,
rst_cmd = False,
run_cmd = None,
num_bytes = None,
dly = None,
scl_ctl = None,
sda_ctl = None):
active_sda = None,
early_release_0 = None,
advance_FIFO = None,
verbose = 1):
"""
@param rst_cmd - reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
@param run_cmd - True - run i2c, False - stop i2c (needed before software i2c), None - no change
@param num_bytes - set number of i2c bytes after slave address (0..3), None - no change
@param dly - set duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA??? obsolete)
@param scl_ctl - directly control SCL line: None - NOP, 'Z' - high Z, 0/False/'L' - low level,
1/True/'H' - high level
@param sda_ctl - directly control SDA line: None - NOP, 'Z' - high Z, 0/False/'L' - low level,
1/True/'H' - high level
@return: i2c control word
"""
print ("func_sensor_i2c_command(): rst_cmd= ",rst_cmd,", run_cmd=",run_cmd,", num_bytes = ",num_bytes,", dly = ",dly)
@param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible
@param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup)
@param advance_FIFO - advance i2c read FIFO
@param verbose - verbose level
@return combined command word.
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
"""
if verbose>0:
print ("func_sensor_i2c_command(): rst_cmd= ",rst_cmd,", run_cmd=",run_cmd,", active_sda = ",active_sda,", early_release_0 = ",early_release_0)
rslt = 0
rslt |= (0,1)[rst_cmd] << vrlg.SENSI2C_CMD_RESET
if not run_cmd is None:
rslt |= 1 << vrlg.SENSI2C_CMD_RUN
rslt |= (0,1)[run_cmd] << (vrlg.SENSI2C_CMD_RUN - vrlg.SENSI2C_CMD_RUN_PBITS)
if not num_bytes is None:
num_bytes &= (1 << vrlg.SENSI2C_CMD_BYTES_PBITS) -1
rslt |= 1 << vrlg.SENSI2C_CMD_BYTES
rslt |= num_bytes << (vrlg.SENSI2C_CMD_BYTES - vrlg.SENSI2C_CMD_BYTES_PBITS)
if not dly is None:
dly &= (1 << vrlg.SENSI2C_CMD_DLY_PBITS) -1
rslt |= 1 << vrlg.SENSI2C_CMD_DLY
rslt |= dly << (vrlg.SENSI2C_CMD_DLY - vrlg.SENSI2C_CMD_DLY_PBITS)
print ("func_sensor_i2c_command(): dly = ",dly," rslt=",rslt)
scl=0
if not scl_ctl is None:
if (scl_ctl is False) or (scl_ctl == 0) or (scl_ctl == "0") or (scl_ctl.upper() == "L"):
scl = 1
elif (scl_ctl is True) or (scl_ctl == 1) or (scl_ctl == "1") or (scl_ctl.upper() == "H"):
scl = 2
elif scl_ctl.upper() == "Z":
scl = 3
rslt |= scl << vrlg.SENSI2C_CMD_SCL
sda=0
if not sda_ctl is None:
if (sda_ctl is False) or (sda_ctl == 0) or (sda_ctl == "0") or (sda_ctl.upper() == "L"):
sda = 1
elif (sda_ctl is True) or (sda_ctl == 1) or (sda_ctl == "1") or (sda_ctl.upper() == "H"):
sda = 2
elif sda_ctl.upper() == "Z":
sda = 3
rslt |= sda << vrlg.SENSI2C_CMD_SDA
if (not active_sda is None) and (not early_release_0 is None):
rslt |= (0,1)[early_release_0] << vrlg.SENSI2C_CMD_ACIVE_EARLY0
rslt |= (0,1)[active_sda] << vrlg.SENSI2C_CMD_ACIVE_SDA
rslt |= 1 << vrlg.SENSI2C_CMD_ACIVE
if advance_FIFO:
rslt |= 1 << vrlg.SENSI2C_CMD_FIFO_RD
return rslt
def func_sensor_i2c_table_reg_wr (self,
slave_addr,
rah,
num_bytes,
bit_delay,
verbose = 1):
"""
@param slave_addr - 7-bit i2c slave address
@param rah - register address high byte (bits [15:8]) optionally used for register write commands
@param num_bytes - number of bytes to send (including register address bytes) 1..10
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param verbose - verbose level
@return combined table data word.
"""
if verbose>0:
print ("func_sensor_i2c_table_reg_wr(): slave_addr= ",slave_addr,", rah=",rah,", num_bytes = ",num_bytes,", bit_delay = ",bit_delay)
rslt = 0
rslt |= (slave_addr & ((1 << vrlg.SENSI2C_TBL_SA_BITS) - 1)) << vrlg.SENSI2C_TBL_SA
rslt |= (rah & ((1 << vrlg.SENSI2C_TBL_RAH_BITS) - 1)) << vrlg.SENSI2C_TBL_RAH
rslt |= (num_bytes & ((1 << vrlg.SENSI2C_TBL_NBWR_BITS) - 1)) << vrlg.SENSI2C_TBL_NBWR
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
return rslt
def func_sensor_i2c_table_reg_rd (self,
two_byte_addr,
num_bytes_rd,
bit_delay,
verbose = 1):
"""
@param two_byte_addr - Use a 2-byte register address for read command (False - single byte)
@param num_bytes_rd - Number of bytes to read (1..8)
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param verbose - verbose level
@return combined table data word.
"""
if verbose>0:
print ("func_sensor_i2c_table_reg_rd(): two_byte_addr= ",two_byte_addr,", num_bytes_rd=",num_bytes_rd,", bit_delay = ",bit_delay)
rslt = 0
rslt |= 1 << vrlg.SENSI2C_TBL_RNWREG # this is read register command (0 - write register)
if two_byte_addr > 1:
two_byte_addr = 1
rslt |= (0,1)[two_byte_addr] << vrlg.SENSI2C_TBL_SA
rslt |= (num_bytes_rd & ((1 << vrlg.SENSI2C_TBL_NBRD_BITS) - 1)) << vrlg.SENSI2C_TBL_NBRD
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
return rslt
def func_sensor_io_ctl (self,
......@@ -371,29 +397,83 @@ class X393Sensor(object):
num_sensor,
rst_cmd = False,
run_cmd = None,
num_bytes = None,
dly = None,
scl_ctl = None,
sda_ctl = None):
active_sda = None,
early_release_0 = None,
advance_FIFO = None,
verbose = 1):
"""
@param num_sensor - sensor port number (0..3)
@param rst_cmd - reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
@param run_cmd - True - run i2c, False - stop i2c (needed before software i2c), None - no change
@param num_bytes - set number of i2c bytes after slave address (0..3), None - no change
@param dly - set duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA??? obsolete)
@param scl_ctl - directly control SCL line: None - NOP, 'Z' - high Z, 0/False/'L' - low level,
1/True/'H' - high level
@param sda_ctl - directly control SDA line: None - NOP, 'Z' - high Z, 0/False/'L' - low level,
1/True/'H' - high level
@return: i2c control word
@param active_sda - pull-up SDA line during second half of SCL=0, when needed and possible
@param early_release_0 - release SDA=0 immediately after the end of SCL=1 (SDA hold will be provided by week pullup)
@param advance_FIFO - advance i2c read FIFO
@param verbose - verbose level
active_sda and early_release_0 should be defined both to take effect (any of the None skips setting these parameters)
"""
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR,
self.func_sensor_i2c_command(
rst_cmd = rst_cmd,
run_cmd = run_cmd,
active_sda = active_sda,
early_release_0 = early_release_0,
advance_FIFO = advance_FIFO,
verbose = verbose))
def set_sensor_i2c_table_reg_wr (self,
num_sensor,
page,
slave_addr,
rah,
num_bytes,
bit_delay,
verbose = 1):
"""
Set table entry for a single index for register write
@param num_sensor - sensor port number (0..3)
@param page - 1 byte table index (later provided as high byte of the 32-bit command)
@param slave_addr - 7-bit i2c slave address
@param rah - register address high byte (bits [15:8]) optionally used for register write commands
@param num_bytes - number of bytes to send (including register address bytes) 1..10
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param verbose - verbose level
"""
ta = (1 << vrlg.SENSI2C_CMD_TABLE) | (1 << vrlg.SENSI2C_CMD_TAND) | (page & 0xff)
td = (1 << vrlg.SENSI2C_CMD_TABLE) | self.func_sensor_i2c_table_reg_wr(
slave_addr = slave_addr,
rah = rah,
num_bytes = num_bytes,
dly = dly,
scl_ctl = scl_ctl,
sda_ctl = sda_ctl))
bit_delay = bit_delay,
verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, td)
def set_sensor_i2c_table_reg_rd (self,
num_sensor,
page,
two_byte_addr,
num_bytes_rd,
bit_delay,
verbose = 1):
"""
Set table entry for a single index for register write
@param num_sensor - sensor port number (0..3)
@param page - 1 byte table index (later provided as high byte of the 32-bit command)
@param two_byte_addr - Use a 2-byte register address for read command (False - single byte)
@param num_bytes_rd - Number of bytes to read (1..8)
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param verbose - verbose level
"""
ta = (1 << vrlg.SENSI2C_CMD_TABLE) | (1 << vrlg.SENSI2C_CMD_TAND) | (page & 0xff)
td = (1 << vrlg.SENSI2C_CMD_TABLE) | self.func_sensor_i2c_table_reg_rd(
two_byte_addr = two_byte_addr,
num_bytes_rd = num_bytes_rd,
bit_delay = bit_delay,
verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, td)
def write_sensor_i2c (self,
num_sensor,
......@@ -405,7 +485,17 @@ class X393Sensor(object):
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param rel_addr - True - relative frame address, False - absolute frame address
@param addr - frame address (0..15)
@param data - Combine slave address/register address/ register data for the i2c command
@param data - depends on context:
1 - register write: index page, 3 payload bytes. Payload bytes are used according to table and sent
after the slave address and optional high address byte other bytes are sent in descending order (LSB- last).
If less than 4 bytes are programmed in the table the high bytes (starting with the one from the table) are
skipped.
If more than 4 bytes are programmed in the table for the page (high byte), one or two next 32-bit words
bypass the index table and all 4 bytes are considered payload ones. If less than 4 extra bytes are to be
sent for such extra word, only the lower bytes are sent.
2 - register read: index page, slave address (8-bit, with lower bit 0) and one or 2 address bytes (as programmed
in the table. Slave address is always in byte 2 (bits 23:16), byte1 (high register address) is skipped if
read address in teh table is programmed to be a single-byte one
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -422,6 +512,49 @@ class X393Sensor(object):
reg_addr += (addr & ~vrlg.SENSI2C_ADDR_MASK);
self.x393_axi_tasks.write_control_register(reg_addr, data)
def read_sensor_i2c (self,
num_sensor,
num_bytes = None):
"""
Read sequence of bytes available
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param num_bytes - number of bytes to read (None - all in FIFO)
@return list of read bytes
"""
ODDEVEN="ODDEVEN"
DAV = "DAV"
DATA = "DATA"
def read_i2c_data(num_sensor):
addr = vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL
d = self.x393_axi_tasks.read_status(addr)
return {ODDEVEN : (d >> 9) & 1, DAV : (d >> 8) & 1, DATA : d & 0xff}
timeout = 1.0 # sec
end_time = time.time() + timeout
rslt = []
while True:
d = read_i2c_data(num_sensor)
if not d[DAV]:
if num_bytes is None:
break # no data available in FIFO and number of bytes is not specified
while (time.time() < end_time) and (not d[DAV]): # wait for data available
d = read_i2c_data(num_sensor)
if not d[DAV]:
break # no data available - timeout
rslt.append(d[DATA])
# advance to the next data byte
oddeven = d[ODDEVEN]
self. set_sensor_i2c_command (
num_sensor = num_sensor,
advance_FIFO = True,
verbose = 1)
# wait until odd/even bit reverses (no timeout here)
while d[ODDEVEN] == oddeven:
d = read_i2c_data(num_sensor)
if len(rslt) == num_bytes:
break # read all that was requested (num_bytes == None will not get here)
return rslt
def set_sensor_io_ctl (self,
num_sensor,
mrst = None,
......
sensor/sensor_i2c_io.v
View file @ 642b83c6
......@@ -147,8 +147,11 @@ module sensor_i2c_io#(
.I (sda_out), // input
.T (!sda_en) // input
);
// So simulation will show different when SDA is not driven
`ifndef SIMULATION
mpullup i_scl_pullup(scl);
mpullup i_sda_pullup(sda);
`endif
endmodule
sensor/sensor_i2c_prot.v
View file @ 642b83c6
......@@ -101,7 +101,7 @@ module sensor_i2c_prot#(
// wire i2c_next_byte;
reg [ 2:0] mem_re;
reg mem_valid;
reg [ 3:0] table_re;
reg [ 2:0] table_re;
// reg read_mem_msb;
// wire decode_reg_rd = &seq_rd[7:4];
......@@ -146,9 +146,10 @@ module sensor_i2c_prot#(
wire pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1];
reg rnw; // last command was read (not write) - do not increment bytes_left_send
// wire dout_stb; // rvalid
assign seq_mem_re = mem_re[1:0];
// assign rvalid = dout_stb && run_reg_rd[1];
always @ (posedge mclk) begin
if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0;
else if (start_rd_seq_w) rnw <= 1;
......@@ -171,7 +172,7 @@ module sensor_i2c_prot#(
else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open;
table_re <= {table_re[2:0], pre_table_re}; // start_wr_seq_w};
table_re <= {table_re[1:0], pre_table_re}; // start_wr_seq_w};
if (table_re[2]) begin
reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; //[ 7:0]; // MSB of the register address (instead of the byte 2)
......
sensor/sensor_i2c_scl_sda.v
View file @ 642b83c6
......@@ -32,7 +32,7 @@ module sensor_i2c_scl_sda(
input snd9,
input rcv, // receive mode (valid with snd9) - master receives, slave - sends
input [ 8:0] din,
output [ 8:0] dout, //
output reg [ 8:0] dout, //
output reg dout_stb, // dout contains valid data
output reg scl, // i2c SCL signal
input sda_in, // i2c SDA signal form I/O pad
......@@ -63,17 +63,21 @@ module sensor_i2c_scl_sda(
reg first_cyc; // first clock cycle for the delay interval - update SCL/SDA outputs
reg active_sda_r; // registered @ snd9, disable in rcv mode
reg active_sda_was_0; // only use active SDA if previous bit was 0 or it is receive mode
reg early_release_r; // to enable it only for LSB before ACKN during send
reg rcv_r;
wire busy_w = busy_r && ! done_r;
// wire pre_dout_stb = dly_over && seq_bit[0] && (bits_left == 0);
// assign ready = !busy_r;
assign ready = !busy_w;
assign is_open = is_open_r;
assign dout = sr;
// assign dout = sr;
always @ (posedge mclk) begin
active_sda_was_0 <= !sda || rcv_r;
if (snd9_w) rcv_r <= rcv;
early_release_r <= early_release_0 && !rcv_r && (bits_left == 1); // only before ACN during master send
// disable active_sda in send messages for the last (ACKN) bit, for the receive - all but ACKN
if (snd9_w) active_sda_r <= active_sda && !rcv;
else if (snd_start_w || snd_stop_w) active_sda_r <= active_sda;
......@@ -123,7 +127,10 @@ module sensor_i2c_scl_sda(
if (snd9_w) sr <= din;
else if (dly_over && seq_bit[0]) sr <= {sr[7:0], sda_r};
dout_stb <= dly_over && seq_bit[0] && (bits_left == 0);
dout_stb <= dly_over && seq_bit[0] && (bits_left == 0) && rcv_r;
// dout_stb <= pre_dout_stb;
// if (pre_dout_stb) dout <= {sr[7:0],sda_r};
if (done_r) dout <= {sr[7:0],sda_r};
if (rst) is_open_r <= 0;
else if (dly_over && seq_start_restart[0]) is_open_r <= 1;
......@@ -153,7 +160,8 @@ module sensor_i2c_scl_sda(
(|seq_start_restart[1:0]) ||
(|seq_stop[2:1]) ||
(!sr[8] && (|seq_bit[3:1])) ||
(!sr[8] && seq_bit[0] && (!early_release_0 || !sr[7])));
// (!sr[8] && seq_bit[0] && (!early_release_0 || !sr[7])));
(!sr[8] && seq_bit[0] && (!early_release_r || !sr[7])));
bus_busy <= busy_r;
end
......
x393_testbench02.sav
View file @ 642b83c6
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Fri Oct 9 05:58:40 2015
[*] Sat Oct 10 04:26:57 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151008232719927.fst"
[dumpfile_mtime] "Fri Oct 9 05:58:07 2015"
[dumpfile_size] 132054423
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151009220220129.fst"
[dumpfile_mtime] "Sat Oct 10 04:26:01 2015"
[dumpfile_size] 96721857
[savefile] "/home/andrey/git/x393/x393_testbench02.sav"
[timestart] 38030000
[timestart] 65911000
[size] 1823 1180
[pos] 1922 0
*-23.015932 86157388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-17.835970 66537388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench02.
[treeopen] x393_testbench02.compressor_control.
[treeopen] x393_testbench02.simul_axi_hp1_wr_i.
......@@ -99,7 +99,7 @@
[treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i.
[sst_width] 312
[signals_width] 303
[signals_width] 388
[sst_expanded] 1
[sst_vpaned_height] 611
@820
......@@ -3872,6 +3872,10 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.scl_out
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_rdata[7:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_rvalid
@1000200
-chn0
@800200
......@@ -3957,10 +3961,10 @@ x393_testbench02.set_sensor_i2c_command.tmp[31:0]
@800200
-sens_i2c
-i2c_prot_sel
@c00200
-chn1
@29
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_start
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_start
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_wr_seq_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_extra_seq_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_rd_seq_w
......@@ -4006,9 +4010,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.seq_rd[7:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_valid
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_byte_wr
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.bytes_left_send[3:0]
......@@ -4034,7 +4035,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.se
-scl_sda
@200
-
@1000200
@1401200
-chn1
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_re[2:0]
......@@ -4063,19 +4064,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.seq_mem_ra[1:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.pre_table_re
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.snd9
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_rdy
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_cmd
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_byte_wr
@1001200
-group_end
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
@28
......@@ -4113,6 +4101,22 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd_sa
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sr_in[8:0]
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
(7)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rvalid
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.num_bytes_send[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.bytes_left_send[3:0]
@200
......@@ -4213,9 +4217,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_extra_seq_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_rd_seq_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_wr_seq_w
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.tand
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.td[27:0]
......@@ -4253,15 +4254,18 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.active_sda_r
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.din[8:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_r
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
@c00022
@800023
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
@28
@29
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
@1401200
@1001201
-group_end
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.first_cyc
......
x393_testbench02.tf
View file @ 642b83c6
......@@ -2910,7 +2910,9 @@ task test_i2c_353;
set_sensor_i2c_command (chn, 0, 3, 0, 0, 0); // run i2c
write_sensor_i2c (chn, 1, 0,'h90050922);
for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 0, i+ 'h12);
write_sensor_i2c (chn, 1, 0,'h91901234);
write_sensor_i2c (chn, 1, 0,'h91900004);
//write_sensor_i2c 0 1 0 0x91900004
//read_sensor_i2c 0
write_sensor_i2c (
chn, // input [1:0] num_sensor;
......
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