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Commit 58ed96d6 authored by Andrey Filippov's avatar Andrey Filippov
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started modifications for tiff images and lwir sensors

parent 984b25f6
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compressor_jp/cmprs_buf_average.v
View file @ 58ed96d6
......@@ -66,7 +66,7 @@ module cmprs_buf_average#(
input [ 7:0] caddrw,
input cwe,
input [ 8:0] signed_c,
output [ 9:0] do, // [9:0] data out (4:2:0) (signed, average=0)
output [ 9:0] dout, // [9:0] data out (4:2:0) (signed, average=0)
// When is it valid?
output [ 8:0] avr, // [8:0] DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!
output dv, // out data valid (will go high for at least 64 cycles)
......@@ -170,7 +170,7 @@ module cmprs_buf_average#(
// assign output signals
assign avr = avr_r; // avermem[avr_ra[3:0]];
assign do = do_r;
assign dout = do_r;
assign tn[2:0] = raddr[8:6];
// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)
assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};
......
compressor_jp/encoderDCAC393.v
View file @ 58ed96d6
......@@ -53,7 +53,7 @@ module encoderDCAC393(
input first_blockz, // first block input (@zds)
input zds, // strobe - one ahead of the DC component output
output reg last, //
output reg [15:0] do,
output reg [15:0] dout,
output reg dv,
// just for debug
output comp_lastinmbo,
......@@ -132,7 +132,7 @@ module encoderDCAC393(
(cntr[5:0]==6'h3f),
ac_in[11:0]}};
was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;
if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
if (pre_dv) dout <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
dv <= pre_dv;
DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust
if (!DCACen) cntr[5:0] <=6'b0;
......
compressor_jp/focus_sharp393.v
View file @ 58ed96d6
......@@ -59,7 +59,7 @@ module focus_sharp393(
input quant_ds, // quantizator ds
input [12:0] quant_d, // [11:0]quantizator data output
input [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module)
output reg [12:0] do, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg [12:0] dout, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg ds, // data out strobe (one ahead of the start of dv)
output reg [31:0] hifreq); //[31:0]) // accumulated high frequency components in a frame sub-window
......@@ -248,7 +248,7 @@ module focus_sharp393(
ds <= pre_ds;
pre_do[12:0] <= next_do[12:0];
need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0);
do[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
dout[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
{2'b0,quant_dc_tdo[15:5]} :
pre_do[12:0];
end
......
compressor_jp/jp_channel.v
View file @ 58ed96d6
......@@ -944,7 +944,7 @@ module jp_channel#(
.caddrw (caddrw), // input[7:0]
.cwe (cwe), // input
.signed_c (signed_c), // input[8:0]
.do (yc_nodc), // output[9:0]
.dout (yc_nodc), // output[9:0]
.avr (yc_avr), // output[8:0]
// .dv (yc_nodc_dv), // output
.dv (), // output unused?
......@@ -1079,7 +1079,7 @@ module jp_channel#(
.first_in (first_block_dct), // input - first block in (valid @ start)
.first_out (first_block_quant), // output reg - valid @ ds
.di (dct_out[12:0]), // input[12:0] - pixel data in (signed)
.do (quant_do[12:0]), // output[12:0] - pixel data out (AC is only 9 bits long?) - changed to 10
.dout (quant_do[12:0]), // output[12:0] - pixel data out (AC is only 9 bits long?) - changed to 10
.dv (), // output reg - data out valid
.ds (quant_ds), // output reg - data out strobe (one ahead of the start of dv)
.dc_tdo (quant_dc_tdo[15:0]), // output[15:0] reg - MSB aligned coefficient for the DC component (used in focus module)
......@@ -1121,7 +1121,7 @@ module jp_channel#(
.quant_ds (quant_ds), // input quantizator ds
.quant_d (quant_do[12:0]), // input[12:0] quantizator data output
.quant_dc_tdo (quant_dc_tdo), // input[15:0] MSB aligned coefficient for the DC component (used in focus module)
.do (focus_do[12:0]), // output[12:0] reg pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
.dout (focus_do[12:0]), // output[12:0] reg pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
.ds (focus_ds), // output reg data out strobe (one ahead of the start of dv)
.hifreq (hifreq[31:0]) // output[31:0] reg accumulated high frequency components in a frame sub-window
);
......@@ -1177,7 +1177,7 @@ module jp_channel#(
`else
.last (), // output reg - not used
`endif
.do (enc_do[15:0]), // output[15:0] reg
.dout (enc_do[15:0]), // output[15:0] reg
.dv (enc_dv) // output reg
`ifdef DEBUG_RING
,.comp_lastinmbo (dbg_comp_lastinmbo)
......
compressor_jp/quantizer393.v
View file @ 58ed96d6
......@@ -58,7 +58,7 @@ module quantizer393(
input first_in, // first block in (valid @ start)
output reg first_out, // valid @ ds
input [12:0] di, // [11:0] pixel data in (signed)
output reg [12:0] do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output reg [12:0] dout, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output dv, // data out valid
output ds, // data out strobe (one ahead of the start of dv)
output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
......@@ -157,13 +157,11 @@ module quantizer393(
assign dcc_data[15:0]=sel_satnum?
{n255[7:0],n000[7:0]}:
{dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
// assign do[12:0]=zigzag_q[12:0];
assign qmul[27:0]=tdor[15:0]*d3[11:0];
assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical
// assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
always @ (posedge clk) begin
d1[12:0] <= di[12:0];
//inv_sign
......@@ -218,7 +216,7 @@ module quantizer393(
if (!en) ren[3:1] <= 0;
else ren[3:1] <= ren [2:0];
if (ren[2]) do[12:0] <= zigzag_q[12:0];
if (ren[2]) dout[12:0] <= zigzag_q[12:0];
if (start_a) first_interm <= first_in;
if (start_out) first_out <=first_interm;
......
fpga_version.vh
View file @ 58ed96d6
......@@ -36,7 +36,8 @@
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
parameter FPGA_VERSION = 32'h03930104; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
// parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met
// parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK
......
system_defines.vh
View file @ 58ed96d6
......@@ -64,7 +64,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
......
x393_sata/wrapper/GTXE2_GPL.v
View file @ 58ed96d6
......@@ -258,7 +258,24 @@ end
endmodule
`endif
module gtxe2_chnl_clocking(
module gtxe2_chnl_clocking#(
parameter [23:0] CPLL_CFG = 29'h00BC07DC,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 5,
parameter [23:0] CPLL_INIT_CFG = 24'h00001E,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [1:0] PMA_RSV3 = 1,
parameter TXOUT_DIV = 2,
//parameter TXRATE = 3'b000;
parameter RXOUT_DIV = 2,
//parameter RXRATE = 3'b000;
parameter TX_INT_DATAWIDTH = 0,
parameter TX_DATA_WIDTH = 20,
parameter RX_INT_DATAWIDTH = 0,
parameter RX_DATA_WIDTH = 20
)(
// top-level interfaces
input wire [2:0] CPLLREFCLKSEL,
input wire GTREFCLK0,
......@@ -314,6 +331,7 @@ module gtxe2_chnl_clocking(
input [19:0] TSTIN
);
// CPLL
/*
parameter [23:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
......@@ -332,18 +350,8 @@ parameter TX_INT_DATAWIDTH = 0;
parameter TX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter RX_DATA_WIDTH = 20;
/*
localparam tx_serial_divider = TXRATE == 3'b001 ? 1
: TXRATE == 3'b010 ? 2
: TXRATE == 3'b011 ? 4
: TXRATE == 3'b100 ? 8
: TXRATE == 3'b101 ? 16 : TXOUT_DIV ;
localparam rx_serial_divider = RXRATE == 3'b001 ? 1
: RXRATE == 3'b010 ? 2
: RXRATE == 3'b011 ? 4
: RXRATE == 3'b100 ? 8
: RXRATE == 3'b101 ? 16 : RXOUT_DIV ;
*/
localparam tx_pma_divider1 = TX_INT_DATAWIDTH == 1 ? 4 : 2;
localparam tx_pcs_divider1 = tx_pma_divider1;
localparam tx_pma_divider2 = TX_DATA_WIDTH == 20 | TX_DATA_WIDTH == 40 | TX_DATA_WIDTH == 80 ? 5 : 4;
......@@ -360,6 +368,11 @@ wire TXPLLREFCLK_DIV2;
wire RXPLLREFCLK_DIV1;
wire RXPLLREFCLK_DIV2;
assign GTREFCLKMONITOR = 'bx; // Was not assigned
assign TXOUTCLKFABRIC = 'bx; // Was not assigned
assign RXOUTCLKFABRIC = 'bx; // Was not assigned
assign tx_phy_clk = TXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
assign TXPLLREFCLK_DIV1 = TXSYSCLKSEL[1] ? QPLLREFCLK : clk_mux_out;
assign rx_phy_clk = RXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
......@@ -2358,6 +2371,8 @@ rx(
.serial_clk (rx_serial_clk)
);
wire tx_piso_clk;
wire rx_sipo_clk;
gtxe2_chnl_clocking #(
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
......@@ -2374,8 +2389,7 @@ gtxe2_chnl_clocking #(
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH)
)
clocking(
) clocking_i ( // was "clocking" w/o "_i" - is it a keyword?
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
......@@ -2410,7 +2424,7 @@ clocking(
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (tx_serial_clk),
.tx_piso_clk (),
.tx_piso_clk (tx_piso_clk),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
......@@ -2425,9 +2439,10 @@ clocking(
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk (rx_serial_clk),
.rx_sipo_clk ()
.rx_sipo_clk (rx_sipo_clk)
);
endmodule
module GTXE2_GPL(
......
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