Commit 58ed96d6 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

started modifications for tiff images and lwir sensors

parent 984b25f6

compressor_jp/cmprs_buf_average.v

+2 −2
Original line number Original line Diff line number Diff line
@@ -66,7 +66,7 @@ module cmprs_buf_average#( 
    input  [ 7:0] caddrw,

    input  [ 7:0] caddrw,

    input         cwe,

    input         cwe,

    input  [ 8:0] signed_c,

    input  [ 8:0] signed_c,

    output [ 9:0] do,         // [9:0] data out (4:2:0) (signed, average=0)

    output [ 9:0] dout,         // [9:0] data out (4:2:0) (signed, average=0)

    // When is it valid?

    // When is it valid?

    output [ 8:0] avr,        // [8:0]    DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!

    output [ 8:0] avr,        // [8:0]    DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!

    output        dv,         // out data valid (will go high for at least 64 cycles)

    output        dv,         // out data valid (will go high for at least 64 cycles)
@@ -170,7 +170,7 @@ module cmprs_buf_average#( 
    

    

    // assign output signals

    // assign output signals

    assign avr  = avr_r; // avermem[avr_ra[3:0]];

    assign avr  = avr_r; // avermem[avr_ra[3:0]];

    assign do =                do_r;

    assign dout =                do_r;

    assign tn[2:0] =           raddr[8:6];

    assign tn[2:0] =           raddr[8:6];

// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)

// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)

    assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};

    assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};

compressor_jp/encoderDCAC393.v

+2 −2
Original line number Original line Diff line number Diff line
@@ -53,7 +53,7 @@ module encoderDCAC393( 
    input             first_blockz,   // first block input (@zds)

    input             first_blockz,   // first block input (@zds)

    input             zds,            // strobe - one ahead of the DC component output

    input             zds,            // strobe - one ahead of the DC component output

    output reg        last,           //

    output reg        last,           //

    output reg [15:0] do,

    output reg [15:0] dout,

    output reg        dv,

    output reg        dv,

    // just for debug

    // just for debug

    output comp_lastinmbo,

    output comp_lastinmbo,
@@ -132,7 +132,7 @@ module encoderDCAC393( 
                              (cntr[5:0]==6'h3f),

                              (cntr[5:0]==6'h3f),

                              ac_in[11:0]}}; 

                              ac_in[11:0]}}; 

        was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;

        was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;

        if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};

        if (pre_dv) dout <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};

        dv    <= pre_dv;

        dv    <= pre_dv;

        DCACen    <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f)));    // adjust

        DCACen    <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f)));    // adjust

        if (!DCACen) cntr[5:0] <=6'b0;

        if (!DCACen) cntr[5:0] <=6'b0;

compressor_jp/focus_sharp393.v

+2 −2
Original line number Original line Diff line number Diff line
@@ -59,7 +59,7 @@ module focus_sharp393( 
    input             quant_ds,     // quantizator ds

    input             quant_ds,     // quantizator ds

    input      [12:0] quant_d,      // [11:0]quantizator data output

    input      [12:0] quant_d,      // [11:0]quantizator data output

    input      [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module)

    input      [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module)

    output reg [12:0] do,           // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)

    output reg [12:0] dout,           // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)

    output reg        ds,           // data out strobe (one ahead of the start of dv)

    output reg        ds,           // data out strobe (one ahead of the start of dv)

    output reg [31:0] hifreq);      //[31:0])  //  accumulated high frequency components in a frame sub-window

    output reg [31:0] hifreq);      //[31:0])  //  accumulated high frequency components in a frame sub-window
@@ -248,7 +248,7 @@ module focus_sharp393( 
        ds <= pre_ds;

        ds <= pre_ds;

        pre_do[12:0] <= next_do[12:0];

        pre_do[12:0] <= next_do[12:0];

        need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0);

        need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0);

        do[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?

        dout[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?

                    {2'b0,quant_dc_tdo[15:5]} :

                    {2'b0,quant_dc_tdo[15:5]} :

                    pre_do[12:0];

                    pre_do[12:0];

     end

     end

compressor_jp/jp_channel.v

+4 −4
Original line number Original line Diff line number Diff line
@@ -944,7 +944,7 @@ module jp_channel#( 
        .caddrw             (caddrw),           // input[7:0] 

        .caddrw             (caddrw),           // input[7:0] 

        .cwe                (cwe),              // input

        .cwe                (cwe),              // input

        .signed_c           (signed_c),         // input[8:0] 

        .signed_c           (signed_c),         // input[8:0] 

        .do                 (yc_nodc),          // output[9:0] 

        .dout               (yc_nodc),          // output[9:0] 

        .avr                (yc_avr),           // output[8:0] 

        .avr                (yc_avr),           // output[8:0] 

//        .dv                 (yc_nodc_dv),       // output

//        .dv                 (yc_nodc_dv),       // output

        .dv                 (),                 // output unused?

        .dv                 (),                 // output unused?
@@ -1079,7 +1079,7 @@ module jp_channel#( 
        .first_in           (first_block_dct),        // input - first block in (valid @ start)

        .first_in           (first_block_dct),        // input - first block in (valid @ start)

        .first_out          (first_block_quant),      // output reg - valid @ ds

        .first_out          (first_block_quant),      // output reg - valid @ ds

        .di                 (dct_out[12:0]),          // input[12:0] -  pixel data in (signed)

        .di                 (dct_out[12:0]),          // input[12:0] -  pixel data in (signed)

        .do                 (quant_do[12:0]),         // output[12:0] - pixel data out (AC is only 9 bits long?) - changed to 10

        .dout               (quant_do[12:0]),         // output[12:0] - pixel data out (AC is only 9 bits long?) - changed to 10

        .dv                 (),                       // output reg - data out valid

        .dv                 (),                       // output reg - data out valid

        .ds                 (quant_ds),               // output reg - data out strobe (one ahead of the start of dv)

        .ds                 (quant_ds),               // output reg - data out strobe (one ahead of the start of dv)

        .dc_tdo             (quant_dc_tdo[15:0]),     // output[15:0] reg -  MSB aligned coefficient for the DC component (used in focus module)

        .dc_tdo             (quant_dc_tdo[15:0]),     // output[15:0] reg -  MSB aligned coefficient for the DC component (used in focus module)
@@ -1121,7 +1121,7 @@ module jp_channel#( 
        .quant_ds           (quant_ds),               // input quantizator ds

        .quant_ds           (quant_ds),               // input quantizator ds

        .quant_d            (quant_do[12:0]),         // input[12:0] quantizator data output

        .quant_d            (quant_do[12:0]),         // input[12:0] quantizator data output

        .quant_dc_tdo       (quant_dc_tdo),           // input[15:0] MSB aligned coefficient for the DC component (used in focus module)

        .quant_dc_tdo       (quant_dc_tdo),           // input[15:0] MSB aligned coefficient for the DC component (used in focus module)

        .do                 (focus_do[12:0]),         // output[12:0] reg  pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)

        .dout               (focus_do[12:0]),         // output[12:0] reg  pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)

        .ds                 (focus_ds),               // output reg data out strobe (one ahead of the start of dv)

        .ds                 (focus_ds),               // output reg data out strobe (one ahead of the start of dv)

        .hifreq             (hifreq[31:0])            // output[31:0] reg accumulated high frequency components in a frame sub-window

        .hifreq             (hifreq[31:0])            // output[31:0] reg accumulated high frequency components in a frame sub-window

    );

    );
@@ -1177,7 +1177,7 @@ module jp_channel#( 
`else

`else

        .last               (),                       // output reg - not used

        .last               (),                       // output reg - not used

`endif

`endif

        .do                 (enc_do[15:0]),           // output[15:0] reg 

        .dout               (enc_do[15:0]),           // output[15:0] reg 

        .dv                 (enc_dv)                  // output reg 

        .dv                 (enc_dv)                  // output reg 

`ifdef DEBUG_RING

`ifdef DEBUG_RING

        ,.comp_lastinmbo               (dbg_comp_lastinmbo)

        ,.comp_lastinmbo               (dbg_comp_lastinmbo)

compressor_jp/quantizer393.v

+2 −4
Original line number Original line Diff line number Diff line
@@ -58,7 +58,7 @@ module quantizer393( 
    input             first_in, // first block in (valid @ start)

    input             first_in, // first block in (valid @ start)

    output reg        first_out, // valid @ ds

    output reg        first_out, // valid @ ds

    input      [12:0] di,    // [11:0] pixel data in (signed)

    input      [12:0] di,    // [11:0] pixel data in (signed)

    output reg [12:0] do,    // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10

    output reg [12:0] dout,    // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10

    output            dv,    // data out valid

    output            dv,    // data out valid

    output            ds,  // data out strobe (one ahead of the start of dv)

    output            ds,  // data out strobe (one ahead of the start of dv)

    output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)

    output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
@@ -157,13 +157,11 @@ module quantizer393( 
    assign        dcc_data[15:0]=sel_satnum?

    assign        dcc_data[15:0]=sel_satnum?

                    {n255[7:0],n000[7:0]}:

                    {n255[7:0],n000[7:0]}:

                    {dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};

                    {dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};

//    assign         do[12:0]=zigzag_q[12:0];

    assign        qmul[27:0]=tdor[15:0]*d3[11:0];

    assign        qmul[27:0]=tdor[15:0]*d3[11:0];





    assign         start_out =   zwe && (zwa[5:0]== 6'h3f);   //adjust?

    assign         start_out =   zwe && (zwa[5:0]== 6'h3f);   //adjust?

    assign         copy_dc_tdo = zwe && (zwa[5:0]== 6'h37);   // not critical

    assign         copy_dc_tdo = zwe && (zwa[5:0]== 6'h37);   // not critical





//    assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));    

    always @ (posedge clk) begin

    always @ (posedge clk) begin

        d1[12:0]      <= di[12:0];

        d1[12:0]      <= di[12:0];

//inv_sign

//inv_sign
@@ -218,7 +216,7 @@ module quantizer393( 
        if      (!en)                 ren[3:1] <= 0;

        if      (!en)                 ren[3:1] <= 0;

        else                          ren[3:1] <= ren [2:0]; 

        else                          ren[3:1] <= ren [2:0]; 

        

        

        if (ren[2])                   do[12:0] <= zigzag_q[12:0];

        if (ren[2])                   dout[12:0] <= zigzag_q[12:0];

        

        

        if (start_a)   first_interm <= first_in;

        if (start_a)   first_interm <= first_in;

        if (start_out) first_out    <=first_interm;

        if (start_out) first_out    <=first_interm;