Working on simulation testbench

.editor_defines → .editor_defines.vh

   // This file may be used to define same pre-processor macros to be included into each parsed file
   // It can be used to check different `ifdef branches
   //`define XIL_TIMING //Simprim 
-  `define IVERILOG
+  `define den4096Mb 1
+//  `define IVERILOG
   // defines for memory channels
   // chn 0 is read from memory
  `define def_enable_mem_chn0

.settings/com.elphel.vdt.iverilog.prefs

@@ -4,6 +4,6 @@ iverilog_77_Param_Exe=/usr/local/bin/iverilog
 iverilog_78_VVP_Exe=/usr/local/bin/vvp
 iverilog_81_TopModulesOther=glbl<-@\#\#@->
 iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
-iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->
+iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->/home/andrey/git/x393/includes<-@\#\#@->
 iverilog_88_ShowNoProblem=true
 iverilog_99_GrepFindErrWarn=error|warning|sorry

ddr3/ddr3.v

@@ -108,20 +108,33 @@ module ddr3 (
     tdqs_n,
     odt
 );
-
-
-`ifdef den1024Mb
+// Icarus searces from "current directory"
+`ifdef IVERILOG
+  `ifdef den1024Mb
     `include "ddr3/1024Mb_ddr3_parameters.vh"
-`elsif den2048Mb
+  `elsif den2048Mb
     `include "ddr3/2048Mb_ddr3_parameters.vh"
-`elsif den4096Mb
+  `elsif den4096Mb
     `include "ddr3/4096Mb_ddr3_parameters.vh"
+  `else
+    // NOTE: Intentionally cause a compile fail here to force the users
+    //       to select the correct component density before continuing
+    ERROR: You must specify component density with +define+den____Mb.
+  `endif
 `else
+// Others search from the source file
+  `ifdef den1024Mb
+    `include "1024Mb_ddr3_parameters.vh"
+  `elsif den2048Mb
+    `include "2048Mb_ddr3_parameters.vh"
+  `elsif den4096Mb
+    `include "4096Mb_ddr3_parameters.vh"
+  `else
     // NOTE: Intentionally cause a compile fail here to force the users
     //       to select the correct component density before continuing
     ERROR: You must specify component density with +define+den____Mb.
+  `endif
 `endif
-
     parameter check_strict_mrbits = 1;
     parameter check_strict_timing = 1;
     parameter feature_pasr = 1;

includes/x393_localparams.vh

+// SuppressWarnings VEditor
+    localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000  << 2
+// SuppressWarnings VEditor
+    localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
+    localparam BASEADDR_CMD0 =     CMD0_ADDR << 2;     // 'h0800 << 2 = 'h2000
+//    localparam BASEADDR_CTRL =     CONTROL_ADDR << 2;
+    localparam BASEADDR_CTRL =     (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
+    localparam BASEADDR_STATUS =   STATUS_ADDR << 2;   // 'h0800 << 2 = 'h2000
+    localparam BASEADDR_DLY_LD =  BASEADDR_CTRL | (DLY_LD_REL <<2);  // 'h080, address to generate delay load
+    localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2);  // 'h070, address to generate delay set
+    localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2);  // 'h000, address to set sequnecer channel and  run (4 LSB-s - channel)
+
+    localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
+    localparam BASEADDR_PATTERNS_TRI =BASEADDR_CTRL | (PATTERNS_TRI_REL<<2); // 'h021, address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
+    localparam BASEADDR_WBUF_DELAY =BASEADDR_CTRL | (WBUF_DELAY_REL<<2); // 'h022, extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
+// SuppressWarnings VEditor
+    localparam BASEADDR_PAGES =   BASEADDR_CTRL | (PAGES_REL<<2);    // 'h023, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
+    localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2);  // 'h024, address to enable('h825)/disable('h824) command/address outputs  
+    localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // 'h026 address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory     
+    localparam BASEADDR_CKE_EN =  BASEADDR_CTRL | (CKE_EN_REL<<2);   // 'h028
+    
+// SuppressWarnings VEditor
+    localparam BASEADDR_DCI_RST =  BASEADDR_CTRL | (DCI_RST_REL<<2);   // 'h02a (+1 - enable)
+// SuppressWarnings VEditor
+    localparam BASEADDR_DLY_RST =  BASEADDR_CTRL | (DLY_RST_REL<<2);   // 'h02c (+1 - enable)
+      
+// SuppressWarnings VEditor
+    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h02e, address to set extra parameters (currently just inv_clk_div)
+    
+    localparam BASEADDR_REFRESH_EN =   BASEADDR_CTRL | (REFRESH_EN_REL<<2);    // address to enable('h31) and disable ('h30) DDR refresh
+    localparam BASEADDR_REFRESH_PER =   BASEADDR_CTRL | (REFRESH_PER_REL<<2);    // address ('h32) to set refresh period in 32 x tCK
+    localparam BASEADDR_REFRESH_ADDR =   BASEADDR_CTRL | (REFRESH_ADDR_REL<<2);    // address ('h33)to set sequencer start address for DDR refresh
+    
+    
+    localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;  
+    localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);  
+    localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);  
+    localparam BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+('h30<<2);  
+
+    localparam BASEADDRESS_CMDA  = BASEADDR_DLY_LD+('h40<<2);
+    localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
+    localparam STATUS_PSHIFTER_RDY_MASK = 'h100;
+// SuppressWarnings VEditor - not yet used
+    localparam STATUS_LOCKED_MASK = 'h200;
+    localparam STATUS_SEQ_BUSY_MASK = 'h400;
+
+`ifdef use200Mhz
+    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
+    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
+    localparam DLY_LANE0_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE0_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
+    localparam DLY_LANE1_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
+    localparam DLY_CMDA=  256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
+// alternative to set same type delays to the same value    
+    localparam DLY_DQ_IDELAY =  'h20 ;// 'h60;
+    localparam DLY_DQ_ODELAY =  'ha0; // 'h48;
+    localparam DLY_DQS_IDELAY = 'h40; // 'ha0;
+    localparam DLY_DQS_ODELAY = 'h4c; // 
+    localparam DLY_DM_ODELAY =  'ha0; // 'h48;
+    localparam DLY_CMDA_ODELAY ='h50; // 'h30;
+    
+`else   
+    localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs
+    localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs
+    localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
+    localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
+    localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
+    localparam DLY_CMDA=  256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
+// alternative to set same type delays to the same value    
+    localparam DLY_DQ_IDELAY =  'h70;
+    localparam DLY_DQ_ODELAY =  'h68;
+    localparam DLY_DQS_IDELAY = 'hd8;
+    localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV
+    localparam DLY_DM_ODELAY =  'h74;
+    localparam DLY_CMDA_ODELAY ='h50;
+
+
+`endif   
+    
+    localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
+    
+    localparam DQSTRI_FIRST=    4'h3; // DQS tri-state control word, first when enabling output 
+    localparam DQSTRI_LAST=     4'hc; // DQS tri-state control word, first after disabling output
+    localparam DQTRI_FIRST=     4'h7; // DQ tri-state control word, first when enabling output 
+    localparam DQTRI_LAST=      4'he; // DQ tri-state control word, first after disabling output
+    localparam WBUF_DLY_DFLT=   4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
+    localparam WBUF_DLY_WLV=    4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
+    
+//    localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
+    localparam INITIALIZE_OFFSET=  'h00; // moemory initialization start address (in words) ..`h0c
+    localparam REFRESH_OFFSET=     'h10; // refresh start address (in words) ..`h13
+    localparam WRITELEV_OFFSET=    'h20; // write leveling start address (in words) ..`h2a
+    
+    localparam READ_PATTERN_OFFSET='h40; // read pattern to memory block sequence start address (in words) ..'h053 with 8x2*64 bits (variable)
+    localparam WRITE_BLOCK_OFFSET= 'h100; // write block sequence start address (in words) ..'h14c
+    localparam READ_BLOCK_OFFSET=  'h180; // read  block sequence start address (in words)

includes/x393_simulation_parameters.vh

+    // simulation-specific parameters
+    , // to continue previous list
+    parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
+    parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
+    parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
+    parameter integer AXI_TASK_HOLD=1.0,
+    parameter integer ADDRESS_NUMBER=15 
+ 

includes/x393_tasks01.vh

+ // Low-level tasks 
+
+    task axi_set_rd_lag;
+        input [3:0] lag;
+        begin
+            @(posedge CLK);
+            RD_LAG <= lag;
+        end
+    endtask
+
+    task axi_set_b_lag;
+        input [3:0] lag;
+        begin
+            @(posedge CLK);
+            B_LAG <= lag;
+        end
+    endtask
+   
+    reg [11:0] GLOBAL_WRITE_ID=0;
+    reg [11:0] GLOBAL_READ_ID=0;
+
+    task read_and_wait;
+    input [31:0] address;
+    begin
+        axi_read_addr(
+            GLOBAL_READ_ID,    // id
+            address & 32'hfffffffc, // addr
+            4'h0, // len - single
+            1     // burst type - increment
+            );
+        GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
+        wait (!CLK && rvalid && rready);
+        wait (CLK);
+        registered_rdata <= rdata;
+    end
+    endtask
+    
+    task axi_write_single; // address in bytes, not words
+        input [31:0] address;
+        input [31:0] data;
+        begin
+`ifdef DEBUG_WR_SINGLE
+          $display("axi_write_single %h:%h @ %t",address,data,$time);
+`endif                
+          axi_write_addr_data(
+                    GLOBAL_WRITE_ID,    // id
+//                    address << 2, // addr
+                    address & 32'hfffffffc, // addr
+                    data,
+                    4'h0, // len - single
+                    1,    // burst type - increment
+                    1'b1, // data_en
+                    4'hf, // wstrb
+                    1'b1 // last
+                );
+          GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
+          #0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
+        end
+    endtask
+   
+    task axi_write_addr_data;
+        input [11:0] id;
+        input [31:0] addr;
+        input [31:0] data;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        input        data_en; // if 0 - do not send data, only address
+        input [ 3:0] wstrb;
+        input        last;
+        reg          data_sent;
+//        wire         data_sent_d;
+//        assign #(.1) data_sent_d= data_sent;
+        begin
+            wait (!CLK && AW_READY);
+            AWID_IN_r    <= id;
+            AWADDR_IN_r  <= addr;
+            AWLEN_IN_r   <= len;
+            AWSIZE_IN_r  <= 3'b010;
+            AWBURST_IN_r <= burst;
+            AW_SET_CMD_r <= 1'b1;
+            if (data_en && W_READY) begin
+                WID_IN_r <= id;
+                WDATA_IN_r <= data;
+                WSTRB_IN_r <= wstrb;
+                WLAST_IN_r <= last;
+                W_SET_CMD_r <= 1'b1; 
+                data_sent <= 1'b1;
+            end else begin
+                data_sent <= 1'b0;
+            end
+            DEBUG1 <=1'b1;
+            wait (CLK);
+            DEBUG1 <=1'b0;
+            AWID_IN_r    <= 'hz;
+            AWADDR_IN_r  <= 'hz;
+            AWLEN_IN_r   <= 'hz;
+            AWSIZE_IN_r  <= 'hz;
+            AWBURST_IN_r <= 'hz;
+            AW_SET_CMD_r <= 1'b0;
+            DEBUG2 <=1'b1;
+            if (data_sent) begin
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+// Now sent data if it was not sent simultaneously with the address
+            if (data_en && !data_sent) begin
+                DEBUG3 <=1'b1;
+                wait (!CLK && W_READY);
+                DEBUG3 <=1'b0;
+                WID_IN_r    <= id;
+                WDATA_IN_r  <= data;
+                WSTRB_IN_r  <= wstrb;
+                WLAST_IN_r  <= last;
+                W_SET_CMD_r <= 1'b1; 
+                wait (CLK);
+                DEBUG3 <=1'bx;
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+            DEBUG2 <=1'b0;
+            #0.1;
+            data_sent <= 1'b0;
+            #0.1;
+        end
+    endtask
+
+    task axi_write_data;
+        input [11:0] id;
+        input [31:0] data;
+        input [ 3:0] wstrb;
+        input        last;
+        begin
+            wait (!CLK && W_READY);
+            WID_IN_r    <= id;
+            WDATA_IN_r  <= data;
+            WSTRB_IN_r  <= wstrb;
+            WLAST_IN_r  <= last;
+            W_SET_CMD_r <= 1'b1; 
+            wait (CLK);
+            WID_IN_r    <= 12'hz;
+            WDATA_IN_r  <= 'hz;
+            WSTRB_IN_r  <= 4'hz;
+            WLAST_IN_r  <= 1'bz;
+            W_SET_CMD_r <= 1'b0;
+            #0.1;
+        end
+    endtask
+
+    task axi_read_addr;
+        input [11:0] id;
+        input [31:0] addr;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        begin
+            wait (!CLK && AR_READY);
+            ARID_IN_r    <= id;
+            ARADDR_IN_r  <= addr;
+            ARLEN_IN_r   <= len;
+            ARSIZE_IN_r  <= 3'b010;
+            ARBURST_IN_r <= burst;
+            AR_SET_CMD_r <= 1'b1;
+            wait (CLK);
+            ARID_IN_r    <= 12'hz;
+            ARADDR_IN_r  <= 'hz;
+            ARLEN_IN_r   <= 4'hz;
+            ARSIZE_IN_r  <= 3'hz;
+            ARBURST_IN_r <= 2'hz;
+            AR_SET_CMD_r <= 1'b0;
+            LAST_ARID <= id;
+        end
+    endtask
+

x393.v

@@ -21,7 +21,7 @@
 `timescale 1ns/1ps
 `define use200Mhz 1
 `define DEBUG_FIFO 1
-`include ".editor_defines" 
+`include ".editor_defines.vh" 
 module  x393 #(
     parameter MCONTR_WR_MASK =       'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
     parameter MCONTR_RD_MASK =       'h1c00, // AXI read address mask to generate busy
@@ -110,6 +110,8 @@ module  x393 #(
     parameter DFLT_CHN_EN=            16'h0,  // channel mask to be enabled at reset
     parameter DFLT_REFRESH_ADDR=      10'h0,  // refresh sequence address in command memory
     parameter DFLT_REFRESH_PERIOD=     8'h0,  // default 8-bit refresh period (scale?)
+    parameter ADDRESS_NUMBER=       15,
+    parameter COLADDR_NUMBER=       10,
     parameter PHASE_WIDTH =     8,
     parameter SLEW_DQ =         "SLOW",
     parameter SLEW_DQS =        "SLOW",
@@ -262,8 +264,8 @@ module  x393 #(
 //    ,input                        MEMCLK
 );
 
-    localparam ADDRESS_NUMBER=15;
-    localparam COLADDR_NUMBER=10;
+//    localparam ADDRESS_NUMBER=15;
+//    localparam COLADDR_NUMBER=10;
 // Source for reset and clock
    wire    [3:0]     fclk;      // PL Clocks [3:0], output
    wire    [3:0]     frst;      // PL Clocks [3:0], output
@@ -729,7 +731,8 @@ end
         .MCNTRL_TILED_TILE_WH              (MCNTRL_TILED_TILE_WH),
         .MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
         .MCNTRL_TILED_PENDING_CNTR_BITS    (MCNTRL_TILED_PENDING_CNTR_BITS),
-        .MCNTRL_TILED_FRAME_PAGE_RESET     (MCNTRL_TILED_FRAME_PAGE_RESET)
+        .MCNTRL_TILED_FRAME_PAGE_RESET     (MCNTRL_TILED_FRAME_PAGE_RESET),
+        .BUFFER_DEPTH32                    (BUFFER_DEPTH32)
     ) mcntrl393_i (
         .rst_in               (axi_rst), // input
         .clk_in               (axi_aclk), // input