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Commit 575da59a authored by Andrey Filippov's avatar Andrey Filippov
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Working on simulation testbench

parent 2d03240b
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.editor_defines → .editor_defines.vh
View file @ 575da59a
// This file may be used to define same pre-processor macros to be included into each parsed file
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define IVERILOG
`define den4096Mb 1
// `define IVERILOG
// defines for memory channels
// chn 0 is read from memory
`define def_enable_mem_chn0
......
.settings/com.elphel.vdt.iverilog.prefs
View file @ 575da59a
......@@ -4,6 +4,6 @@ iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->
iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->/home/andrey/git/x393/includes<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry
ddr3/ddr3.v
View file @ 575da59a
......@@ -108,20 +108,33 @@ module ddr3 (
tdqs_n,
odt
);
`ifdef den1024Mb
// Icarus searces from "current directory"
`ifdef IVERILOG
`ifdef den1024Mb
`include "ddr3/1024Mb_ddr3_parameters.vh"
`elsif den2048Mb
`elsif den2048Mb
`include "ddr3/2048Mb_ddr3_parameters.vh"
`elsif den4096Mb
`elsif den4096Mb
`include "ddr3/4096Mb_ddr3_parameters.vh"
`else
// NOTE: Intentionally cause a compile fail here to force the users
// to select the correct component density before continuing
ERROR: You must specify component density with +define+den____Mb.
`endif
`else
// Others search from the source file
`ifdef den1024Mb
`include "1024Mb_ddr3_parameters.vh"
`elsif den2048Mb
`include "2048Mb_ddr3_parameters.vh"
`elsif den4096Mb
`include "4096Mb_ddr3_parameters.vh"
`else
// NOTE: Intentionally cause a compile fail here to force the users
// to select the correct component density before continuing
ERROR: You must specify component density with +define+den____Mb.
`endif
`endif
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
......
includes/x393_localparams.vh 0 → 100644
View file @ 575da59a
// SuppressWarnings VEditor
localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000 << 2
// SuppressWarnings VEditor
localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
localparam BASEADDR_CMD0 = CMD0_ADDR << 2; // 'h0800 << 2 = 'h2000
// localparam BASEADDR_CTRL = CONTROL_ADDR << 2;
localparam BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
localparam BASEADDR_STATUS = STATUS_ADDR << 2; // 'h0800 << 2 = 'h2000
localparam BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2); // 'h080, address to generate delay load
localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2); // 'h070, address to generate delay set
localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2); // 'h000, address to set sequnecer channel and run (4 LSB-s - channel)
localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
localparam BASEADDR_PATTERNS_TRI =BASEADDR_CTRL | (PATTERNS_TRI_REL<<2); // 'h021, address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
localparam BASEADDR_WBUF_DELAY =BASEADDR_CTRL | (WBUF_DELAY_REL<<2); // 'h022, extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// SuppressWarnings VEditor
localparam BASEADDR_PAGES = BASEADDR_CTRL | (PAGES_REL<<2); // 'h023, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2); // 'h024, address to enable('h825)/disable('h824) command/address outputs
localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // 'h026 address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory
localparam BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2); // 'h028
// SuppressWarnings VEditor
localparam BASEADDR_DCI_RST = BASEADDR_CTRL | (DCI_RST_REL<<2); // 'h02a (+1 - enable)
// SuppressWarnings VEditor
localparam BASEADDR_DLY_RST = BASEADDR_CTRL | (DLY_RST_REL<<2); // 'h02c (+1 - enable)
// SuppressWarnings VEditor
localparam BASEADDR_EXTRA = BASEADDR_CTRL | (EXTRA_REL<<2); // 'h02e, address to set extra parameters (currently just inv_clk_div)
localparam BASEADDR_REFRESH_EN = BASEADDR_CTRL | (REFRESH_EN_REL<<2); // address to enable('h31) and disable ('h30) DDR refresh
localparam BASEADDR_REFRESH_PER = BASEADDR_CTRL | (REFRESH_PER_REL<<2); // address ('h32) to set refresh period in 32 x tCK
localparam BASEADDR_REFRESH_ADDR = BASEADDR_CTRL | (REFRESH_ADDR_REL<<2); // address ('h33)to set sequencer start address for DDR refresh
localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;
localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);
localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);
localparam BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+('h30<<2);
localparam BASEADDRESS_CMDA = BASEADDR_DLY_LD+('h40<<2);
localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
localparam STATUS_PSHIFTER_RDY_MASK = 'h100;
// SuppressWarnings VEditor - not yet used
localparam STATUS_LOCKED_MASK = 'h200;
localparam STATUS_SEQ_BUSY_MASK = 'h400;
`ifdef use200Mhz
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE0_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE0_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
localparam DLY_LANE1_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = 'h20 ;// 'h60;
localparam DLY_DQ_ODELAY = 'ha0; // 'h48;
localparam DLY_DQS_IDELAY = 'h40; // 'ha0;
localparam DLY_DQS_ODELAY = 'h4c; //
localparam DLY_DM_ODELAY = 'ha0; // 'h48;
localparam DLY_CMDA_ODELAY ='h50; // 'h30;
`else
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = 'h70;
localparam DLY_DQ_ODELAY = 'h68;
localparam DLY_DQS_IDELAY = 'hd8;
localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV
localparam DLY_DM_ODELAY = 'h74;
localparam DLY_CMDA_ODELAY ='h50;
`endif
localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
localparam DQSTRI_FIRST= 4'h3; // DQS tri-state control word, first when enabling output
localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
localparam DQTRI_FIRST= 4'h7; // DQ tri-state control word, first when enabling output
localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
localparam WBUF_DLY_DFLT= 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_WLV= 4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
localparam INITIALIZE_OFFSET= 'h00; // moemory initialization start address (in words) ..`h0c
localparam REFRESH_OFFSET= 'h10; // refresh start address (in words) ..`h13
localparam WRITELEV_OFFSET= 'h20; // write leveling start address (in words) ..`h2a
localparam READ_PATTERN_OFFSET='h40; // read pattern to memory block sequence start address (in words) ..'h053 with 8x2*64 bits (variable)
localparam WRITE_BLOCK_OFFSET= 'h100; // write block sequence start address (in words) ..'h14c
localparam READ_BLOCK_OFFSET= 'h180; // read block sequence start address (in words)
includes/x393_parameters.vh 0 → 100644
View file @ 575da59a
parameter MCONTR_WR_MASK = 'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h1c00, // AXI read address mask to generate busy
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
// 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
// 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
// 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // enable/disable active-low reset signal to DDR3 memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
//0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
// 0x1050 - PATTERNS // 16 bits
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// 0x1053 - EXTRA_REL // 1 bit - set extra parameters (currently just inv_clk_div)
// 0x1054 - STATUS_CNTRL // 8 bits - write to status control
parameter MCONTR_PHY_16BIT_PATTERNS = 'h0, // set DQM and DQS patterns (16'h0055)
parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter MCONTR_PHY_16BIT_WBUF_DELAY = 'h2, // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
parameter MCONTR_PHY_16BIT_EXTRA = 'h3, // ? bits - set extra parameters (currently just inv_clk_div)
parameter MCONTR_PHY_STATUS_CNTRL = 'h4, // write to status control (8-bit)
//0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h3f0, // Address mask to set channel priorities
//0x1070..1077 - 16-bit top memory controller:
parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h3f8, // address mask to set mcontr top control registers
// 0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
// 0x1071 - REFRESH_PERIOD // 8-bit refresh period
// 0x1072 - REFRESH_ADDRESS // 10 bits
// 0x1073 - STATUS_CNTRL // 8 bits - write to status control (and debug?)
parameter MCONTR_TOP_16BIT_CHN_EN = 'h0, // 16 bits per-channel enable (want/need requests)
parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1, // 8-bit refresh period
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
// Status read address
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 0, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
parameter DFLT_REFRESH_ADDR= 10'h0, // refresh sequence address in command memory
parameter DFLT_REFRESH_PERIOD= 8'h0, // default 8-bit refresh period (scale?)
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
parameter STATUS_ADDR_MASK = 'h1400, // AXI write address of status registers
parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
parameter AXI_WR_ADDR_BITS = 13,
parameter AXI_RD_ADDR_BITS = 13,
parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h1400, // AXI write address of control registers
parameter NUM_CYCLES_LOW_BIT= 'h6, // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
// TODO: put actual data
parameter NUM_CYCLES_00 = 2, // 2-cycle 000.003f
parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff
parameter NUM_CYCLES_04 = 6, // 6-cycle 100.013f
parameter NUM_CYCLES_05 = 6, // 6-cycle 140.017f
parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
parameter NUM_CYCLES_08 = 6, //
parameter NUM_CYCLES_09 = 6, //
parameter NUM_CYCLES_10 = 6, //
parameter NUM_CYCLES_11 = 6, //
parameter NUM_CYCLES_12 = 6, //
parameter NUM_CYCLES_13 = 5, // 5-cycle - not yet used
parameter NUM_CYCLES_14 = 6, // 6-cycle - not yet used
parameter NUM_CYCLES_15 = 9, // single-cycle
// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
includes/x393_simulation_parameters.vh 0 → 100644
View file @ 575da59a
// simulation-specific parameters
, // to continue previous list
parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
parameter integer AXI_TASK_HOLD=1.0,
parameter integer ADDRESS_NUMBER=15
includes/x393_tasks01.vh 0 → 100644
View file @ 575da59a
// Low-level tasks
task axi_set_rd_lag;
input [3:0] lag;
begin
@(posedge CLK);
RD_LAG <= lag;
end
endtask
task axi_set_b_lag;
input [3:0] lag;
begin
@(posedge CLK);
B_LAG <= lag;
end
endtask
reg [11:0] GLOBAL_WRITE_ID=0;
reg [11:0] GLOBAL_READ_ID=0;
task read_and_wait;
input [31:0] address;
begin
axi_read_addr(
GLOBAL_READ_ID, // id
address & 32'hfffffffc, // addr
4'h0, // len - single
1 // burst type - increment
);
GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
wait (!CLK && rvalid && rready);
wait (CLK);
registered_rdata <= rdata;
end
endtask
task axi_write_single; // address in bytes, not words
input [31:0] address;
input [31:0] data;
begin
`ifdef DEBUG_WR_SINGLE
$display("axi_write_single %h:%h @ %t",address,data,$time);
`endif
axi_write_addr_data(
GLOBAL_WRITE_ID, // id
// address << 2, // addr
address & 32'hfffffffc, // addr
data,
4'h0, // len - single
1, // burst type - increment
1'b1, // data_en
4'hf, // wstrb
1'b1 // last
);
GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
#0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
end
endtask
task axi_write_addr_data;
input [11:0] id;
input [31:0] addr;
input [31:0] data;
input [ 3:0] len;
input [ 1:0] burst;
input data_en; // if 0 - do not send data, only address
input [ 3:0] wstrb;
input last;
reg data_sent;
// wire data_sent_d;
// assign #(.1) data_sent_d= data_sent;
begin
wait (!CLK && AW_READY);
AWID_IN_r <= id;
AWADDR_IN_r <= addr;
AWLEN_IN_r <= len;
AWSIZE_IN_r <= 3'b010;
AWBURST_IN_r <= burst;
AW_SET_CMD_r <= 1'b1;
if (data_en && W_READY) begin
WID_IN_r <= id;
WDATA_IN_r <= data;
WSTRB_IN_r <= wstrb;
WLAST_IN_r <= last;
W_SET_CMD_r <= 1'b1;
data_sent <= 1'b1;
end else begin
data_sent <= 1'b0;
end
DEBUG1 <=1'b1;
wait (CLK);
DEBUG1 <=1'b0;
AWID_IN_r <= 'hz;
AWADDR_IN_r <= 'hz;
AWLEN_IN_r <= 'hz;
AWSIZE_IN_r <= 'hz;
AWBURST_IN_r <= 'hz;
AW_SET_CMD_r <= 1'b0;
DEBUG2 <=1'b1;
if (data_sent) begin
WID_IN_r <= 'hz;
WDATA_IN_r <= 'hz;
WSTRB_IN_r <= 'hz;
WLAST_IN_r <= 'hz;
W_SET_CMD_r <= 1'b0;
end
// Now sent data if it was not sent simultaneously with the address
if (data_en && !data_sent) begin
DEBUG3 <=1'b1;
wait (!CLK && W_READY);
DEBUG3 <=1'b0;
WID_IN_r <= id;
WDATA_IN_r <= data;
WSTRB_IN_r <= wstrb;
WLAST_IN_r <= last;
W_SET_CMD_r <= 1'b1;
wait (CLK);
DEBUG3 <=1'bx;
WID_IN_r <= 'hz;
WDATA_IN_r <= 'hz;
WSTRB_IN_r <= 'hz;
WLAST_IN_r <= 'hz;
W_SET_CMD_r <= 1'b0;
end
DEBUG2 <=1'b0;
#0.1;
data_sent <= 1'b0;
#0.1;
end
endtask
task axi_write_data;
input [11:0] id;
input [31:0] data;
input [ 3:0] wstrb;
input last;
begin
wait (!CLK && W_READY);
WID_IN_r <= id;
WDATA_IN_r <= data;
WSTRB_IN_r <= wstrb;
WLAST_IN_r <= last;
W_SET_CMD_r <= 1'b1;
wait (CLK);
WID_IN_r <= 12'hz;
WDATA_IN_r <= 'hz;
WSTRB_IN_r <= 4'hz;
WLAST_IN_r <= 1'bz;
W_SET_CMD_r <= 1'b0;
#0.1;
end
endtask
task axi_read_addr;
input [11:0] id;
input [31:0] addr;
input [ 3:0] len;
input [ 1:0] burst;
begin
wait (!CLK && AR_READY);
ARID_IN_r <= id;
ARADDR_IN_r <= addr;
ARLEN_IN_r <= len;
ARSIZE_IN_r <= 3'b010;
ARBURST_IN_r <= burst;
AR_SET_CMD_r <= 1'b1;
wait (CLK);
ARID_IN_r <= 12'hz;
ARADDR_IN_r <= 'hz;
ARLEN_IN_r <= 4'hz;
ARSIZE_IN_r <= 3'hz;
ARBURST_IN_r <= 2'hz;
AR_SET_CMD_r <= 1'b0;
LAST_ARID <= id;
end
endtask
x393.v
View file @ 575da59a
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
`include ".editor_defines"
`include ".editor_defines.vh"
module x393 #(
parameter MCONTR_WR_MASK = 'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h1c00, // AXI read address mask to generate busy
......@@ -110,6 +110,8 @@ module x393 #(
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
parameter DFLT_REFRESH_ADDR= 10'h0, // refresh sequence address in command memory
parameter DFLT_REFRESH_PERIOD= 8'h0, // default 8-bit refresh period (scale?)
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
......@@ -262,8 +264,8 @@ module x393 #(
// ,input MEMCLK
);
localparam ADDRESS_NUMBER=15;
localparam COLADDR_NUMBER=10;
// localparam ADDRESS_NUMBER=15;
// localparam COLADDR_NUMBER=10;
// Source for reset and clock
wire [3:0] fclk; // PL Clocks [3:0], output
wire [3:0] frst; // PL Clocks [3:0], output
......@@ -729,7 +731,8 @@ end
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.BUFFER_DEPTH32 (BUFFER_DEPTH32)
) mcntrl393_i (
.rst_in (axi_rst), // input
.clk_in (axi_aclk), // input
......
x393_testbench01.v 0 → 100644
View file @ 575da59a
/*******************************************************************************
* Module: x393_testbench01
* Date:2015-02-06
* Author: andrey
* Description: testbench for the initial x393.v simulation
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* x393_testbench01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_testbench01.tf is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
`include "includes/x393_simulation_parameters.vh"
)(
);
`ifdef IVERILOG
// $display("IVERILOG is defined");
`include "IVERILOG_INCLUDE.v"
`else
// $display("IVERILOG is not defined");
parameter lxtname = "x393.lxt";
`endif
`define DEBUG_WR_SINGLE 1
`define DEBUG_RD_DATA 1
`include "includes/x393_localparams.vh"
// DDR3 signals
wire SDRST;
wire SDCLK; // output
wire SDNCLK; // output
wire [ADDRESS_NUMBER-1:0] SDA; // output[14:0]
wire [ 2:0] SDBA; // output[2:0]
wire SDWE; // output
wire SDRAS; // output
wire SDCAS; // output
wire SDCKE; // output
wire SDODT; // output
wire [15:0] SDD; // inout[15:0]
wire SDDML; // inout
wire DQSL; // inout
wire NDQSL; // inout
wire SDDMU; // inout
wire DQSU; // inout
wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization"
wire MEMCLK;
// Simulation signals
reg [11:0] ARID_IN_r;
reg [31:0] ARADDR_IN_r;
reg [3:0] ARLEN_IN_r;
reg [2:0] ARSIZE_IN_r;
reg [1:0] ARBURST_IN_r;
reg [11:0] AWID_IN_r;
reg [31:0] AWADDR_IN_r;
reg [3:0] AWLEN_IN_r;
reg [2:0] AWSIZE_IN_r;
reg [1:0] AWBURST_IN_r;
reg [11:0] WID_IN_r;
reg [31:0] WDATA_IN_r;
reg [ 3:0] WSTRB_IN_r;
reg WLAST_IN_r;
reg [11:0] LAST_ARID; // last issued ARID
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [ 9:0] SIMUL_AXI_ADDR_W;
// SuppressWarnings VEditor
wire SIMUL_AXI_MISMATCH;
// SuppressWarnings VEditor
reg [31:0] SIMUL_AXI_READ;
// SuppressWarnings VEditor
reg [ 9:0] SIMUL_AXI_ADDR;
// SuppressWarnings VEditor
reg SIMUL_AXI_FULL; // some data available
reg [31:0] registered_rdata;
reg CLK;
reg RST;
reg AR_SET_CMD_r;
wire AR_READY;
reg AW_SET_CMD_r;
wire AW_READY;
reg W_SET_CMD_r;
wire W_READY;
wire [11:0] #(AXI_TASK_HOLD) ARID_IN = ARID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) ARADDR_IN = ARADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) ARLEN_IN = ARLEN_IN_r;
wire [2:0] #(AXI_TASK_HOLD) ARSIZE_IN = ARSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) ARBURST_IN = ARBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) AWID_IN = AWID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) AWADDR_IN = AWADDR_IN_r;
wire [3:0] #(AXI_TASK_HOLD) AWLEN_IN = AWLEN_IN_r;
wire [2:0] #(AXI_TASK_HOLD) AWSIZE_IN = AWSIZE_IN_r;
wire [1:0] #(AXI_TASK_HOLD) AWBURST_IN = AWBURST_IN_r;
wire [11:0] #(AXI_TASK_HOLD) WID_IN = WID_IN_r;
wire [31:0] #(AXI_TASK_HOLD) WDATA_IN = WDATA_IN_r;
wire [ 3:0] #(AXI_TASK_HOLD) WSTRB_IN = WSTRB_IN_r;
wire #(AXI_TASK_HOLD) WLAST_IN = WLAST_IN_r;
wire #(AXI_TASK_HOLD) AR_SET_CMD = AR_SET_CMD_r;
wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;
reg [3:0] RD_LAG; // ready signal lag in axi read channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
reg [3:0] B_LAG; // ready signal lag in axi arete response channel (0 - RDY=1, 1..15 - RDY is asserted N cycles after valid)
// Simulation modules interconnection
wire [11:0] arid;
wire [31:0] araddr;
wire [3:0] arlen;
wire [2:0] arsize;
wire [1:0] arburst;
// SuppressWarnings VEditor : assigned in $readmem(14) system task
wire [3:0] arcache;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [2:0] arprot;
wire arvalid;
wire arready;
wire [11:0] awid;
wire [31:0] awaddr;
wire [3:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [3:0] awcache;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [2:0] awprot;
wire awvalid;
wire awready;
wire [11:0] wid;
wire [31:0] wdata;
wire [3:0] wstrb;
wire wlast;
wire wvalid;
wire wready;
wire [31:0] rdata;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [11:0] rid;
wire rlast;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [1:0] rresp;
wire rvalid;
wire rready;
wire rstb=rvalid && rready;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [1:0] bresp;
// SuppressWarnings VEditor : assigned in $readmem() system task
wire [11:0] bid;
wire bvalid;
wire bready;
always #(CLKIN_PERIOD/2) CLK <= ~CLK;
initial begin
`ifdef IVERILOG
$display("IVERILOG is defined");
`else
$display("IVERILOG is not defined");
`endif
`ifdef ICARUS
$display("ICARUS is defined");
`else
$display("ICARUS is not defined");
`endif
$dumpfile(lxtname);
// SuppressWarnings VEditor : assigned in $readmem() system task
$dumpvars(0,ddrc_test01_testbench);
CLK <=1'b0;
RST <= 1'bx;
AR_SET_CMD_r <= 1'b0;
AW_SET_CMD_r <= 1'b0;
W_SET_CMD_r <= 1'b0;
#500;
// $display ("x393_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst=%d",x393_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.rst);
#500;
RST <= 1'b1;
#99000; // same as glbl
repeat (20) @(posedge CLK) ;
RST <=1'b0;
//set simulation-only parameters
axi_set_b_lag(0); //(1);
axi_set_rd_lag(0);
//...
end
// protect from never end
initial begin
// #10000000;
#200000;
$display("finish testbench 2");
$finish;
end
assign x393_i.ps7_i.FCLKCLK= {4{CLK}};
assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
// Read address
assign x393_i.ps7_i.MAXIGP0ARADDR= araddr;
assign x393_i.ps7_i.MAXIGP0ARVALID= arvalid;
assign arready= x393_i.ps7_i.MAXIGP0ARREADY;
assign x393_i.ps7_i.MAXIGP0ARID= arid;
assign x393_i.ps7_i.MAXIGP0ARLEN= arlen;
assign x393_i.ps7_i.MAXIGP0ARSIZE= arsize[1:0]; // arsize[2] is not used
assign x393_i.ps7_i.MAXIGP0ARBURST= arburst;
// Read data
assign rdata= x393_i.ps7_i.MAXIGP0RDATA;
assign rvalid= x393_i.ps7_i.MAXIGP0RVALID;
assign x393_i.ps7_i.MAXIGP0RREADY= rready;
assign rid= x393_i.ps7_i.MAXIGP0RID;
assign rlast= x393_i.ps7_i.MAXIGP0RLAST;
assign rresp= x393_i.ps7_i.MAXIGP0RRESP;
// Write address
assign x393_i.ps7_i.MAXIGP0AWADDR= awaddr;
assign x393_i.ps7_i.MAXIGP0AWVALID= awvalid;
assign awready= x393_i.ps7_i.MAXIGP0AWREADY;
//assign awready= AWREADY_AAAA;
assign x393_i.ps7_i.MAXIGP0AWID=awid;
// SuppressWarnings VEditor all
// wire [ 1:0] AWLOCK;
// SuppressWarnings VEditor all
// wire [ 3:0] AWCACHE;
// SuppressWarnings VEditor all
// wire [ 2:0] AWPROT;
assign x393_i.ps7_i.MAXIGP0AWLEN= awlen;
assign x393_i.ps7_i.MAXIGP0AWSIZE= awsize[1:0]; // awsize[2] is not used
assign x393_i.ps7_i.MAXIGP0AWBURST= awburst;
// SuppressWarnings VEditor all
// wire [ 3:0] AWQOS;
// Write data
assign x393_i.ps7_i.MAXIGP0WDATA= wdata;
assign x393_i.ps7_i.MAXIGP0WVALID= wvalid;
assign wready= x393_i.ps7_i.MAXIGP0WREADY;
assign x393_i.ps7_i.MAXIGP0WID= wid;
assign x393_i.ps7_i.MAXIGP0WLAST= wlast;
assign x393_i.ps7_i.MAXIGP0WSTRB= wstrb;
// Write responce
assign bvalid= x393_i.ps7_i.MAXIGP0BVALID;
assign x393_i.ps7_i.MAXIGP0BREADY= bready;
assign bid= x393_i.ps7_i.MAXIGP0BID;
assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
// Top module under test
x393 #(
.MCONTR_WR_MASK (MCONTR_WR_MASK),
.MCONTR_RD_MASK (MCONTR_RD_MASK),
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF3_WR_ADDR (MCONTR_BUF3_WR_ADDR),
.MCONTR_BUF4_RD_ADDR (MCONTR_BUF4_RD_ADDR),
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
.MCONTR_PHY_0BIT_ADDR_MASK (MCONTR_PHY_0BIT_ADDR_MASK),
.MCONTR_PHY_0BIT_DLY_SET (MCONTR_PHY_0BIT_DLY_SET),
.MCONTR_PHY_0BIT_CMDA_EN (MCONTR_PHY_0BIT_CMDA_EN),
.MCONTR_PHY_0BIT_SDRST_ACT (MCONTR_PHY_0BIT_SDRST_ACT),
.MCONTR_PHY_0BIT_CKE_EN (MCONTR_PHY_0BIT_CKE_EN),
.MCONTR_PHY_0BIT_DCI_RST (MCONTR_PHY_0BIT_DCI_RST),
.MCONTR_PHY_0BIT_DLY_RST (MCONTR_PHY_0BIT_DLY_RST),
.MCONTR_TOP_0BIT_ADDR (MCONTR_TOP_0BIT_ADDR),
.MCONTR_TOP_0BIT_ADDR_MASK (MCONTR_TOP_0BIT_ADDR_MASK),
.MCONTR_TOP_0BIT_MCONTR_EN (MCONTR_TOP_0BIT_MCONTR_EN),
.MCONTR_TOP_0BIT_REFRESH_EN (MCONTR_TOP_0BIT_REFRESH_EN),
.MCONTR_PHY_16BIT_ADDR (MCONTR_PHY_16BIT_ADDR),
.MCONTR_PHY_16BIT_ADDR_MASK (MCONTR_PHY_16BIT_ADDR_MASK),
.MCONTR_PHY_16BIT_PATTERNS (MCONTR_PHY_16BIT_PATTERNS),
.MCONTR_PHY_16BIT_PATTERNS_TRI (MCONTR_PHY_16BIT_PATTERNS_TRI),
.MCONTR_PHY_16BIT_WBUF_DELAY (MCONTR_PHY_16BIT_WBUF_DELAY),
.MCONTR_PHY_16BIT_EXTRA (MCONTR_PHY_16BIT_EXTRA),
.MCONTR_PHY_STATUS_CNTRL (MCONTR_PHY_STATUS_CNTRL),
.MCONTR_ARBIT_ADDR (MCONTR_ARBIT_ADDR),
.MCONTR_ARBIT_ADDR_MASK (MCONTR_ARBIT_ADDR_MASK),
.MCONTR_TOP_16BIT_ADDR (MCONTR_TOP_16BIT_ADDR),
.MCONTR_TOP_16BIT_ADDR_MASK (MCONTR_TOP_16BIT_ADDR_MASK),
.MCONTR_TOP_16BIT_CHN_EN (MCONTR_TOP_16BIT_CHN_EN),
.MCONTR_TOP_16BIT_REFRESH_PERIOD (MCONTR_TOP_16BIT_REFRESH_PERIOD),
.MCONTR_TOP_16BIT_REFRESH_ADDRESS (MCONTR_TOP_16BIT_REFRESH_ADDRESS),
.MCONTR_TOP_16BIT_STATUS_CNTRL (MCONTR_TOP_16BIT_STATUS_CNTRL),
.MCONTR_PHY_STATUS_REG_ADDR (MCONTR_PHY_STATUS_REG_ADDR),
.MCONTR_TOP_STATUS_REG_ADDR (MCONTR_TOP_STATUS_REG_ADDR),
.CHNBUF_READ_LATENCY (CHNBUF_READ_LATENCY),
.DFLT_DQS_PATTERN (DFLT_DQS_PATTERN),
.DFLT_DQM_PATTERN (DFLT_DQM_PATTERN),
.DFLT_DQ_TRI_ON_PATTERN (DFLT_DQ_TRI_ON_PATTERN),
.DFLT_DQ_TRI_OFF_PATTERN (DFLT_DQ_TRI_OFF_PATTERN),
.DFLT_DQS_TRI_ON_PATTERN (DFLT_DQS_TRI_ON_PATTERN),
.DFLT_DQS_TRI_OFF_PATTERN (DFLT_DQS_TRI_OFF_PATTERN),
.DFLT_WBUF_DELAY (DFLT_WBUF_DELAY),
.DFLT_INV_CLK_DIV (DFLT_INV_CLK_DIV),
.DFLT_CHN_EN (DFLT_CHN_EN),
.DFLT_REFRESH_ADDR (DFLT_REFRESH_ADDR),
.DFLT_REFRESH_PERIOD (DFLT_REFRESH_PERIOD),
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.PHASE_WIDTH (PHASE_WIDTH),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
.SLEW_CMDA (SLEW_CMDA),
.SLEW_CLK (SLEW_CLK),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
.REF_JITTER1 (REF_JITTER1),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT),
.STATUS_ADDR (STATUS_ADDR),
.STATUS_ADDR_MASK (STATUS_ADDR_MASK),
.STATUS_DEPTH (STATUS_DEPTH),
.AXI_WR_ADDR_BITS (AXI_WR_ADDR_BITS),
.AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
.CONTROL_ADDR (CONTROL_ADDR),
.CONTROL_ADDR_MASK (CONTROL_ADDR_MASK),
.NUM_CYCLES_LOW_BIT (NUM_CYCLES_LOW_BIT),
.NUM_CYCLES_00 (NUM_CYCLES_00),
.NUM_CYCLES_01 (NUM_CYCLES_01),
.NUM_CYCLES_02 (NUM_CYCLES_02),
.NUM_CYCLES_03 (NUM_CYCLES_03),
.NUM_CYCLES_04 (NUM_CYCLES_04),
.NUM_CYCLES_05 (NUM_CYCLES_05),
.NUM_CYCLES_06 (NUM_CYCLES_06),
.NUM_CYCLES_07 (NUM_CYCLES_07),
.NUM_CYCLES_08 (NUM_CYCLES_08),
.NUM_CYCLES_09 (NUM_CYCLES_09),
.NUM_CYCLES_10 (NUM_CYCLES_10),
.NUM_CYCLES_11 (NUM_CYCLES_11),
.NUM_CYCLES_12 (NUM_CYCLES_12),
.NUM_CYCLES_13 (NUM_CYCLES_13),
.NUM_CYCLES_14 (NUM_CYCLES_14),
.NUM_CYCLES_15 (NUM_CYCLES_15),
.MCNTRL_PS_ADDR (MCNTRL_PS_ADDR),
.MCNTRL_PS_MASK (MCNTRL_PS_MASK),
.MCNTRL_PS_STATUS_REG_ADDR (MCNTRL_PS_STATUS_REG_ADDR),
.MCNTRL_PS_EN_RST (MCNTRL_PS_EN_RST),
.MCNTRL_PS_CMD (MCNTRL_PS_CMD),
.MCNTRL_PS_STATUS_CNTRL (MCNTRL_PS_STATUS_CNTRL),
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_SCANLINE_CHN2_ADDR (MCNTRL_SCANLINE_CHN2_ADDR),
.MCNTRL_SCANLINE_CHN3_ADDR (MCNTRL_SCANLINE_CHN3_ADDR),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
.MCNTRL_SCANLINE_STATUS_CNTRL (MCNTRL_SCANLINE_STATUS_CNTRL),
.MCNTRL_SCANLINE_STARTADDR (MCNTRL_SCANLINE_STARTADDR),
.MCNTRL_SCANLINE_FRAME_FULL_WIDTH (MCNTRL_SCANLINE_FRAME_FULL_WIDTH),
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.MCNTRL_TEST01_ADDR (MCNTRL_TEST01_ADDR),
.MCNTRL_TEST01_MASK (MCNTRL_TEST01_MASK),
.MCNTRL_TEST01_CHN2_MODE (MCNTRL_TEST01_CHN2_MODE),
.MCNTRL_TEST01_CHN2_STATUS_CNTRL (MCNTRL_TEST01_CHN2_STATUS_CNTRL),
.MCNTRL_TEST01_CHN3_MODE (MCNTRL_TEST01_CHN3_MODE),
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) x393_i (
.SDRST (SDRST), // DDR3 reset (active low)
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // outputread_and_wait(BASEADDR_STATUS)
.SDA (SDA[14:0]), // output[14:0]
.SDBA (SDBA[2:0]), // output[2:0]
.SDWE (SDWE), // output
.SDRAS (SDRAS), // output
.SDCAS (SDCAS), // output
.SDCKE (SDCKE), // output
.SDODT (SDODT), // output
.SDD (SDD[15:0]), // inout[15:0]
.SDDML (SDDML), // inout
.DQSL (DQSL), // inout
.NDQSL (NDQSL), // inout
.SDDMU (SDDMU), // inout
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.DUMMY_TO_KEEP(DUMMY_TO_KEEP), // to keep PS7 signals from "optimization"
.MEMCLK (MEMCLK)
);
// Micron DDR3 memory model
/* Instance of Micron DDR3 memory model */
ddr3 #(
.TCK_MIN (2500),
.TJIT_PER (100),
.TJIT_CC (200),
.TERR_2PER (147),
.TERR_3PER (175),
.TERR_4PER (194),
.TERR_5PER (209),
.TERR_6PER (222),
.TERR_7PER (232),
.TERR_8PER (241),
.TERR_9PER (249),
.TERR_10PER (257),
.TERR_11PER (263),
.TERR_12PER (269),
.TDS (125),
.TDH (150),
.TDQSQ (200),
.TDQSS (0.25),
.TDSS (0.20),
.TDSH (0.20),
.TDQSCK (400),
.TQSH (0.38),
.TQSL (0.38),
.TDIPW (600),
.TIPW (900),
.TIS (350),
.TIH (275),
.TRAS_MIN (37500),
.TRC (52500),
.TRCD (15000),
.TRP (15000),
.TXP (7500),
.TCKE (7500),
.TAON (400),
.TWLS (325),
.TWLH (325),
.TWLO (9000),
.TAA_MIN (15000),
.CL_TIME (15000),
.TDQSCK_DLLDIS (400),
.TRRD (10000),
.TFAW (40000),
.CL_MIN (5),
.CL_MAX (14),
.AL_MIN (0),
.AL_MAX (2),
.WR_MIN (5),
.WR_MAX (16),
.BL_MIN (4),
.BL_MAX (8),
.CWL_MIN (5),
.CWL_MAX (10),
.TCK_MAX (3300),
.TCH_AVG_MIN (0.47),
.TCL_AVG_MIN (0.47),
.TCH_AVG_MAX (0.53),
.TCL_AVG_MAX (0.53),
.TCH_ABS_MIN (0.43),
.TCL_ABS_MIN (0.43),
.TCKE_TCK (3),
.TAA_MAX (20000),
.TQH (0.38),
.TRPRE (0.90),
.TRPST (0.30),
.TDQSH (0.45),
.TDQSL (0.45),
.TWPRE (0.90),
.TWPST (0.30),
.TCCD (4),
.TCCD_DG (2),
.TRAS_MAX (60e9),
.TWR (15000),
.TMRD (4),
.TMOD (15000),
.TMOD_TCK (12),
.TRRD_TCK (4),
.TRRD_DG (3000),
.TRRD_DG_TCK (2),
.TRTP (7500),
.TRTP_TCK (4),
.TWTR (7500),
.TWTR_DG (3750),
.TWTR_TCK (4),
.TWTR_DG_TCK (2),
.TDLLK (512),
.TRFC_MIN (260000),
.TRFC_MAX (70200000),
.TXP_TCK (3),
.TXPDLL (24000),
.TXPDLL_TCK (10),
.TACTPDEN (1),
.TPRPDEN (1),
.TREFPDEN (1),
.TCPDED (1),
.TPD_MAX (70200000),
.TXPR (270000),
.TXPR_TCK (5),
.TXS (270000),
.TXS_TCK (5),
.TXSDLL (512),
.TISXR (350),
.TCKSRE (10000),
.TCKSRE_TCK (5),
.TCKSRX (10000),
.TCKSRX_TCK (5),
.TCKESR_TCK (4),
.TAOF (0.7),
.TAONPD (8500),
.TAOFPD (8500),
.ODTH4 (4),
.ODTH8 (6),
.TADC (0.7),
.TWLMRD (40),
.TWLDQSEN (25),
.TWLOE (2000),
.DM_BITS (2),
.ADDR_BITS (15),
.ROW_BITS (15),
.COL_BITS (10),
.DQ_BITS (16),
.DQS_BITS (2),
.BA_BITS (3),
.MEM_BITS (10),
.AP (10),
.BC (12),
.BL_BITS (3),
.BO_BITS (2),
.CS_BITS (1),
.RANKS (1),
.RZQ (240),
.PRE_DEF_PAT (8'hAA),
.STOP_ON_ERROR (1),
.DEBUG (1),
.BUS_DELAY (0),
.RANDOM_OUT_DELAY (0),
.RANDOM_SEED (31913),
.RDQSEN_PRE (2),
.RDQSEN_PST (1),
.RDQS_PRE (2),
.RDQS_PST (1),
.RDQEN_PRE (0),
.RDQEN_PST (0),
.WDQS_PRE (2),
.WDQS_PST (1),
.check_strict_mrbits (1),
.check_strict_timing (1),
.feature_pasr (1),
.feature_truebl4 (0),
.feature_odt_hi (0),
.PERTCKAVG (512),
.LOAD_MODE (4'b0000),
.REFRESH (4'b0001),
.PRECHARGE (4'b0010),
.ACTIVATE (4'b0011),
.WRITE (4'b0100),
.READ (4'b0101),
.ZQ (4'b0110),
.NOP (4'b0111),
.PWR_DOWN (4'b1000),
.SELF_REF (4'b1001),
.RFF_BITS (128),
.RFF_CHUNK (32),
.SAME_BANK (2'd0),
.DIFF_BANK (2'd1),
.DIFF_GROUP (2'd2),
.SIMUL_500US (5),
.SIMUL_200US (2)
) ddr3_i (
.rst_n (SDRST), // input
.ck (SDCLK), // input
.ck_n (SDNCLK), // input
.cke (SDCKE), // input
.cs_n (1'b0), // input
.ras_n (SDRAS), // input
.cas_n (SDCAS), // input
.we_n (SDWE), // input
.dm_tdqs ({SDDMU,SDDML}), // inout[1:0]
.ba (SDBA[2:0]), // input[2:0]
.addr (SDA[14:0]), // input[14:0]
.dq (SDD[15:0]), // inout[15:0]
.dqs ({DQSU,DQSL}), // inout[1:0]
.dqs_n ({NDQSU,NDQSL}), // inout[1:0]
.tdqs_n (), // output[1:0]
.odt (SDODT) // input
);
// Simulation modules
simul_axi_master_rdaddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_RDADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_rdaddr_i (
.clk(CLK),
.reset(RST),
.arid_in(ARID_IN[11:0]),
.araddr_in(ARADDR_IN[31:0]),
.arlen_in(ARLEN_IN[3:0]),
.arsize_in(ARSIZE_IN[2:0]),
.arburst_in(ARBURST_IN[1:0]),
.arcache_in(4'b0),
.arprot_in(3'b0), // .arprot_in(2'b0),
.arid(arid[11:0]),
.araddr(araddr[31:0]),
.arlen(arlen[3:0]),
.arsize(arsize[2:0]),
.arburst(arburst[1:0]),
.arcache(arcache[3:0]),
.arprot(arprot[2:0]),
.arvalid(arvalid),
.arready(arready),
.set_cmd(AR_SET_CMD), // latch all other input data at posedge of clock
.ready(AR_READY) // command/data FIFO can accept command
);
simul_axi_master_wraddr
#(
.ID_WIDTH(12),
.ADDRESS_WIDTH(32),
.LATENCY(AXI_WRADDR_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.5),
.VALID_DELAY(4.0)
) simul_axi_master_wraddr_i (
.clk(CLK),
.reset(RST),
.awid_in(AWID_IN[11:0]),
.awaddr_in(AWADDR_IN[31:0]),
.awlen_in(AWLEN_IN[3:0]),
.awsize_in(AWSIZE_IN[2:0]),
.awburst_in(AWBURST_IN[1:0]),
.awcache_in(4'b0),
.awprot_in(3'b0), //.awprot_in(2'b0),
.awid(awid[11:0]),
.awaddr(awaddr[31:0]),
.awlen(awlen[3:0]),
.awsize(awsize[2:0]),
.awburst(awburst[1:0]),
.awcache(awcache[3:0]),
.awprot(awprot[2:0]),
.awvalid(awvalid),
.awready(awready),
.set_cmd(AW_SET_CMD), // latch all other input data at posedge of clock
.ready(AW_READY) // command/data FIFO can accept command
);
simul_axi_master_wdata
#(
.ID_WIDTH(12),
.DATA_WIDTH(32),
.WSTB_WIDTH(4),
.LATENCY(AXI_WRDATA_LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(8), // maximal number of commands in FIFO
.DATA_DELAY(3.2),
.VALID_DELAY(3.6)
) simul_axi_master_wdata_i (
.clk(CLK),
.reset(RST),
.wid_in(WID_IN[11:0]),
.wdata_in(WDATA_IN[31:0]),
.wstrb_in(WSTRB_IN[3:0]),
.wlast_in(WLAST_IN),
.wid(wid[11:0]),
.wdata(wdata[31:0]),
.wstrb(wstrb[3:0]),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.set_cmd(W_SET_CMD), // latch all other input data at posedge of clock
.ready(W_READY) // command/data FIFO can accept command
);
simul_axi_slow_ready simul_axi_slow_ready_read_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(RD_LAG), //input [3:0] delay,
.valid(rvalid), // input valid,
.ready(rready) //output ready
);
simul_axi_slow_ready simul_axi_slow_ready_write_resp_i(
.clk(CLK),
.reset(RST), //input reset,
.delay(B_LAG), //input [3:0] delay,
.valid(bvalid), // input ADDRESS_NUMBER+2:0 valid,
.ready(bready) //output ready
);
simul_axi_read simul_axi_read_i(
.clk(CLK),
.reset(RST),
.last(rlast),
.data_stb(rstb),
.raddr(ARADDR_IN[11:2]),
.rlen(ARLEN_IN),
.rcmd(AR_SET_CMD),
.addr_out(SIMUL_AXI_ADDR_W),
.burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug
// wire [ 3:0] SIMUL_ADD_ADDR;
always @ (posedge CLK) begin
if (RST) SIMUL_AXI_FULL <=0;
else if (rstb) SIMUL_AXI_FULL <=1;
if (rstb) begin
SIMUL_AXI_ADDR <= SIMUL_AXI_ADDR_W;
SIMUL_AXI_READ <= rdata;
`ifdef DEBUG_RD_DATA
$display (" Read data (addr:data): 0x%x:0x%x @%t",SIMUL_AXI_ADDR_W,rdata,$time);
`endif
end
end
// SuppressWarnings VEditor all - these variables are just for viewing, not used anywhere else
reg DEBUG1, DEBUG2, DEBUG3;
`include "includes/x393_tasks01.vh"
endmodule
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