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Commit 56006910 authored by Andrey Filippov's avatar Andrey Filippov
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another memory sequence encoder module

parent 7faa227a
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Showing with 245 additions and 4 deletions
memctrl/cmd_encod_linear_rd.v 0 → 100644
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memctrl/cmd_encod_linear_wr.v
View file @ 56006910
...@@ -59,7 +59,7 @@ module cmd_encod_linear_wr #( ...@@ -59,7 +59,7 @@ module cmd_encod_linear_wr #(
localparam ENC_CMD_WRITE= 1; localparam ENC_CMD_WRITE= 1;
localparam ENC_CMD_PRECHARGE=2; localparam ENC_CMD_PRECHARGE=2;
localparam ENC_CMD_ACTIVATE= 3; localparam ENC_CMD_ACTIVATE= 3;
localparam PAUSE_ADDR=4; localparam REPEAT_ADDR=4;
localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic) localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)
localparam CMD_WRITE= 3; localparam CMD_WRITE= 3;
...@@ -97,13 +97,13 @@ module cmd_encod_linear_wr #( ...@@ -97,13 +97,13 @@ module cmd_encod_linear_wr #(
if (rst) gen_addr <= 0; if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0; else if (!start && !gen_run) gen_addr <= 0;
else if ((gen_addr==(PAUSE_ADDR-1)) && (num128[5:1]==0)) gen_addr <= PAUSE_ADDR+1; // skip loop alltogeter else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[5:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
else if ((gen_addr !=PAUSE_ADDR) || (num128[5:1]==0)) gen_addr <= gen_addr+1; // not in a loop else if ((gen_addr !=REPEAT_ADDR) || (num128[5:1]==0)) gen_addr <= gen_addr+1; // not in a loop
if (rst) num128 <= 0; if (rst) num128 <= 0;
else if (start) num128 <= num128_in; else if (start) num128 <= num128_in;
else if (!gen_run) gen_addr <= 0; // else if (!gen_run) gen_addr <= 0; //
else if ((gen_addr == (PAUSE_ADDR-1)) || (gen_addr ==PAUSE_ADDR)) num128 <= num128 -1; else if ((gen_addr == (REPEAT_ADDR-1)) || (gen_addr == REPEAT_ADDR)) num128 <= num128 -1;
end end
always @ (posedge clk) if (start) begin always @ (posedge clk) if (start) begin
...@@ -126,6 +126,7 @@ module cmd_encod_linear_wr #( ...@@ -126,6 +126,7 @@ module cmd_encod_linear_wr #(
4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT); 4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT); 4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE); 4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
endcase endcase
end end
always @ (posedge rst or posedge clk) begin always @ (posedge rst or posedge clk) begin
......
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