ran some tests with TEST_SCANLINE_WRITE, fixed some bugs

includes/x393_tasks_mcntrl_buffers.vh

@@ -19,7 +19,60 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-//MCONTR_BUF1_WR_ADDR
+task write_block_scanline_chn;  // S uppressThisWarning VEditor : may be unused
+    input integer chn; // buffer channel
+    input   [1:0] page;
+    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
+    input integer startX;
+    input integer startY;
+    reg    [29:0] start_addr;
+    begin
+        case (chn)
+            1:  start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
+            3:  start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
+            default: begin
+                $display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
+                start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
+            end
+        endcase
+        write_block_incremtal (start_addr, num_words, startX+startY<<16);
+    end
+endtask
+
+
+task write_block_incremtal;
+    input [29:0] start_word_address;
+    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
+    input integer start_value;      
+    integer i, j;
+    begin
+        $display("**** write_block_buf  @%t", $time);
+        for (i = 0; i < num_words; i = i + 16) begin
+            axi_write_addr_data(
+                i,    // id
+                {start_word_address,2'b0}+( i << 2),
+                start_value+i,
+                4'hf, // len
+                1,    // burst type - increment
+                1'b1, // data_en
+                4'hf, // wstrb
+                1'b0 // last
+                );
+//            $display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
+            $display("+Write block incremental (addr:data): 0x%x:0x%08x @%t", i, start_value+i, $time);
+            for (j = 1; j < 16; j = j + 1) begin
+                axi_write_data(
+                    i,        // id
+                    start_value+i+j,
+                    4'hf, // wstrb
+                    (1 == 15) ? 1 : 0 // last
+                    );
+                $display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
+            end
+        end
+    end
+endtask
+
 task write_block_buf_chn;  // S uppressThisWarning VEditor : may be unused
     input integer chn; // buffer channel
     input   [1:0] page;
@@ -68,7 +121,6 @@ task write_block_buf;
                     (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
             end
         end
-
     end
 endtask
    

memctrl/cmd_encod_linear_rd.v

@@ -34,6 +34,7 @@ module  cmd_encod_linear_rd #(
 //    parameter BASEADDR = 0,
     parameter ADDRESS_NUMBER=       15,
     parameter COLADDR_NUMBER=       10,
+    parameter NUM_XFER_BITS=         6,    // number of bits to specify transfer length
     parameter CMD_PAUSE_BITS=       10,
     parameter CMD_DONE_BIT=         10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
 ) (
@@ -45,7 +46,7 @@ module  cmd_encod_linear_rd #(
     input                  [2:0] bank_in,     // bank address
     input   [ADDRESS_NUMBER-1:0] row_in,      // memory row
     input   [COLADDR_NUMBER-4:0] start_col,   // start memory column in 8-bursts
-    input                  [5:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
+    input    [NUM_XFER_BITS-1:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
     input                        start,       // start generating commands
     output reg            [31:0] enc_cmd,     // encoded commnad
     output reg                   enc_wr,      // write encoded command
@@ -78,7 +79,7 @@ module  cmd_encod_linear_rd #(
     reg   [ADDRESS_NUMBER-1:0] row;     // memory row
     reg   [COLADDR_NUMBER-4:0] col;     // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
     reg                  [2:0] bank;    // memory bank;
-    reg                  [5:0] num128;  // number of 128-bit words to transfer
+    reg    [NUM_XFER_BITS-1:0] num128;  // number of 128-bit words to transfer
     
     reg                        gen_run;
     reg                        gen_run_d;
@@ -106,8 +107,8 @@ module  cmd_encod_linear_rd #(
 
         if (rst)                     gen_addr <= 0;
         else if (!start && !gen_run) gen_addr <= 0;
-        else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[5:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
-        else if ((gen_addr !=REPEAT_ADDR) || (num128[5:1]==0)) gen_addr <= gen_addr+1; // not in a loop
+        else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
+        else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= gen_addr+1; // not in a loop
 //counting loops?        
         if      (rst)          num128 <= 0;
         else if (start)        num128 <= num128_in;

memctrl/mcntrl393.v

@@ -916,6 +916,7 @@ module  mcntrl393 #(
     cmd_encod_linear_rd #(
         .ADDRESS_NUMBER  (ADDRESS_NUMBER),
         .COLADDR_NUMBER  (COLADDR_NUMBER),
+        .NUM_XFER_BITS   (NUM_XFER_BITS),
         .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
         .CMD_DONE_BIT    (CMD_DONE_BIT)
     ) cmd_encod_linear_rd_i (
@@ -935,6 +936,7 @@ module  mcntrl393 #(
     cmd_encod_linear_wr #(
         .ADDRESS_NUMBER  (ADDRESS_NUMBER),
         .COLADDR_NUMBER  (COLADDR_NUMBER),
+        .NUM_XFER_BITS   (NUM_XFER_BITS),
         .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
         .CMD_DONE_BIT  (CMD_DONE_BIT)
     ) cmd_encod_linear_wr_i (

memctrl/mcntrl_linear_rw.v

@@ -152,8 +152,8 @@ module  mcntrl_linear_rw #(
     reg   [FRAME_HEIGHT_BITS-1:0] window_y0;      // (programmed) window top
     reg    [FRAME_WIDTH_BITS-1:0] start_x;        // (programmed) normally 0, copied to curr_x on frame_start  
     reg   [FRAME_HEIGHT_BITS-1:0] start_y;        // (programmed) normally 0, copied to curr_y on frame_start 
-    
-    
+    reg                           xfer_done_d;    // xfer_done delayed by 1 cycle;
+ //   reg                           no_more_needed; // frame finished, no more requests is needed
     assign set_mode_w =         cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
     assign set_status_w =       cmd_we && (cmd_a== MCNTRL_SCANLINE_STATUS_CNTRL);
     assign set_start_addr_w =   cmd_we && (cmd_a== MCNTRL_SCANLINE_STARTADDR);
@@ -205,6 +205,8 @@ module  mcntrl_linear_rw #(
     assign xfer_reset_page = xfer_reset_page_r;
     assign frame_done=  frame_done_r;
     assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
+//    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;
+    //
     assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
     assign last_row_w=  next_y==window_height;
     assign xfer_want=   want_r;
@@ -261,6 +263,19 @@ module  mcntrl_linear_rw #(
         else if (frame_start)  busy_r <= 1;
         else if (frame_done_r) busy_r <= 0;
         
+        if (rst)          xfer_done_d <= 0;
+        else              xfer_done_d <= xfer_done;
+        
+
+        if      (rst)                                                       frame_done_r <= 0;
+        else if (chn_rst || frame_start)                                    frame_done_r <= 0;
+        else if (busy_r && last_block && xfer_done_d && (pending_xfers==0)) frame_done_r <= 1;
+
+//        if (rst)          frame_done_r <= 0;
+//        else              frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
+        
+        
+        
         if (rst) xfer_start_r <= 0;
         else     xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
         
@@ -273,9 +288,9 @@ module  mcntrl_linear_rw #(
         else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
         
         if (rst)                                 page_cntr <= 0;
-        else if (frame_start)                    page_cntr <= cmd_wrmem?0:4;
-        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;     
-        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr - 1;
+        else if (frame_start)                    page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end?
+        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr - 1;     
+        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr + 1;
         
 /*
         if (rst)                         xfer_page_r <= 0;
@@ -298,15 +313,20 @@ module  mcntrl_linear_rw #(
                
         if      (rst)                         last_block <= 0;
         else if (chn_rst || !busy_r)          last_block <= 0;
-        else if (last_row_w && last_in_row_w) last_block <= 1;
+//        else if (last_row_w && last_in_row_w) last_block <= 1;
+        else if (xfer_start_r[0])             last_block <= last_row_w && last_in_row_w;
         
         if      (rst)                            pending_xfers <= 0;
         else if (chn_rst || !busy_r)             pending_xfers <= 0;
         else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;     
         else if (!xfer_start_r[0] &&  xfer_done) pending_xfers <= pending_xfers - 1;
         
-        if (rst)          frame_done_r <= 0;
-        else              frame_done_r <= busy_r && last_block && xfer_done && (pending_xfers==0);
+        
+//        else              frame_done_r <= busy_r && no_more_needed && xfer_done && (pending_xfers==0);
+        
+//       if (rst)                          no_more_needed <= 0;
+//       else if (chn_rst || !busy_r)      no_more_needed <= 0;
+//       else if (xfer_start_r[0])         no_more_needed <= last_block;
         
         //line_unfinished_r cmd_wrmem
         if (rst)                         line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};

memctrl/mcntrl_tiled_rw.v

@@ -24,6 +24,7 @@
 module  mcntrl_tiled_rw#(
    parameter ADDRESS_NUMBER=                   15,
     parameter COLADDR_NUMBER=                   10,
+    parameter NUM_XFER_BITS=                     6,    // number of bits to specify transfer length
     parameter FRAME_WIDTH_BITS=                 13,    // Maximal frame width - 8-word (16 bytes) bursts 
     parameter FRAME_HEIGHT_BITS=                16,    // Maximal frame height 
     parameter MAX_TILE_WIDTH=                   6,     // number of bits to specify maximal tile (width-1) (6 -> 64)

memctrl/memctrl16.v

@@ -578,7 +578,7 @@ wire rst=rst_in; // TODO: decide where toi generate
     reg             cmd_seq_refresh;     // sequencer is running refresh
     reg    [10:0]   cmd_seq_addr;   // start address of the command sequencer (MSB - bank: 0 - PS, 1:PL): valid with cmd_seq_run
 
-    wire            sel_refresh_w;  // select refresh over channel
+    wire            sel_refresh_w;  // select refresh over channel, only valid @ a single-cycle pre_run_seq_w
     wire            pre_run_seq_w;  // initiate run sequence next cycle
     wire            pre_run_chn_w;  // initiate run sequence next cycle for a channel (not refresh)
     wire            mcontr_reset;   // reset controller, generated with ddr_rst in the sequencer
@@ -758,7 +758,10 @@ wire rst=rst_in; // TODO: decide where toi generate
 assign mcontr_enabled=mcontr_en && !mcontr_reset; 
 //assign sel_refresh_w= refresh_need || (refresh_want && (!cmd_seq_need || !(cmd_seq_full || (cmd_seq_fill && seq_set ))));  
 assign sel_refresh_w= refresh_need || (refresh_want && !(cmd_seq_need && cmd_seq_full));
-assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !refresh_grant && (cmd_seq_full || refresh_need || refresh_want);
+//assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !refresh_grant && (cmd_seq_full || refresh_need || refresh_want);
+//assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !refresh_grant && !cmd_seq_run && (cmd_seq_full || refresh_want);
+assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !cmd_seq_run && (cmd_seq_full || refresh_want);
+
 assign pre_run_chn_w= pre_run_seq_w && !sel_refresh_w;
 assign en_schedul= mcontr_enabled && !cmd_seq_fill && !cmd_seq_full;
 
@@ -1225,7 +1228,7 @@ end
 /// Combine read data from multiple channel buffers
 wire [3:0] ext_buf_rchn_late;
 wire       ext_buf_rd_late; 
-localparam [3:0] EXT_READ_LATENCY=CHNBUF_READ_LATENCY+1;
+localparam [3:0] EXT_READ_LATENCY=CHNBUF_READ_LATENCY+2; // +1;
     dly_16 #(
         .WIDTH(5)
     ) dly_16_i (

x393_testbench01.sav

 [*]
 [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
-[*] Sat Feb 14 08:08:56 2015
+[*] Sun Feb 15 05:48:02 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150213233756874.lxt"
-[dumpfile_mtime] "Sat Feb 14 06:45:49 2015"
-[dumpfile_size] 133654536
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150214223135659.lxt"
+[dumpfile_mtime] "Sun Feb 15 05:39:28 2015"
+[dumpfile_size] 371031838
 [savefile] "/home/andrey/git/x393/x393_testbench01.sav"
-[timestart] 150882500
-[size] 1823 1180
-[pos] 1934 -3
-*-14.698502 150936875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[timestart] 154325000
+[size] 1823 1173
+[pos] 1937 0
+*-17.698502 154934323 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench01.
 [treeopen] x393_testbench01.x393_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
@@ -25,11 +26,12 @@
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
+[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
 [treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
-[sst_width] 328
-[signals_width] 445
+[sst_width] 324
+[signals_width] 310
 [sst_expanded] 1
-[sst_vpaned_height] 377
+[sst_vpaned_height] 380
 @800200
 -top_simulation
 @28
@@ -866,8 +868,8 @@ x393_testbench01.x393_i.SDCKE[0]
 x393_testbench01.x393_i.SDCLK[0]
 @22
 x393_testbench01.x393_i.SDA[14:0]
-@28
 x393_testbench01.x393_i.SDBA[2:0]
+@28
 x393_testbench01.x393_i.SDRAS[0]
 x393_testbench01.x393_i.SDCAS[0]
 x393_testbench01.x393_i.SDWE[0]
@@ -879,7 +881,6 @@ x393_testbench01.x393_i.SDDML[0]
 x393_testbench01.x393_i.SDDMU[0]
 @22
 x393_testbench01.x393_i.SDD[15:0]
-@28
 x393_testbench01.x393_i.SDODT[0]
 @1000200
 -DDR3
@@ -1305,7 +1306,7 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
 x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
 @1401200
 -mcntrl393_test01
-@c00200
+@800200
 -linear_ch3
 @28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.busy_r[0]
@@ -1363,12 +1364,18 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.need_r[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.next_page[0]
 @22
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.next_y[16:0]
-@28
+@c00022
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.page_cntr[2:0]
+@28
+(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.page_cntr[2:0]
+(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.page_cntr[2:0]
+(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.page_cntr[2:0]
+@1401200
+-group_end
 @22
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.par_mod_r[6:0]
-@28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pending_xfers[1:0]
+@28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pgm_param_w[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.pre_want[0]
 @22
@@ -1400,12 +1407,37 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_height[16:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_width[13:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_x0[12:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.window_y0[15:0]
+@800200
+-other
 @28
-x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_bank[2:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.en_schedul[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.grant[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.grant_chn[3:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_busy[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_chn_w[0]
+@29
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.refresh_grant[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.grant_r[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.refresh_want[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.refresh_need[0]
+@200
+-
+@1000200
+-other
 @22
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_bank[2:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_col[6:0]
 @28
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_done[0]
+x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_done_d[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_grant[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_need[0]
 @22
@@ -1420,13 +1452,13 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_row[14:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start_r[2:0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_want[0]
-@1401200
+@1000200
 -linear_ch3
-@800200
+@c00200
 -cmd1_buf
 @28
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel[0]
-@23
+@22
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
 @28
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_done[0]
@@ -1456,12 +1488,155 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.wc
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we[0]
 @22
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0]
-@1000200
+@1401200
 -cmd1_buf
 @200
 -
 @800200
 -encod_linear_wr
+@200
+-
+@c00200
+-ch3_buf
+@22
+x393_testbench01.x393_i.mcntrl393_i.axiwr_pre_awaddr[12:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.axiwr_wen[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata[63:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata3[63:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata1[63:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.buf_rd_chn[0]
+@800028
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.latency_reg[1:0]
+@28
+(0)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.latency_reg[1:0]
+(1)x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.latency_reg[1:0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.buf_rdata_chn[63:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_rdata_chn3[63:0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.ext_buf_rdata[63:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd[0]
+x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd_late[0]
+@1001200
+-group_end
+@200
+-
+@22
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.data_out[63:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ext_clk[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ext_data_in[31:0]
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ext_waddr[9:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ext_we[0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.page[1:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.page_next[0]
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.page_r[1:0]
+@22
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.raddr[6:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.rclk[0]
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.rd[0]
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.regen[0]
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.rpage_in[1:0]
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.rpage_set[0]
+@200
+-
+@22
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ram_1kx32w_512x64r_i.waddr[9:0]
+@28
+x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.ram_1kx32w_512x64r_i.we[0]
+@1401200
+-ch3_buf
+@c00200
+-write_block_scanline_chn
+@22
+x393_testbench01.write_block_scanline_chn.chn[31:0]
+x393_testbench01.write_block_scanline_chn.num_words[31:0]
+x393_testbench01.write_block_scanline_chn.page[1:0]
+x393_testbench01.write_block_scanline_chn.startX[31:0]
+x393_testbench01.write_block_scanline_chn.startY[31:0]
+x393_testbench01.write_block_scanline_chn.start_addr[29:0]
+@200
+-
+@22
+x393_testbench01.write_block_incremtal.i[31:0]
+x393_testbench01.write_block_incremtal.j[31:0]
+x393_testbench01.write_block_incremtal.num_words[31:0]
+x393_testbench01.write_block_incremtal.start_value[31:0]
+x393_testbench01.write_block_incremtal.start_word_address[29:0]
+@1401200
+-write_block_scanline_chn
+@200
+-
+@22
+x393_testbench01.ii[31:0]
+@28
+x393_testbench01.wait_status_condition.invert_match[0]
+@22
+x393_testbench01.wait_status_condition.mask[25:0]
+@28
+x393_testbench01.wait_status_condition.match[0]
+@22
+x393_testbench01.wait_status_condition.pattern[25:0]
+x393_testbench01.wait_status_condition.seq_num[5:0]
+x393_testbench01.wait_status_condition.status_address[7:0]
+x393_testbench01.wait_status_condition.status_control_address[29:0]
+@28
+x393_testbench01.wait_status_condition.status_mode[1:0]
+@800200
+-test_chn3
+@22
+x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0]
+@28
+x393_testbench01.x393_i.mcntrl393_test01_i.status_rq[0]
+x393_testbench01.x393_i.mcntrl393_test01_i.status_start[0]
+x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn3[0]
+x393_testbench01.x393_i.mcntrl393_test01_i.frame_done_chn3[0]
+x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn3[0]
+@22
+x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn3[15:0]
+@28
+x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn3[0]
+@22
+x393_testbench01.x393_i.mcntrl393_test01_i.page_chn3[3:0]
+@28
+x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0]
+@c00022
+x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+@28
+(0)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(1)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(2)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(3)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(4)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(5)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(6)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(7)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(8)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(9)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(10)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(11)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(12)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(13)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(14)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(15)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(16)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(17)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(18)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(19)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(20)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+(21)x393_testbench01.x393_i.mcntrl393_test01_i.status_chn3[21:0]
+@1401200
+-group_end
+@1000200
+-test_chn3
 @28
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_wr[0]
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_set[0]
@@ -2027,7 +2202,7 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
 @1401200
 -PS_PIO
-@800200
+@c00200
 -memcntrl16_0
 @22
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0]
@@ -2136,6 +2311,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we
 x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0]
 @1000200
 -cmd0_buf
+@1401200
 -memcntrl16_0
 @c00200
 -max_0001

x393_testbench01.tf

@@ -23,10 +23,10 @@
 `define DEBUG_FIFO 1
 `undef WAIT_MRS
 `define SET_PER_PIN_DEALYS 1 // set individual (including per-DQ pin delays)
-`define TEST_WRITE_LEVELLING 1
-`define TEST_READ_PATTERN 1
-`define TEST_WRITE_BLOCK 1
-`define TEST_READ_BLOCK 1
+//`define TEST_WRITE_LEVELLING 1
+//`define TEST_READ_PATTERN 1
+//`define TEST_WRITE_BLOCK 1
+//`define TEST_READ_BLOCK 1
 `define TEST_SCANLINE_WRITE 1
 `define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
 
@@ -187,15 +187,22 @@ module  x393_testbench01 #(
   localparam       FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
   localparam       FRAME_FULL_WIDTH=    'h0c0;  // Padded line length (8-row increment), in 8-bursts (16 bytes)
 //  localparam SCANLINE_WINDOW_WH=  `h079000a2;  // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
-  localparam       SCANLINE_WINDOW_WH=  'h0009000b;  // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
-  localparam       SCANLINE_X0Y0=       'h00050003;  // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
-  localparam       SCANLINE_STARTXY=    'h0;         // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
+//  localparam       SCANLINE_WINDOW_WH=  'h0009000b;  // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
+  localparam       SCANLINE_WINDOW_W=   'h000b;  // 176:  13-bit window width (0->'h4000)
+  localparam       SCANLINE_WINDOW_H=   'h0009;  // 9:    16-bit frame height (0->'h10000)
+//  localparam       SCANLINE_X0Y0=       'h00050003;  // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
+  localparam       SCANLINE_X0=         'h0003;  // X0=3*16=48 - 13-bit window left
+  localparam       SCANLINE_Y0=         'h0005;  // Y0=5: 16-bit window top
+//  localparam       SCANLINE_STARTXY=    'h0;         // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
+  localparam       SCANLINE_STARTX=     'h0;         // 13-bit start X (relative to window), high word (normally 0)
+  localparam       SCANLINE_STARTY=     'h0;         // 16-bit start y (normally 0)
   localparam [1:0] SCANLINE_EXTRA_PAGES= 0;          // 0..2 - number of pages in the buffer to keep/not write
   
   localparam       TEST01_START_FRAME=   1;         
   localparam       TEST01_NEXT_PAGE=     2;         
   localparam       TEST01_SUSPEND=       4;         
-//  integer ii;
+  integer ii;
+  localparam       TEST_INITIAL_BURST=   4; // 3;
 always #(CLKIN_PERIOD/2) CLK <= ~CLK;
   initial begin
 `ifdef IVERILOG              
@@ -269,6 +276,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 //    first refreshes will be fast (accummulated while waiting)
 `endif    
     enable_refresh(1);
+    axi_set_dqs_odelay('h78); //??? dafaults - wrong?
+    
 `ifdef TEST_WRITE_LEVELLING    
 // Set special values for DQS idelay for write leveling
         wait_ps_pio_done(DEFAULT_STATUS_MODE); // not no interrupt running cycle - delays are changed immediately
@@ -350,9 +359,9 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 `ifdef TEST_SCANLINE_WRITE
     write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_STARTADDR,        FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) 
     write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
-    write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_WH,        SCANLINE_WINDOW_WH);
-    write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0,      SCANLINE_X0Y0);
-    write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY,   SCANLINE_STARTXY);
+    write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_WH,        SCANLINE_WINDOW_W + (SCANLINE_WINDOW_H<<16));
+    write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0,      SCANLINE_X0+ (SCANLINE_Y0<<16));
+    write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY,   SCANLINE_STARTX+(SCANLINE_STARTY<<16));
     write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_MODE,             {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
 
     configure_channel_priority(3,0);    // lowest priority channel 1
@@ -362,12 +371,33 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
 //  localparam       TEST01_SUSPEND=       4;         
     
     write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_START_FRAME);
+    for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
+        write_block_scanline_chn(3, (ii & 3), SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+ii);  // now assumes that width is <= than maximal xfer
+    end
+//    write_block_scanline_chn(3,0, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+0);  // now assumes that width is <= than maximal xfer
+//    write_block_scanline_chn(3,1, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+1);
+//    write_block_scanline_chn(3,2, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+2);
+
+//    write_block_scanline_chn(3,3, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+3);
+//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
+//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
+//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
+//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
+// now need to repeat - test ready, then next page
+    for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin
+        if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
+            wait_status_condition (
+                MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
+                MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
+                DEFAULT_STATUS_MODE,
+                (ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
+                'hf << 16,  // mask for the 4-bit page number
+                1); // not equal to
+            write_block_scanline_chn(3, (ii & 3), SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+ii);
+        end
+        write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
+    end
     
-    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-// now need to repeat - test ready, then next page    
 `endif
   #40000;
   $finish;