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x393
Commit 511eda4b authored by Andrey Filippov's avatar Andrey Filippov
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restored saxigp 250MHz, xclk slightly not met, 0x03931017

parent f99260f2
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fpga_version.vh
View file @ 511eda4b
......@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03931016; // debugging histograms - MOD_SAXI on, restore actual histogram data
parameter FPGA_VERSION = 32'h03931017; // restoring both saxigp clocks to 150MHz (from 100 MHz)
// parameter FPGA_VERSION = 32'h03931016; // debugging histograms - MOD_SAXI on, restore actual histogram data (works, pushed to git)
// parameter FPGA_VERSION = 32'h03931015; // debugging histograms - MOD_SAXI on, fixed some bugs related to inactive cycle with page_ra == 8'hff - works?
// parameter FPGA_VERSION = 32'h03931014; // debugging histograms - MOD_SAXI on, updates sim_saxi to match hardware (wlast disables wready, smaller fifo)
// parameter FPGA_VERSION = 32'h03931013; // debugging histograms - trying to re-enable FAKE_WDATA1 top word - timer, lower - page address - OK
......
x393.v
View file @ 511eda4b
......@@ -1712,7 +1712,8 @@ assign axi_grst = axi_rst_pre;
);
// SAXIGP0 signals (read unused) (for the histograms)
wire saxi0_aclk = camsync_clk; // hclk; // 150KHz -> 100 MHz
wire saxi0_aclk = hclk; // v.03931016: camsync_clk; // hclk; // 150KHz -> 100 MHz
wire [31:0] saxi0_awaddr;
wire saxi0_awvalid;
wire saxi0_awready;
......@@ -1736,7 +1737,7 @@ assign axi_grst = axi_rst_pre;
wire [ 1:0] saxi0_bresp;
// SAXIGP1 signals (read unused) (for the event logger - has 3 spare channels for write)
wire saxi1_aclk = camsync_clk; // hclk; // 150KHz -> 100 MHz
wire saxi1_aclk = hclk; // v.03931016: camsync_clk; // hclk; // 150KHz -> 100 MHz
wire [31:0] saxi1_awaddr;
wire saxi1_awvalid;
wire saxi1_awready;
......
x393_parallel.bit
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x393_parallel.timing_summary_impl
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x393_parallel_utilization.report
View file @ 511eda4b
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Wed Mar 15 12:53:56 2023
| Date : Wed Mar 15 13:44:33 2023
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_parallel_utilization.report
| Design : x393
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 41831 | 0 | 78600 | 53.22 |
| LUT as Logic | 38434 | 0 | 78600 | 48.90 |
| LUT as Memory | 3397 | 0 | 26600 | 12.77 |
| Slice LUTs | 41903 | 0 | 78600 | 53.31 |
| LUT as Logic | 38505 | 0 | 78600 | 48.99 |
| LUT as Memory | 3398 | 0 | 26600 | 12.77 |
| LUT as Distributed RAM | 2858 | 0 | | |
| LUT as Shift Register | 539 | 0 | | |
| Slice Registers | 54280 | 0 | 157200 | 34.53 |
| Register as Flip Flop | 54280 | 0 | 157200 | 34.53 |
| LUT as Shift Register | 540 | 0 | | |
| Slice Registers | 54268 | 0 | 157200 | 34.52 |
| Register as Flip Flop | 54268 | 0 | 157200 | 34.52 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 54 | 0 | 39300 | 0.14 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
......@@ -59,7 +59,7 @@ Table of Contents
| 16 | Yes | - | Set |
| 693 | Yes | - | Reset |
| 964 | Yes | Set | - |
| 52607 | Yes | Reset | - |
| 52595 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16512 | 0 | 19650 | 84.03 |
| SLICEL | 10885 | 0 | | |
| SLICEM | 5627 | 0 | | |
| LUT as Logic | 38434 | 0 | 78600 | 48.90 |
| using O5 output only | 3 | | | |
| using O6 output only | 29881 | | | |
| using O5 and O6 | 8550 | | | |
| LUT as Memory | 3397 | 0 | 26600 | 12.77 |
| Slice | 16460 | 0 | 19650 | 83.77 |
| SLICEL | 10867 | 0 | | |
| SLICEM | 5593 | 0 | | |
| LUT as Logic | 38505 | 0 | 78600 | 48.99 |
| using O5 output only | 1 | | | |
| using O6 output only | 29918 | | | |
| using O5 and O6 | 8586 | | | |
| LUT as Memory | 3398 | 0 | 26600 | 12.77 |
| LUT as Distributed RAM | 2858 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 108 | | | |
| using O5 and O6 | 2748 | | | |
| LUT as Shift Register | 539 | 0 | | |
| using O5 output only | 256 | | | |
| using O6 output only | 233 | | | |
| using O5 and O6 | 50 | | | |
| LUT Flip Flop Pairs | 24431 | 0 | 78600 | 31.08 |
| fully used LUT-FF pairs | 4596 | | | |
| LUT-FF pairs with one unused LUT output | 17731 | | | |
| LUT-FF pairs with one unused Flip Flop | 17547 | | | |
| Unique Control Sets | 4592 | | | |
| LUT as Shift Register | 540 | 0 | | |
| using O5 output only | 266 | | | |
| using O6 output only | 225 | | | |
| using O5 and O6 | 49 | | | |
| LUT Flip Flop Pairs | 24440 | 0 | 78600 | 31.09 |
| fully used LUT-FF pairs | 4592 | | | |
| LUT-FF pairs with one unused LUT output | 17776 | | | |
| LUT-FF pairs with one unused Flip Flop | 17625 | | | |
| Unique Control Sets | 4655 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -197,12 +197,12 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52607 | Flop & Latch |
| LUT3 | 11410 | LUT |
| LUT6 | 10331 | LUT |
| LUT2 | 8166 | LUT |
| LUT4 | 7799 | LUT |
| LUT5 | 7655 | LUT |
| FDRE | 52595 | Flop & Latch |
| LUT3 | 11416 | LUT |
| LUT6 | 10351 | LUT |
| LUT2 | 8189 | LUT |
| LUT4 | 7846 | LUT |
| LUT5 | 7666 | LUT |
| RAMD32 | 4174 | Distributed Memory |
| CARRY4 | 2809 | CarryLogic |
| LUT1 | 1623 | LUT |
......
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