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x393
Commit 50c837f9 authored by Andrey Filippov's avatar Andrey Filippov
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trying synthesis

parent 9266a87c
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.project
View file @ 50c837f9
......@@ -92,7 +92,7 @@
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718203305908.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719165235946.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
......@@ -102,7 +102,7 @@
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150718203305908.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719165235946.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
......@@ -112,7 +112,7 @@
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150718203305908.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719165235946.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -132,7 +132,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150718203305908.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719165235946.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 50c837f9
......@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1
axi/cmprs_afi_mux_status.v
View file @ 50c837f9
......@@ -46,10 +46,10 @@ module cmprs_afi_mux_status #(
output reg [3:0] chunk_ptr_ra, // full pointer address - {eof,wresp,chn[1:0]}
input [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_rd // pointer data
);
reg [15:0] mode_data_mclk; // some bits unused
localparam MODE_IDTH = 15;
reg [MODE_IDTH-1:0] mode_data_mclk; // some bits unused
wire mode_we_hclk;
reg [7:0] mode_hclk;
reg [1:0] index;
reg [CMPRS_AFIMUX_CYCBITS-1:0] cntr;
reg [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_hclk; // pointer data
......@@ -67,7 +67,7 @@ module cmprs_afi_mux_status #(
assign stb_w = en && (cntr==0);
always @ (posedge mclk) begin
if (mode_we) mode_data_mclk <= cmd_data[15:0];
if (mode_we) mode_data_mclk <= cmd_data[MODE_IDTH-1:0];
end
always @ (posedge hclk) begin
......
compressor_jp/cmprs_buf_average.v
View file @ 50c837f9
......@@ -110,7 +110,8 @@ module cmprs_buf_average#(
wire [1:0] pre_accCdone; // need to make sure that pre_accCdone do_r not happen with pre_accYdone
reg [3:0] accYrun;
reg [1:0] accCrun;
reg [3:0] accYdone; // only bit 0 is used as a start of output
// reg [3:0] accYdone; // only bit 0 is used as a start of output
reg accYdone; // only bit 0 is used as a start of output
reg accYdoneAny;
reg [1:0] avrY_wa, pre_avrY_wa;
reg avrC_wa, pre_avrC_wa;
......@@ -199,7 +200,8 @@ module cmprs_buf_average#(
accYrun[3:0] <= {4{frame_en}} & ((accYfirst[3:0] & accYen[3:0]) | (accYrun[3:0] & ~pre_accYdone[3:0]));
accCrun[1:0] <= {2{frame_en}} & ((accCfirst[1:0] & accCen[1:0]) | (accCrun[1:0] & ~pre_accCdone[1:0]));
accYdone[3:0] <= pre_accYdone[3:0] & accYrun[3:0];
// accYdone[3:0] <= pre_accYdone[3:0] & accYrun[3:0];
accYdone <= pre_accYdone[0] & accYrun[0];
accYdoneAny <= |(pre_accYdone[3:0] & accYrun[3:0]);
avr_we <= |(pre_accYdone[3:0] & accYrun[3:0]) || |(pre_accCdone[1:0] & accCrun[1:0]);
......@@ -284,11 +286,11 @@ module cmprs_buf_average#(
case (converter_type_r)
CMPRS_COLOR18: ccv_out_start <= (yaddrw[7:0]==8'hc4); //TODO: adjust to minimal latency?
CMPRS_COLOR20: ccv_out_start <= (yaddrw[7:0]==8'hc4); //TODO: adjust to minimal latency?
CMPRS_MONO16: ccv_out_start <= accYdone[0];
CMPRS_JP4: ccv_out_start <= accYdone[0];
CMPRS_JP4DIFF: ccv_out_start <= accYdone[0];
CMPRS_MONO8: ccv_out_start <= accYdone[0];
default: ccv_out_start <= accYdone[0];
CMPRS_MONO16: ccv_out_start <= accYdone; //[0];
CMPRS_JP4: ccv_out_start <= accYdone; //[0];
CMPRS_JP4DIFF: ccv_out_start <= accYdone; //[0];
CMPRS_MONO8: ccv_out_start <= accYdone; //[0];
default: ccv_out_start <= accYdone; //[0];
endcase
end
......
compressor_jp/cmprs_cmd_decode.v
View file @ 50c837f9
......@@ -305,7 +305,7 @@ module cmprs_cmd_decode#(
always @ (posedge xclk) begin
if (format_we_xclk) format_xclk <= format_mclk;
if (color_sat_we_xclk) color_sat_xclk <= color_sat_mclk;
if (color_sat_we_xclk) color_sat_xclk <= color_sat_mclk; // SuppressThisWarning VivadoSynthesis
if (coring_we_xclk) coring_xclk <= coring_mclk;
end
......
compressor_jp/cmprs_macroblock_buf_iface.v
View file @ 50c837f9
......@@ -85,7 +85,8 @@ module cmprs_macroblock_buf_iface #(
reg [ 2:0] next_valid; // number of next valid page (only 2 LSB are actual page number)
reg [ 2:0] next_invalid; // oldest valid page
reg [ 1:0] add_invalid; // advance next_invalid pointer by this value, send next_page pulses
reg [ 2:0] used_pages; // number of pages simultaneously used for the last macroblock
// reg [ 2:0] used_pages; // number of pages simultaneously used for the last macroblock
reg [ 1:0] used_pages; // number of pages simultaneously used for the last macroblock - [2] was never used
reg [ 2:0] needed_page; // calculate at MB start
reg pre_first_mb; // from frame start to mb_pre_start[2]
// reg first_mb; // from mb_pre_start[2] to mb_pre_start[1]
......@@ -183,7 +184,8 @@ module cmprs_macroblock_buf_iface #(
pre_advance_tiles[1:0] <= {1'b0, mbl_x_inc_r[7]};
end
endcase
used_pages <= needed_page - next_invalid +1;
// used_pages <= needed_page - next_invalid +1;
used_pages <= needed_page[1:0] - next_invalid[1:0] +1; // nit [2] not used
end
if (mb_pre_start[7]) begin // TODO: apply after delay, regardless last or not
if (mb_last_in_row) add_invalid <= used_pages[1:0];
......
compressor_jp/csconvert.v
View file @ 50c837f9
......@@ -268,6 +268,18 @@ module csconvert#(
// pre_color_enable <= 1'b0;
// ccv_out_start <= accYdone[0];
end
default:begin //color 18 (or try 'X'
pre_first_out <= 'bx; // conv18_pre_first_out;
signed_y[8:0] <= 'bx; // {conv18_signed_y[7],conv18_signed_y[7:0]};
ywe <= 'bx; //conv18_ywe;
yaddrw[7:0] <= 'bx; //{conv18_yaddrw[7],conv18_yaddrw[3],conv18_yaddrw[6:4],conv18_yaddrw[2:0]};
signed_c[8:0] <= 'bx; //{conv18_signed_c[8:0]};
cwe <= 'bx; //conv18_cwe;
caddrw[7:0] <= 'bx; //{1'b0,conv18_caddrw[6:0]};
n000 <= 'bx; //conv18_n000;
n255 <= 'bx; //conv18_n255;
end
endcase
......
compressor_jp/csconvert18a.v
View file @ 50c837f9
......@@ -380,13 +380,13 @@ module csconvert18a(
// second term is pa1, third - (pd0+pd2)/2
// else
// second term is (pa1 + (pd0+pd2)/2)/2, third - (pa0+pa2)/2
reg [7:0] m1;
// reg [7:0] m1; same as pd1_dly
reg [7:0] m2;
reg [7:0] m3;
wire [8:0] pd02s= {1'b0,pd_prev[7:0]}+{1'b0,pd_next[7:0]}; // will use pd02s[8:1]
wire [8:0] pa1pd02s={1'b0,pa1[7:0]}+{1'b0,pd02s[8:1]}; // will use pa1pd02s[8:1]
wire [8:0] pa02s= {1'b0,pa_prev[7:0]}+{1'b0,pa_next[7:0]}; // will use pa02s[8:1]
always @ (posedge CLK) m1 <= pd1[7:0];
// always @ (posedge CLK) m1 <= pd1[7:0]; // same as pd1_dly
// always @ (posedge CLK) m2 <= (odd_pix==odd_line)? pa1[7:0] : pa1pd02s[8:1];
// always @ (posedge CLK) m3 <= (odd_pix==odd_line)? pd02s[8:1] : pa02s[8:1];
always @ (posedge CLK) m2 <= pix_green? pa1[7:0] : pa1pd02s[8:1];
......@@ -526,16 +526,17 @@ Y[1,1]=(0x96*P[1,1]+ 0x1d*((P[1,0]+P[1,2])/2 + 0x4d*((P[0,1] +
end
endcase
wire [15:0] mm1=m1[7:0]*k1[7:0];
wire [15:0] mm1=pd1_dly[7:0] * k1[7:0]; //m1[7:0]*k1[7:0];
wire [15:0] mm2=m2[7:0]*k2[7:0];
wire [15:0] mm3=m3[7:0]*k3[7:0];
reg [7:0] y;
reg [7:0] y0; // bypass in monochrome mode
// reg [7:0] y0; // bypass in monochrome mode
wire [7:0] y0 = pdc;
// wire [7:0] y0; // bypass in monochrome mode
reg [15:0] y1,y2,y3;
wire [15:0] y_sum =y1+y2+y3;
always @ (posedge CLK) y0 <= m1;
// always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent
always @ (posedge CLK) y1 <= mm1;
always @ (posedge CLK) y2 <= mm2;
always @ (posedge CLK) y3 <= mm3;
......
compressor_jp/focus_sharp393.v
View file @ 50c837f9
......@@ -85,7 +85,8 @@ module focus_sharp393(
reg [11:0] di_d;
reg [11:0] d1;
reg [8:0] start2;
reg [7:0] finish2;
// reg [7:0] finish2;
reg [6:0] finish2; // bit[7] never used
reg [5:0] use_k_dly;
reg [23:0] acc_blk; // accumulator for the sum ((a[i]*d[i])^2)
reg [22:0] sum_blk; // accumulator for the sum ((a[i]*d[i])^2), copied at block end
......@@ -141,6 +142,7 @@ module focus_sharp393(
3'h4: wnd_totalwidth[8:1] <= wnd_reg[11:4] ;
3'h5: filt_sel0[3:0] <= wnd_reg[3:0] ;
3'h6: stren <= wnd_reg[0] ;
default: begin end
endcase
end
end
......@@ -193,10 +195,12 @@ module focus_sharp393(
filt_sel[3:0] <= filt_sel0[3:0];
if (clksync[2]) d1[11:0]<=di_d[11:0];
start2[8:0] <= {start2[7:0], start && csync};
finish2[7:0]<= {finish2[6:0],use_coef && !next_ac};
// finish2[7:0]<= {finish2[6:0],use_coef && !next_ac};
finish2[6:0]<= {finish2[5:0],use_coef && !next_ac}; // finish2[7] was never used
if (!en || start2[0]) tba[5:0] <= 6'h0;
else if (!csync && (tba[5:0] != 6'h3f)) tba[5:0] <= tba[5:0] + 1;
mult_s[17:0] <= (&mult_p[35:31] || !(&mult_p[35:31]))?mult_p[31:14]:18'h1ffff;
// mult_s[17:0] <= (&mult_p[35:31] || !(&mult_p[35:31]))?mult_p[31:14]:18'h1ffff;
mult_s[17:0] <= (&mult_p[35:31] || !(|mult_p[35:31]))?mult_p[31:14]:18'h1ffff;
next_ac <= en && (start2[3] || (next_ac && ((tba[5:0] != 6'h3f) || csync )));
use_coef <= next_ac && !csync;
use_k_dly[5:0] <= {use_k_dly[4:0],use_coef};
......
includes/x393_parameters.vh
View file @ 50c837f9
......@@ -650,18 +650,18 @@
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
parameter CLKIN_PERIOD_XCLK = 20, // 24MHz
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 50, // 1000 MHz
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
parameter CLKIN_PERIOD_SYNC = 20, // 24MHz
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 50, // 1000 MHz
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
parameter BUF_CLK1X_SYNC = "BUFG",
......
sensor/sens_sync.v
View file @ 50c837f9
......@@ -36,7 +36,7 @@ module sens_sync#(
input rst, // global reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input mclk, // global system clock, synchronizes commands
input en, // enable channel (0 resets counters)
input en, // @pclk enable channel (0 resets counters)
input sof_in, // @pclk start of frame input, single-cycle
input eof_in, // @pclk end of frame input, single-cycle (to limit sof_late
input hact, // @pclk (use to count lines for delayed pulse)
......
sensor/sensor_channel.v
View file @ 50c837f9
......@@ -51,10 +51,11 @@ module sensor_channel#(
parameter SENSOR_CTRL_RADDR = 0, //'h00
parameter SENSOR_CTRL_ADDR_MASK = 'h7ff, //
// bits of the SENSOR mode register
parameter SENSOR_MODE_WIDTH = 9,
parameter SENSOR_HIST_EN_BIT = 0, // 0..3 1 - enable histogram modules, disable after processing the started frame
parameter SENSOR_HIST_NRST_BIT = 4, // 0 - immediately reset all histogram modules
parameter SENSOR_16BIT_BIT = 8, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
parameter SENSOR_MODE_WIDTH = 10,
parameter SENSOR_HIST_EN_BIT = 4, // 0..3 1 - enable histogram modules, disable after processing the started frame
parameter SENSOR_HIST_NRST_BIT = 8, // 0 - immediately reset all histogram modules
parameter SENSOR_CHN_EN_BIT = 8, // 1 - this enable channel
parameter SENSOR_16BIT_BIT = 9, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
parameter SENSI2C_CTRL_RADDR = 2, // 'h02..'h03
parameter SENSI2C_CTRL_MASK = 'h7fe,
......@@ -256,6 +257,8 @@ module sensor_channel#(
wire sensor_ctrl_we;
reg [SENSOR_MODE_WIDTH-1:0] mode;
wire [3:0] hist_en;
wire en_mclk; // enable this channel
wire en_pclk; // enabole in pclk domain
wire hist_nrst;
wire bit16; // 16-bit mode, 0 - 8 bit mode
wire [3:0] hist_rq;
......@@ -291,6 +294,7 @@ module sensor_channel#(
assign dav_w = bit16 ? gamma_hact_in : dav_8bit;
assign last_in_line = ! ( bit16 ? gamma_hact_in : gamma_hact_out);
assign en_mclk = mode[SENSOR_CHN_EN_BIT];
assign hist_en = mode[SENSOR_HIST_EN_BIT+:4];
assign hist_nrst = mode[SENSOR_HIST_NRST_BIT];
assign bit16 = mode[SENSOR_16BIT_BIT];
......@@ -303,7 +307,7 @@ module sensor_channel#(
always @ (posedge rst or posedge mclk) begin
if (rst) mode <= 0;
else if (sensor_ctrl_we) mode <= sensor_ctrl_data[8:0];
else if (sensor_ctrl_we) mode <= sensor_ctrl_data[SENSOR_MODE_WIDTH-1:0];
end
always @ (posedge pclk) begin
......@@ -319,6 +323,8 @@ module sensor_channel#(
eof_out_r <= bit16 ? gamma_eof_in : gamma_eof_out;
end
level_cross_clocks level_cross_clocks_en_pclk_i (.clk(pclk), .d_in(en_mclk), .d_out(en_pclk));
status_router2 status_router2_sensor_i (
.rst (rst), // input
.clk (mclk), // input
......@@ -475,7 +481,7 @@ module sensor_channel#(
.rst (rst), // input
.pclk (pclk), // input
.mclk (mclk), // input
.en(), // input
.en (en_pclk), // input @pclk
.sof_in (sof), // input
.eof_in (eof), // input
.hact (hact), // input
......@@ -489,9 +495,6 @@ module sensor_channel#(
.cmd_stb (cmd_stb) // input
);
sens_gamma #(
.SENS_GAMMA_NUM_CHN (SENS_GAMMA_NUM_CHN),
.SENS_GAMMA_BUFFER (SENS_GAMMA_BUFFER),
......
util_modules/clocks393.v
View file @ 50c837f9
......@@ -42,18 +42,18 @@ module clocks393#(
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
parameter CLKIN_PERIOD_XCLK = 20, // 24MHz
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 50, // 1000 MHz
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
parameter CLKIN_PERIOD_SYNC = 20, // 24MHz
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 50, // 1000 MHz
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
parameter BUF_CLK1X_SYNC = "BUFG",
......
util_modules/cmd_frame_sequencer.v
View file @ 50c837f9
......@@ -92,7 +92,7 @@ module cmd_frame_sequencer#(
reg we_fifo_wp; // enable writing to fifo write pointer memory
reg next_frame_rq; // request to switch to the new frame page, clear pointer for the one just left
wire pre_wpage_inc;
reg [PNTR_WIDH-1:0] fifo_wr_pointers_ram [0:7];
reg [PNTR_WIDH-1:0] fifo_wr_pointers_ram [0:15];
wire [PNTR_WIDH-1:0] fifo_wr_pointers_outw=fifo_wr_pointers_ram[wpage_w];
wire [PNTR_WIDH-1:0] fifo_wr_pointers_outr=fifo_wr_pointers_ram[page_r];
......
x393_timing.xdc
View file @ 50c837f9
......@@ -69,16 +69,15 @@ create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre ]
create_generated_clock -name mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
####create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
####create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
####create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
####create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
####create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
####set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
####set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
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