Commit 50c837f9 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

trying synthesis

parent 9266a87c

.project

+4 −4
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ 
		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718203305908.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719165235946.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -102,7 +102,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150718203305908.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719165235946.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -112,7 +112,7 @@ 
		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150718203305908.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719165235946.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -132,7 +132,7 @@ 
		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150718203305908.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719165235946.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+1 −1
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@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none 
VivadoSynthesis_127_verbose=true

VivadoSynthesis_81_parser_mode=1

VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->

VivadoSynthesis_95_ShowInfo=false

VivadoSynthesis_95_ShowInfo=true

com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->

eclipse.preferences.version=1

axi/cmprs_afi_mux_status.v

+6 −6
Original line number Diff line number Diff line
@@ -46,10 +46,10 @@ module cmprs_afi_mux_status #( 
    output reg               [3:0] chunk_ptr_ra, // full pointer address - {eof,wresp,chn[1:0]}

    input [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_rd  // pointer data

);

    reg [15:0] mode_data_mclk; // some bits unused

   localparam MODE_IDTH = 15;

    reg              [MODE_IDTH-1:0] mode_data_mclk; // some bits unused

    wire                             mode_we_hclk;

    reg                        [7:0] mode_hclk;



    reg                        [1:0] index;

    reg   [CMPRS_AFIMUX_CYCBITS-1:0] cntr;

    reg     [CMPRS_AFIMUX_WIDTH-1:0] chunk_ptr_hclk;  // pointer data
@@ -67,7 +67,7 @@ module cmprs_afi_mux_status #( 
    

    assign stb_w = en && (cntr==0);

    always @ (posedge mclk) begin

        if (mode_we) mode_data_mclk <= cmd_data[15:0];

        if (mode_we) mode_data_mclk <= cmd_data[MODE_IDTH-1:0];

    end



    always @ (posedge hclk) begin

compressor_jp/cmprs_buf_average.v

+9 −7
Original line number Diff line number Diff line
@@ -110,7 +110,8 @@ module cmprs_buf_average#( 
    wire [1:0] pre_accCdone; // need to make sure that pre_accCdone do_r not happen with pre_accYdone

    reg  [3:0] accYrun;

    reg  [1:0] accCrun;

    reg  [3:0] accYdone; // only bit 0 is used as a start of output

//    reg  [3:0] accYdone; // only bit 0 is used as a start of output

    reg        accYdone; // only bit 0 is used as a start of output

    reg        accYdoneAny;

    reg  [1:0] avrY_wa, pre_avrY_wa;

    reg        avrC_wa, pre_avrC_wa;
@@ -199,7 +200,8 @@ module cmprs_buf_average#( 
        accYrun[3:0] <= {4{frame_en}} & ((accYfirst[3:0] & accYen[3:0]) | (accYrun[3:0] & ~pre_accYdone[3:0]));

        accCrun[1:0] <= {2{frame_en}} & ((accCfirst[1:0] & accCen[1:0]) | (accCrun[1:0] & ~pre_accCdone[1:0]));

        

        accYdone[3:0] <=  pre_accYdone[3:0] & accYrun[3:0];

//        accYdone[3:0] <=  pre_accYdone[3:0] & accYrun[3:0];

        accYdone      <=  pre_accYdone[0] & accYrun[0];

        accYdoneAny   <=  |(pre_accYdone[3:0] & accYrun[3:0]);

        avr_we        <=  |(pre_accYdone[3:0] & accYrun[3:0]) || |(pre_accCdone[1:0] & accCrun[1:0]);
@@ -284,11 +286,11 @@ module cmprs_buf_average#( 
        case (converter_type_r)

            CMPRS_COLOR18: ccv_out_start <= (yaddrw[7:0]==8'hc4); //TODO: adjust to minimal latency?

            CMPRS_COLOR20: ccv_out_start <= (yaddrw[7:0]==8'hc4); //TODO: adjust to minimal latency?

            CMPRS_MONO16:  ccv_out_start    <=  accYdone[0];

            CMPRS_JP4:     ccv_out_start    <=  accYdone[0];

            CMPRS_JP4DIFF: ccv_out_start    <=  accYdone[0];

            CMPRS_MONO8:   ccv_out_start    <=  accYdone[0];

            default:       ccv_out_start    <=  accYdone[0];

            CMPRS_MONO16:  ccv_out_start    <=  accYdone; //[0];

            CMPRS_JP4:     ccv_out_start    <=  accYdone; //[0];

            CMPRS_JP4DIFF: ccv_out_start    <=  accYdone; //[0];

            CMPRS_MONO8:   ccv_out_start    <=  accYdone; //[0];

            default:       ccv_out_start    <=  accYdone; //[0];

        endcase

    end

compressor_jp/cmprs_cmd_decode.v

+1 −1
Original line number Diff line number Diff line
@@ -305,7 +305,7 @@ module cmprs_cmd_decode#( 
    

    always @ (posedge xclk) begin

         if (format_we_xclk)    format_xclk <=    format_mclk;

         if (color_sat_we_xclk) color_sat_xclk <= color_sat_mclk;

         if (color_sat_we_xclk) color_sat_xclk <= color_sat_mclk; // SuppressThisWarning VivadoSynthesis

         if (coring_we_xclk)    coring_xclk <=    coring_mclk;

    end