Commit 4e2a8fce authored by Andrey Filippov's avatar Andrey Filippov

reduced debug verbosity

parent 75ff14dd
...@@ -186,7 +186,7 @@ class X393Mem(object): ...@@ -186,7 +186,7 @@ class X393Mem(object):
packedData=struct.pack(self.ENDIAN+"L",data) packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0] d=struct.unpack(self.ENDIAN+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData mm[page_offs:page_offs+4]=packedData
if quiet <2: if quiet < 1:
print ("0x%08x <== 0x%08x (%d)"%(addr,d,d)) print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
def read_mem (self,addr,quiet=1): def read_mem (self,addr,quiet=1):
......
...@@ -353,7 +353,7 @@ class X393Sensor(object): ...@@ -353,7 +353,7 @@ class X393Sensor(object):
@param verbose - verbose level @param verbose - verbose level
@return combined table data word. @return combined table data word.
""" """
if verbose>0: if verbose>1:
print ("func_sensor_i2c_table_reg_wr(): slave_addr= ",slave_addr,", rah=",rah,", num_bytes = ",num_bytes,", bit_delay = ",bit_delay) print ("func_sensor_i2c_table_reg_wr(): slave_addr= ",slave_addr,", rah=",rah,", num_bytes = ",num_bytes,", bit_delay = ",bit_delay)
rslt = 0 rslt = 0
rslt |= (slave_addr & ((1 << vrlg.SENSI2C_TBL_SA_BITS) - 1)) << vrlg.SENSI2C_TBL_SA rslt |= (slave_addr & ((1 << vrlg.SENSI2C_TBL_SA_BITS) - 1)) << vrlg.SENSI2C_TBL_SA
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment