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x393
Commit 4bb4f227 authored by Andrey Filippov's avatar Andrey Filippov
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channels/compressor synchronization

parent 51d9d5ad
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cocotb/x393_cocotb_02.sav
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compressor_jp/cmprs_frame_sync.v
View file @ 4bb4f227
...@@ -76,6 +76,7 @@ module cmprs_frame_sync#( ...@@ -76,6 +76,7 @@ module cmprs_frame_sync#(
input [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line in this (compressor) channel input [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges) in this (compressor channel input [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges) in this (compressor channel
input frames_in_sync, // frame number in destination memory channel is valid for bonded mode
input frame_done, // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input frame_done, // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
output reg suspend, // suspend reading data for this channel - waiting for the source data output reg suspend, // suspend reading data for this channel - waiting for the source data
...@@ -91,11 +92,15 @@ module cmprs_frame_sync#( ...@@ -91,11 +92,15 @@ module cmprs_frame_sync#(
a) "broken frame" - attempted to start a new frame before previous one was completely read from the memory a) "broken frame" - attempted to start a new frame before previous one was completely read from the memory
b) turned off enable while frame was being compressed b) turned off enable while frame was being compressed
Abort frame lasts until flush end or timeout expire Abort frame lasts until flush end or timeout expire
TODO: Simplify logic: instead of frame_start_pend_r - copy frame_number_srtc @ vsync_late, and start frame if it is not reading,
in "run" mode, and frame_number_differ (in multi-frame mode)
*/ */
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late // wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
// wire frame_started_mclk; // wire frame_started_mclk;
reg bonded_mode; reg bonded_mode;
reg [3:0] frame_start_dst_r; reg [5:0] frame_start_dst_r;
reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late
reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_* reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_*
reg frames_numbers_differ; // src and dest point to different frames (multi-frame buffer mode), disregard line_unfinished_* reg frames_numbers_differ; // src and dest point to different frames (multi-frame buffer mode), disregard line_unfinished_*
...@@ -108,7 +113,7 @@ module cmprs_frame_sync#( ...@@ -108,7 +113,7 @@ module cmprs_frame_sync#(
reg [CMPRS_TIMEOUT_BITS-1:0] timeout; reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
reg cmprs_en_extend_r=0; reg cmprs_en_extend_r=0;
reg cmprs_en_d; reg cmprs_en_d;
reg suspend_end; // suspend at teh end of the current frame until frame number changes reg suspend_end; // suspend at the end of the current frame until frame number changes
// reg cmprs_en_xclk; // reg cmprs_en_xclk;
assign frame_start_dst = frame_start_dst_r[0]; assign frame_start_dst = frame_start_dst_r[0];
assign cmprs_en_extend = cmprs_en_extend_r; assign cmprs_en_extend = cmprs_en_extend_r;
...@@ -146,19 +151,25 @@ module cmprs_frame_sync#( ...@@ -146,19 +151,25 @@ module cmprs_frame_sync#(
if (!cmprs_en || frame_done ) reading_frame_r <= 0; if (!cmprs_en || frame_done ) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1; else if (frame_started_mclk) reading_frame_r <= 1;
if (!cmprs_en) frame_start_pend_r <= 0; // if (!cmprs_en || frame_start_dst_r[0]) frame_start_pend_r <= 0;
else if (cmprs_run && vsync_late && reading_frame_r) frame_start_pend_r <= 1; if (!cmprs_run || frame_start_dst_r[0]) frame_start_pend_r <= 0;
else if (frame_start_dst_r[0]) frame_start_pend_r <= 0; // else if (cmprs_run && vsync_late && reading_frame_r) frame_start_pend_r <= 1;
else if ((cmprs_run && vsync_late && reading_frame_r) ||
if (!cmprs_en) suspend_end <= 0; (frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1;
// else if (frame_start_dst_r[0]) frame_start_pend_r <= 0;
// If started frame differs from tghe source one, needs to comrfess next frame after this is done, without vsync_late
// else if (frame_start_dst_r[5] ) frame_start_pend_r <= bonded_mode && frames_numbers_differ;
// if (!cmprs_en) suspend_end <= 0;
if (!cmprs_run) suspend_end <= 0;
else if (frame_done) suspend_end <= 1; else if (frame_done) suspend_end <= 1;
else if (frame_start_dst_r[3]) suspend_end <= 0; else if (frame_start_dst_r[3]) suspend_end <= 0;
frame_start_dst_r[0] <= cmprs_en && (cmprs_run ? frame_start_dst_r[0] <= cmprs_en && (cmprs_run ?
((vsync_late && !reading_frame_r) || (frame_start_pend_r && frame_done)): ((vsync_late && !reading_frame_r) || (frame_start_pend_r && frame_done)):
cmprs_standalone); cmprs_standalone);
if (!cmprs_en) frame_start_dst_r[3:1] <=0; if (!cmprs_en) frame_start_dst_r[5:1] <=0;
else frame_start_dst_r[3:1] <= frame_start_dst_r[2:0]; else frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];
if (!cmprs_en) bonded_mode <= 0; if (!cmprs_en) bonded_mode <= 0;
else if (cmprs_run) bonded_mode <= 1; else if (cmprs_run) bonded_mode <= 1;
...@@ -171,8 +182,7 @@ module cmprs_frame_sync#( ...@@ -171,8 +182,7 @@ module cmprs_frame_sync#(
line_numbers_sync <= (line_unfinished_src > line_unfinished); line_numbers_sync <= (line_unfinished_src > line_unfinished);
suspend <= bonded_mode && !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync); suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync));
end end
......
compressor_jp/cmprs_macroblock_buf_iface.v
View file @ 4bb4f227
...@@ -42,11 +42,12 @@ ...@@ -42,11 +42,12 @@
module cmprs_macroblock_buf_iface #( module cmprs_macroblock_buf_iface #(
`ifdef USE_OLD_DCT `ifdef USE_OLD_DCT
parameter DCT_PIPELINE_PAUSE = 0 // No need to delay parameter DCT_PIPELINE_PAUSE = 0, // No need to delay
`else `else
parameter DCT_PIPELINE_PAUSE = 48 // TODO: find really required value (minimal), adjust counter bits (now 6) parameter DCT_PIPELINE_PAUSE = 48, // TODO: find really required value (minimal), adjust counter bits (now 6)
// 48 seems to be OK (may be less) // 48 seems to be OK (may be less)
`endif `endif
parameter FRAME_QUEUE_WIDTH = 2
)( )(
// input rst, // input rst,
input xclk, // global clock input, compressor single clock rate input xclk, // global clock input, compressor single clock rate
...@@ -64,6 +65,7 @@ module cmprs_macroblock_buf_iface #( ...@@ -64,6 +65,7 @@ module cmprs_macroblock_buf_iface #(
input frame_start_xclk, // frame parameters are valid after this pulse input frame_start_xclk, // frame parameters are valid after this pulse
input frame_go, // start frame: if idle, will start reading data (if available), input frame_go, // start frame: if idle, will start reading data (if available),
// if running - will not restart a new frame if 0. // if running - will not restart a new frame if 0.
input cmprs_run_mclk, // 0 - off or stopping, reset frame_pre_run
input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile) input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
input [12:0] n_blocks_in_row_m1, // number of macroblocks in a macroblock row minus 1 input [12:0] n_blocks_in_row_m1, // number of macroblocks in a macroblock row minus 1
input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1 input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
...@@ -125,10 +127,22 @@ module cmprs_macroblock_buf_iface #( ...@@ -125,10 +127,22 @@ module cmprs_macroblock_buf_iface #(
reg frame_pre_run; reg frame_pre_run;
// reg [1:0] frame_may_start; // reg [1:0] frame_may_start;
reg frame_start_xclk_r; // next cycle after frame_start_xclk reg frame_start_xclk_r; // next cycle after frame_start_xclk
reg cmprs_run_xclk;
reg [5:0] dct_pipeline_delay_cntr; reg [5:0] dct_pipeline_delay_cntr;
reg [FRAME_QUEUE_WIDTH:0] frame_que_cntr; // width+1
reg [1:0] frame_finish_r; // active after last macroblock in a frame
wire mb_done_w;
wire frame_finish_w;
wire frames_pending;
// assign mb_done = mb_pre_start[1] && last_mb; // mb_pre_end_in && last_mb;
assign mb_done_w = mb_pre_start[1] && last_mb; // mb_pre_end_in && last_mb;
// assign mb_done_w = first_mb && (dct_pipeline_delay_cntr == 1);
assign frame_finish_w = frame_finish_r[1] && !frame_finish_r[0];
assign frames_pending = !frame_que_cntr[FRAME_QUEUE_WIDTH] && (|frame_que_cntr[FRAME_QUEUE_WIDTH-1:0]);
`ifdef DEBUG_RING `ifdef DEBUG_RING
assign dbg_add_invalid = add_invalid; assign dbg_add_invalid = add_invalid;
assign dbg_mb_release_buf = mb_release_buf; assign dbg_mb_release_buf = mb_release_buf;
...@@ -150,8 +164,11 @@ module cmprs_macroblock_buf_iface #( ...@@ -150,8 +164,11 @@ module cmprs_macroblock_buf_iface #(
((frame_may_start==2'b1) && !frame_pre_run && !starting); ((frame_may_start==2'b1) && !frame_pre_run && !starting);
assign frame_pre_start_w = frame_may_start[0] && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_may_start[1] && !starting)); assign frame_pre_start_w = frame_may_start[0] && ((mb_pre_end_in && last_mb) || (!frame_pre_run && !frame_may_start[1] && !starting));
*/ */
// one extra at the end of frame is needed (sequence will be short)
assign mb_pre_start_w = mb_pre_end_in || (frame_start_xclk_r && !frame_pre_run && !starting); assign mb_pre_start_w = mb_pre_end_in || (frame_start_xclk_r && !frame_pre_run && !starting);
assign frame_pre_start_w = (mb_pre_end_in && last_mb) || (frame_start_xclk_r && !frame_pre_run && !starting); // assign frame_pre_start_w = (mb_pre_end_in && last_mb) || (frame_start_xclk_r && !frame_pre_run && !starting);
assign frame_pre_start_w = (frames_pending && frame_finish_w) || (frame_start_xclk_r && !frame_pre_run && !starting);
//frame_start_xclk_r //frame_start_xclk_r
assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock
always @ (posedge xclk) begin always @ (posedge xclk) begin
...@@ -173,10 +190,11 @@ module cmprs_macroblock_buf_iface #( ...@@ -173,10 +190,11 @@ module cmprs_macroblock_buf_iface #(
else if (frame_pre_start_r) mb_first_in_row <= 1; else if (frame_pre_start_r) mb_first_in_row <= 1;
else if (mb_pre_start[0]) mb_first_in_row <= mb_last_in_row; else if (mb_pre_start[0]) mb_first_in_row <= mb_last_in_row;
cmprs_run_xclk <=cmprs_run_mclk;
if (!frame_en) frame_pre_run <= 0; if (!frame_en || (!frames_pending && frame_finish_w)) frame_pre_run <= 0;
else if (mb_pre_start_w) frame_pre_run <= 1; else if (mb_pre_start_w) frame_pre_run <= 1;
else if (mb_pre_end_in && last_mb) frame_pre_run <= 0; // else if (mb_pre_end_in && last_mb) frame_pre_run <= 0;
if (frame_pre_start_r) mb_rows_left <= n_block_rows_m1; if (frame_pre_start_r) mb_rows_left <= n_block_rows_m1;
else if (mb_pre_start[0] && mb_last_in_row) mb_rows_left <= mb_rows_left - 1; else if (mb_pre_start[0] && mb_last_in_row) mb_rows_left <= mb_rows_left - 1;
...@@ -184,9 +202,11 @@ module cmprs_macroblock_buf_iface #( ...@@ -184,9 +202,11 @@ module cmprs_macroblock_buf_iface #(
if (frame_pre_start_r || (mb_pre_start[0] && mb_last_in_row)) mb_cols_left <= n_blocks_in_row_m1; if (frame_pre_start_r || (mb_pre_start[0] && mb_last_in_row)) mb_cols_left <= n_blocks_in_row_m1;
else if (mb_pre_start[0]) mb_cols_left <= mb_cols_left - 1; else if (mb_pre_start[0]) mb_cols_left <= mb_cols_left - 1;
if (mb_pre_start[1]) mb_last_row <= (mb_rows_left == 0); if (frame_pre_start_r) mb_last_row <= 0;
else if (mb_pre_start[1]) mb_last_row <= (mb_rows_left == 0);
if (mb_pre_start[1]) mb_last_in_row <= (mb_cols_left == 0); if (frame_pre_start_r) mb_last_in_row <= 0;
else if (mb_pre_start[1]) mb_last_in_row <= (mb_cols_left == 0);
if (!frame_en || mb_pre_start[1]) pre_first_mb <= 0; if (!frame_en || mb_pre_start[1]) pre_first_mb <= 0;
else if (frame_pre_start_r) pre_first_mb <= 1; else if (frame_pre_start_r) pre_first_mb <= 1;
...@@ -203,18 +223,35 @@ module cmprs_macroblock_buf_iface #( ...@@ -203,18 +223,35 @@ module cmprs_macroblock_buf_iface #(
// TODO: Here enforce minimal pause (if not zero for the DCT pipeline to recover // TODO: Here enforce minimal pause (if not zero for the DCT pipeline to recover
// will wait for buf_ready_w, but not less than DCT_PIPELINE_PAUSE (or no wait at all) // will wait for buf_ready_w, but not less than DCT_PIPELINE_PAUSE (or no wait at all)
mb_pre_start4_first <=mb_pre_start[3]; mb_pre_start4_first <=mb_pre_start[3];
if (!frame_en) frame_finish_r[0] <= 0;
else if (mb_done_w) frame_finish_r[0] <= 1;
else if (dct_pipeline_delay_cntr == 0) frame_finish_r[0] <= 0;
frame_finish_r[1] <= frame_finish_r[0];
if (xrst) dct_pipeline_delay_cntr <= 0; if (xrst) dct_pipeline_delay_cntr <= 0;
else if (mb_pre_start4_first && !buf_ready_w) dct_pipeline_delay_cntr <= DCT_PIPELINE_PAUSE -1; else if ((mb_pre_start4_first && !buf_ready_w) ||
mb_done_w) dct_pipeline_delay_cntr <= DCT_PIPELINE_PAUSE -1;
else if (|dct_pipeline_delay_cntr) dct_pipeline_delay_cntr <= dct_pipeline_delay_cntr -1; else if (|dct_pipeline_delay_cntr) dct_pipeline_delay_cntr <= dct_pipeline_delay_cntr -1;
if (!frame_en_r) mb_pre_start <= 0; // if (!frame_en_r) mb_pre_start <= 0;
if (mb_pre_start_w) mb_pre_start <= 1; // if (!frame_en_r || (mb_pre_start[1] && last_mb)) mb_pre_start <= 0;
if (!frame_en_r || (mb_pre_start[3] && frame_finish_r[0])) mb_pre_start <= 0; // so needed page is updated
else if (mb_pre_start_w) mb_pre_start <= 1;
// if (mb_pre_start_w && ! last_mb) mb_pre_start <= 1;
else if (!mb_pre_start[4] || (buf_ready_w && !(|dct_pipeline_delay_cntr))) mb_pre_start <= mb_pre_start << 1; else if (!mb_pre_start[4] || (buf_ready_w && !(|dct_pipeline_delay_cntr))) mb_pre_start <= mb_pre_start << 1;
if (!cmprs_run_xclk) frame_que_cntr <= 0;
else if ( frame_start_xclk_r && !frame_pre_start_r) frame_que_cntr <= frame_que_cntr + 1;
else if (!frame_start_xclk_r && frame_pre_start_r) frame_que_cntr <= frame_que_cntr - 1;
if (mb_pre_start[1]) mbl_x_r[6:3] <= mb_first_in_row? {2'b0,left_marg[4:3]} : mbl_x_next_r[6:3]; if (mb_pre_start[1]) mbl_x_r[6:3] <= mb_first_in_row? {2'b0,left_marg[4:3]} : mbl_x_next_r[6:3];
if (mb_pre_start[2]) mbl_x_last_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {2'b0,mb_w_m1[5:3]}; if (mb_pre_start[2]) mbl_x_last_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {2'b0,mb_w_m1[5:3]};
if (mb_pre_start[3]) begin
if (reset_page_rd) needed_page[2:0] <= 0; // together with next_valid, next_invalid
else if (mb_pre_start[3]) begin
case (tile_width) case (tile_width)
2'b00: needed_page[2:0] <= next_invalid[2:0]+{1'b0, mbl_x_last_r[5:4]}; 2'b00: needed_page[2:0] <= next_invalid[2:0]+{1'b0, mbl_x_last_r[5:4]};
2'b01: needed_page[2:0] <= next_invalid[2:0]+{1'b0, mbl_x_last_r[6:5]}; 2'b01: needed_page[2:0] <= next_invalid[2:0]+{1'b0, mbl_x_last_r[6:5]};
......
compressor_jp/compressor393.v
View file @ 4bb4f227
...@@ -176,6 +176,8 @@ module compressor393 # ( ...@@ -176,6 +176,8 @@ module compressor393 # (
// Used withe a single-frame buffers // Used withe a single-frame buffers
input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
input [4*LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel input [4*LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
input [3:0] frames_in_sync, // frame number in destination memory channel is valid for bonded mode
input [3:0]frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input [3:0]frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353 // use as 'eot_real' in 353
output [3:0]suspend, // suspend reading data for this channel - waiting for the source data output [3:0]suspend, // suspend reading data for this channel - waiting for the source data
...@@ -441,6 +443,7 @@ module compressor393 # ( ...@@ -441,6 +443,7 @@ module compressor393 # (
.frame_done_src (frame_done_src[i]), // input .frame_done_src (frame_done_src[i]), // input
.line_unfinished_dst (line_unfinished_dst[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0] .line_unfinished_dst (line_unfinished_dst[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0] .frame_number_dst (frame_number_dst[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frames_in_sync (frames_in_sync[i]), //input
.frame_done_dst (frame_done_dst[i]), // input .frame_done_dst (frame_done_dst[i]), // input
.suspend (suspend[i]), // output .suspend (suspend[i]), // output
.frame_number_finished (frame_number_finished[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // output reg[15:0] .frame_number_finished (frame_number_finished[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // output reg[15:0]
......
compressor_jp/jp_channel.v
View file @ 4bb4f227
...@@ -163,6 +163,7 @@ module jp_channel#( ...@@ -163,6 +163,7 @@ module jp_channel#(
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel input [FRAME_HEIGHT_BITS-1:0] line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel input [LAST_FRAME_BITS-1:0] frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
input frames_in_sync, // frame number in destination memory channel is valid for bonded mode
input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353 // use as 'eot_real' in 353
output suspend, // suspend reading data for this channel - waiting for the source data output suspend, // suspend reading data for this channel - waiting for the source data
...@@ -802,6 +803,7 @@ module jp_channel#( ...@@ -802,6 +803,7 @@ module jp_channel#(
// Used withe a single-frame buffers // Used withe a single-frame buffers
.line_unfinished (line_unfinished_dst), // input[15:0] - number of the current (unfinished ) line in this (compressor) channel .line_unfinished (line_unfinished_dst), // input[15:0] - number of the current (unfinished ) line in this (compressor) channel
.frame_number (frame_number_dst), // input[15:0] - current frame number (for multi-frame ranges) in this (compressor channel .frame_number (frame_number_dst), // input[15:0] - current frame number (for multi-frame ranges) in this (compressor channel
.frames_in_sync (frames_in_sync), // frame number in destination memory channel is valid for bonded mode
.frame_done (frame_done_dst), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory .frame_done (frame_done_dst), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
.suspend (suspend), // output reg - suspend reading data for this channel - waiting for the source data .suspend (suspend), // output reg - suspend reading data for this channel - waiting for the source data
.stuffer_running (stuffer_running), // input .stuffer_running (stuffer_running), // input
...@@ -823,6 +825,7 @@ module jp_channel#( ...@@ -823,6 +825,7 @@ module jp_channel#(
.frame_en (frame_en), // input .frame_en (frame_en), // input
.frame_start_xclk (frame_start_xclk), // input@posedge xclk - parameters are copied @ this pulse .frame_start_xclk (frame_start_xclk), // input@posedge xclk - parameters are copied @ this pulse
.frame_go (frame_go), // input - do not use - assign to frame_en? Running frames can be controlled by other means .frame_go (frame_go), // input - do not use - assign to frame_en? Running frames can be controlled by other means
.cmprs_run_mclk (cmprs_run_mclk), // input used to reset frame_pre_run (enable vsync_late for the new frame after stop)
.left_marg (left_marg), // input[4:0] .left_marg (left_marg), // input[4:0]
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0] .n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
.n_block_rows_m1 (n_block_rows_m1), // input[12:0] .n_block_rows_m1 (n_block_rows_m1), // input[12:0]
......
fpga_version.vh
View file @ 4bb4f227
...@@ -35,7 +35,12 @@ ...@@ -35,7 +35,12 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h039300a9; // parallel, added copying maste-t-slave frame number -0.169(8 paths), 80.28% parameter FPGA_VERSION = 32'h039300ae; // parallel, increasing sesnsor-channels maximal delays to 12 bits
// parameter FPGA_VERSION = 32'h039300ad; // parallel, resetting frame_pre_run. All met, 79.97%
// parameter FPGA_VERSION = 32'h039300ac; // parallel, adding reset needed_page in compressor -0.012 (2), 79.39%
// parameter FPGA_VERSION = 32'h039300ab; // parallel, more on frame sync in compressor All met, 79.04%
// parameter FPGA_VERSION = 32'h039300aa; // parallel, improving frame sync in compressor -0.036ns, 79.60%
// parameter FPGA_VERSION = 32'h039300a9; // parallel, added copying maste-t-slave frame number -0.169(8 paths), 80.28%
// parameter FPGA_VERSION = 32'h039300a8; // parallel, fixing BUG in command sequencer that was missing some commands 79.25%, all met // parameter FPGA_VERSION = 32'h039300a8; // parallel, fixing BUG in command sequencer that was missing some commands 79.25%, all met
// parameter FPGA_VERSION = 32'h039300a7; // parallel, changing parameter to reset buffer pages at each frame start. 79.4%, -0.022 (2 paths) // parameter FPGA_VERSION = 32'h039300a7; // parallel, changing parameter to reset buffer pages at each frame start. 79.4%, -0.022 (2 paths)
// parameter FPGA_VERSION = 32'h039300a6; // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated // parameter FPGA_VERSION = 32'h039300a6; // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated
......
includes/x393_parameters.vh
View file @ 4bb4f227
...@@ -299,7 +299,7 @@ ...@@ -299,7 +299,7 @@
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode) parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse
// Channel test module parameters // Channel test module parameters
......
memctrl/mcntrl393.v
View file @ 4bb4f227
...@@ -262,7 +262,7 @@ module mcntrl393 #( ...@@ -262,7 +262,7 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode) parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
) ( ) (
...@@ -350,6 +350,8 @@ module mcntrl393 #( ...@@ -350,6 +350,8 @@ module mcntrl393 #(
// Used withe a single-frame buffers // Used withe a single-frame buffers
output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_dst,// number of the current (unfinished ) line in this (compressor) channel
output [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel output [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_dst, // current frame number (for multi-frame ranges) in this (compressor channel
output [3:0] cmprs_frames_in_sync, // cmprs_frame_number_dst is valid (in bonded mode)
output [3:0] cmprs_frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory output [3:0] cmprs_frame_done_dst, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353 // use as 'eot_real' in 353
input [3:0] cmprs_suspend, // suspend reading data for this channel - waiting for the source data input [3:0] cmprs_suspend, // suspend reading data for this channel - waiting for the source data
...@@ -1205,6 +1207,7 @@ module mcntrl393 #( ...@@ -1205,6 +1207,7 @@ module mcntrl393 #(
.line_unfinished (cmprs_line_unfinished_dst[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]), // output[15:0] .line_unfinished (cmprs_line_unfinished_dst[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]), // output[15:0]
.suspend (cmprs_suspend[i]), // input .suspend (cmprs_suspend[i]), // input
.frame_number (cmprs_frame_number_dst[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // output[15:0] .frame_number (cmprs_frame_number_dst[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // output[15:0]
.frames_in_sync (cmprs_frames_in_sync[i]), // output
.master_frame (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // input[15:0] .master_frame (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // input[15:0]
.master_set (sens_frame_set[i]), // input .master_set (sens_frame_set[i]), // input
// .master_follow (master_follow[i]), // input // .master_follow (master_follow[i]), // input
...@@ -1431,6 +1434,7 @@ module mcntrl393 #( ...@@ -1431,6 +1434,7 @@ module mcntrl393 #(
.line_unfinished (line_unfinished_chn2), // output[15:0] .line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input .suspend (suspend_chn2), // input
.frame_number (frame_number_chn2), .frame_number (frame_number_chn2),
.frames_in_sync(), // output
.master_frame (16'b0), // input[15:0] .master_frame (16'b0), // input[15:0]
.master_set (1'b0), // input .master_set (1'b0), // input
// .master_follow (1'b0), // input // .master_follow (1'b0), // input
...@@ -1502,6 +1506,7 @@ module mcntrl393 #( ...@@ -1502,6 +1506,7 @@ module mcntrl393 #(
.line_unfinished (line_unfinished_chn4), // output[15:0] .line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input .suspend (suspend_chn4), // input
.frame_number (frame_number_chn4), // output [15:0] .frame_number (frame_number_chn4), // output [15:0]
.frames_in_sync (), // output
.master_frame (16'b0), // input[15:0] .master_frame (16'b0), // input[15:0]
.master_set (1'b0), // input .master_set (1'b0), // input
// .master_follow (1'b0), // input // .master_follow (1'b0), // input
......
memctrl/mcntrl_linear_rw.v
View file @ 4bb4f227
...@@ -82,7 +82,7 @@ module mcntrl_linear_rw #( ...@@ -82,7 +82,7 @@ module mcntrl_linear_rw #(
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the // TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive - // first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
// just continue. // just continue.
parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
)( )(
input mrst, input mrst,
...@@ -257,12 +257,12 @@ module mcntrl_linear_rw #( ...@@ -257,12 +257,12 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start_late reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start_late
reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped) reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start
wire frame_start_late; reg [MCNTRL_SCANLINE_DLY_WIDTH:0] start_delay_cntr = {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}}; // start delay counter
reg frame_start_late;
wire set_start_delay_w; wire set_start_delay_w;
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4 // if total number of pages in a frame is not multiple of 4
assign frame_number = frame_number_current; assign frame_number = frame_number_current;
assign set_mode_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE); assign set_mode_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
...@@ -290,12 +290,13 @@ module mcntrl_linear_rw #( ...@@ -290,12 +290,13 @@ module mcntrl_linear_rw #(
else single_frame_r <= single_frame_w; else single_frame_r <= single_frame_w;
if (mrst) rst_frame_num_r <= 0; if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0], else rst_frame_num_r <= {rst_frame_num_r[0], rst_frame_num_w }; // now only at specific command
rst_frame_num_w | /*
|
set_start_addr_w | set_start_addr_w |
set_last_frame_w | set_last_frame_w |
set_frame_size_w}; set_frame_size_w};
*/
if (mrst) start_range_addr <= 0; if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0]; else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
...@@ -315,13 +316,14 @@ module mcntrl_linear_rw #( ...@@ -315,13 +316,14 @@ module mcntrl_linear_rw #(
// if (mrst) frame_start_r <= 0; // if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en}; // else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
if (mrst) frame_en <= 0; // if (mrst) frame_en <= 0;
if (!chn_en) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1; else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start_late) frame_en <= 0; else if (frame_start_late) frame_en <= 0;
// will reset buffer page at next frame start // will reset buffer page at next frame start
if (mrst ||frame_start_r[0]) buf_reset_pend <= 0; if (mrst ||frame_start_r[0]) buf_reset_pend <= 0;
else if (rst_frame_num_r) buf_reset_pend <= 1; else if (rst_frame_num_r[0]) buf_reset_pend <= 1;
if (mrst) frame_number_cntr <= 0; if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0; else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
...@@ -365,6 +367,14 @@ module mcntrl_linear_rw #( ...@@ -365,6 +367,14 @@ module mcntrl_linear_rw #(
if (mrst) start_delay <= MCNTRL_SCANLINE_DLY_DEFAULT; if (mrst) start_delay <= MCNTRL_SCANLINE_DLY_DEFAULT;
else if (set_start_delay_w) start_delay <= cmd_data[MCNTRL_SCANLINE_DLY_WIDTH-1:0]; else if (set_start_delay_w) start_delay <= cmd_data[MCNTRL_SCANLINE_DLY_WIDTH-1:0];
if (mrst) start_delay_cntr <= {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}};
else if (frame_start) start_delay_cntr <= {1'b0, start_delay};
else if (!start_delay_cntr[MCNTRL_SCANLINE_DLY_WIDTH]) start_delay_cntr <= start_delay_cntr - 1;
frame_start_late <= start_delay_cntr == 0;
//
end end
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0]; assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
...@@ -694,17 +704,5 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -694,17 +704,5 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
.rq (status_rq), // output .rq (status_rq), // output
.start (status_start) // input .start (status_start) // input
); );
dly_var #(
.WIDTH (1),
.DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH)
) frame_start_late_i (
.clk (mclk), // input
.rst (mrst), // input
.dly (start_delay), // input[0:0]
.din (frame_start), // input[0:0]
.dout (frame_start_late) // output[0:0]
);
endmodule endmodule
memctrl/mcntrl_tiled_rw.v
View file @ 4bb4f227
...@@ -105,6 +105,7 @@ module mcntrl_tiled_rw#( ...@@ -105,6 +105,7 @@ module mcntrl_tiled_rw#(
output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line, RELATIVE TO FRAME, NOT WINDOW. output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line, RELATIVE TO FRAME, NOT WINDOW.
input suspend, // suspend transfers (from external line number comparator) input suspend, // suspend transfers (from external line number comparator)
output [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges) output [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges)
output frames_in_sync, // frame number valid for bonded mode
input [LAST_FRAME_BITS-1:0] master_frame, // current frame number of a master channel input [LAST_FRAME_BITS-1:0] master_frame, // current frame number of a master channel
input master_set, // master frame number set (1-st cycle when new value is valid) input master_set, // master frame number set (1-st cycle when new value is valid)
// input master_follow, // copy master frame number instead of reset @master_set, 0 - ignore master_set // input master_follow, // copy master frame number instead of reset @master_set, 0 - ignore master_set
...@@ -272,7 +273,9 @@ module mcntrl_tiled_rw#( ...@@ -272,7 +273,9 @@ module mcntrl_tiled_rw#(
reg set_frame_from_master; // single-clock copy frame counter from the master channel reg set_frame_from_master; // single-clock copy frame counter from the master channel
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4 // if total number of pages in a frame is not multiple of 4
reg frames_in_sync_r;
assign frames_in_sync = frames_in_sync_r;
assign frame_number = frame_number_current; assign frame_number = frame_number_current;
assign set_mode_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE); assign set_mode_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE);
...@@ -300,11 +303,11 @@ module mcntrl_tiled_rw#( ...@@ -300,11 +303,11 @@ module mcntrl_tiled_rw#(
else single_frame_r <= single_frame_w; else single_frame_r <= single_frame_w;
if (mrst) rst_frame_num_r <= 0; if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0], else rst_frame_num_r <= {rst_frame_num_r[0], rst_frame_num_w}; // resetting only at specific command
rst_frame_num_w | //|
set_start_addr_w | // set_start_addr_w |
set_last_frame_w | // set_last_frame_w |
set_frame_size_w}; // set_frame_size_w};
if (mrst) start_range_addr <= 0; if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0]; else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
...@@ -325,16 +328,23 @@ module mcntrl_tiled_rw#( ...@@ -325,16 +328,23 @@ module mcntrl_tiled_rw#(
if (mrst) frame_start_r <= 0; if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en}; else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
if (mrst) frame_en <= 0; // if (mrst) frame_en <= 0;
if (!chn_en) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1; else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start) frame_en <= 0; else if (frame_start) frame_en <= 0;
if (mrst ||master_set) frame_master_pend <= 0; if (mrst ||master_set) frame_master_pend <= 0;
else if (set_copy_frame_num_w) frame_master_pend <= 1; else if (set_copy_frame_num_w) frame_master_pend <= 1;
// after channel was disabled frame number reported is incorrect, until updated by master_set
// Without this signal compressor was reading data between the time source frame number was updated and this one.
if (!chn_en) frames_in_sync_r <= 0;
// else if (frame_start_r[2]) frames_in_sync_r <= 1;
else if (frame_start_r[3]) frames_in_sync_r <= 1; // to match line_unfinished
// will reset buffer page at next frame start // will reset buffer page at next frame start
if (mrst ||frame_start_r[0]) buf_reset_pend <= 0; if (mrst ||frame_start_r[0]) buf_reset_pend <= 0;
else if (rst_frame_num_r) buf_reset_pend <= 1; else if (rst_frame_num_r[0]) buf_reset_pend <= 1;
set_frame_from_master <= master_set && frame_master_pend; set_frame_from_master <= master_set && frame_master_pend;
......
py393/x393_cmprs.py
View file @ 4bb4f227
...@@ -461,7 +461,7 @@ class X393Cmprs(object): ...@@ -461,7 +461,7 @@ class X393Cmprs(object):
disable_need = disable_need, disable_need = disable_need,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # Now needed to propagate start address False,
byte32 = byte32, byte32 = byte32,
keep_open = False, keep_open = False,
extra_pages = extra_pages, extra_pages = extra_pages,
......
py393/x393_export_c.py
View file @ 4bb4f227
...@@ -1654,7 +1654,7 @@ class X393ExportC(object): ...@@ -1654,7 +1654,7 @@ class X393ExportC(object):
dw.append(("extra_pages", vrlg.MCONTR_LINTILE_EXTRAPG, vrlg.MCONTR_LINTILE_EXTRAPG_BITS,0, "2-bit number of extra pages that need to stay (not to be overwritten) in the buffer")) dw.append(("extra_pages", vrlg.MCONTR_LINTILE_EXTRAPG, vrlg.MCONTR_LINTILE_EXTRAPG_BITS,0, "2-bit number of extra pages that need to stay (not to be overwritten) in the buffer"))
dw.append(("keep_open", vrlg.MCONTR_LINTILE_KEEP_OPEN,1,0, "for 8 or less rows - do not close page between accesses (not used in scanline mode)")) dw.append(("keep_open", vrlg.MCONTR_LINTILE_KEEP_OPEN,1,0, "for 8 or less rows - do not close page between accesses (not used in scanline mode)"))
dw.append(("byte32", vrlg.MCONTR_LINTILE_BYTE32,1,1, "32-byte columns (0 - 16-byte), not used in scanline mode")) dw.append(("byte32", vrlg.MCONTR_LINTILE_BYTE32,1,1, "32-byte columns (0 - 16-byte), not used in scanline mode"))
dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number (also resets buffer at next frame start)")) dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number (also resets buffer at next frame start). NEEDED after initial set up to propagate start address!"))
dw.append(("single", vrlg.MCONTR_LINTILE_SINGLE,1,0, "run single frame")) dw.append(("single", vrlg.MCONTR_LINTILE_SINGLE,1,0, "run single frame"))
dw.append(("repetitive", vrlg.MCONTR_LINTILE_REPEAT,1,1, "run repetitive frames")) dw.append(("repetitive", vrlg.MCONTR_LINTILE_REPEAT,1,1, "run repetitive frames"))
dw.append(("disable_need", vrlg.MCONTR_LINTILE_DIS_NEED,1,0, "disable 'need' generation, only 'want' (compressor channels)")) dw.append(("disable_need", vrlg.MCONTR_LINTILE_DIS_NEED,1,0, "disable 'need' generation, only 'want' (compressor channels)"))
......
py393/x393_jpeg.py
View file @ 4bb4f227
...@@ -1429,11 +1429,11 @@ write_cmd_frame_sequencer 0 0 2 0x700 0x600 ...@@ -1429,11 +1429,11 @@ write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900 write_cmd_frame_sequencer 0 0 2 0x700 0x900
#stop compressor memory @2, restart @3 and copy frame number # Better to turn off compressor before resetting memory channel #stop compressor memory @2, restart @3 and copy frame number # Better to turn off compressor before resetting memory channel
write_cmd_frame_sequencer 0 1 2 0x600 0x5 # stop compressor write_cmd_frame_sequencer 0 1 3 0x600 0x5 # stop compressor
#write_cmd_frame_sequencer 0 1 2 0x6c0 0x1c49 # enable off #write_cmd_frame_sequencer 0 1 3 0x6c0 0x1c49 # enable off
#write_cmd_frame_sequencer 0 1 3 0x6c0 0x3c4b # enable on, copy frame #write_cmd_frame_sequencer 0 1 4 0x6c0 0x3c4b # enable on, copy frame
#write_cmd_frame_sequencer 0 1 3 0x6c0 0x3d4b # enable on, copy frame, reset buffer #write_cmd_frame_sequencer 0 1 4 0x6c0 0x3d4b # enable on, copy frame, reset buffer
write_cmd_frame_sequencer 0 1 3 0x600 0x7 # run compressor (after memory?) write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (after memory?)
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68 #set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays? #set_sensor_io_ctl all None None None None None 1 None # load all delays?
...@@ -1443,8 +1443,149 @@ compressor_interrupt_control all en ...@@ -1443,8 +1443,149 @@ compressor_interrupt_control all en
compressor_control all 3 compressor_control all 3
jpeg_sim_multi 4 jpeg_sim_multi 4
jpeg_sim_multi 8 jpeg_sim_multi 8
jpeg_sim_multi 8
jpeg_sim_multi 4
################## Simulate Parallel 3 ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
#sequencer test
#ctrl_cmd_frame_sequencer <num_sensor> <reset=False> <start=False> <stop=False>
ctrl_cmd_frame_sequencer 0 0 1 0
write_cmd_frame_sequencer 0 1 1 0x700 0x6
write_cmd_frame_sequencer 0 1 1 0x700 0x9
write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
write_cmd_frame_sequencer 0 0 2 0x700 0x9
write_cmd_frame_sequencer 0 0 2 0x700 0x60
write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
#stop compressor memory @2, restart @3 and copy frame number # Better to turn off compressor before resetting memory channel
#write_cmd_frame_sequencer 0 1 3 0x600 0x5 # stop compressor
write_cmd_frame_sequencer 0 1 2 0x6c0 0x1c49 # enable off
write_cmd_frame_sequencer 0 1 4 0x6c0 0x3c4b # enable on, copy frame
#write_cmd_frame_sequencer 0 1 4 0x6c0 0x3d4b # enable on, copy frame, reset buffer
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (after memory?)
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
jpeg_sim_multi 4
jpeg_sim_multi 8
jpeg_sim_multi 8
jpeg_sim_multi 4
################## Simulate Parallel 4 ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
#sequencer test
#ctrl_cmd_frame_sequencer <num_sensor> <reset=False> <start=False> <stop=False>
ctrl_cmd_frame_sequencer 0 0 1 0
write_cmd_frame_sequencer 0 1 1 0x700 0x6
write_cmd_frame_sequencer 0 1 1 0x700 0x9
write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
write_cmd_frame_sequencer 0 0 2 0x700 0x9
write_cmd_frame_sequencer 0 0 2 0x700 0x60
write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
#stop compressor memory @2, restart @3 and copy frame number # Better to turn off compressor before resetting memory channel
#write_cmd_frame_sequencer 0 1 3 0x600 0x5 # stop compressor
write_cmd_frame_sequencer 0 1 2 0x6c0 0x1c49 # enable off
write_cmd_frame_sequencer 0 1 4 0x6c0 0x3c4b # enable on, copy frame
#write_cmd_frame_sequencer 0 1 4 0x6c0 0x3d4b # enable on, copy frame, reset buffer
#### write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (after memory?)
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
jpeg_sim_multi 4
jpeg_sim_multi 8
jpeg_sim_multi 8
jpeg_sim_multi 4
################## Simulate Parallel 5 ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
#irq coming, image not changing - yes
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 2 0x680 0x1405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
write_cmd_frame_sequencer 0 1 2 0x6c0 0x1c49 # stop compressor memory (+0)
write_cmd_frame_sequencer 0 1 3 0x680 0x1507 # run sensor memory (+1) Can not be 0
write_cmd_frame_sequencer 0 1 4 0x6c0 0x3d4b # run compressor memory (+2)
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
#sequencer test
#ctrl_cmd_frame_sequencer <num_sensor> <reset=False> <start=False> <stop=False>
ctrl_cmd_frame_sequencer 0 0 1 0
write_cmd_frame_sequencer 0 1 1 0x700 0x6
write_cmd_frame_sequencer 0 1 1 0x700 0x9
write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
write_cmd_frame_sequencer 0 0 2 0x700 0x9
write_cmd_frame_sequencer 0 0 2 0x700 0x60
write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
jpeg_sim_multi 4
jpeg_sim_multi 8
jpeg_sim_multi 8
jpeg_sim_multi 4
#write_cmd_frame_sequencer 0 1 4 0x6c0 0x1c49 # stop compressor memory (+0)
#write_cmd_frame_sequencer 0 1 6 0x6c0 0x3d4b # enable run compressor memory (+2)
################## Serial #################### ################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
......
py393/x393_mcntrl_membridge.py
View file @ 4bb4f227
...@@ -309,7 +309,7 @@ class X393McntrlMembridge(object): ...@@ -309,7 +309,7 @@ class X393McntrlMembridge(object):
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # Is needed to propagate start addressFalse,
extra_pages = 0, extra_pages = 0,
write_mem = write_ddr3, write_mem = write_ddr3,
enable = True, enable = True,
......
py393/x393_mcntrl_tests.py
View file @ 4bb4f227
...@@ -294,7 +294,7 @@ class X393McntrlTests(object): ...@@ -294,7 +294,7 @@ class X393McntrlTests(object):
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # False,
extra_pages = extra_pages, extra_pages = extra_pages,
write_mem = True, write_mem = True,
enable = True, enable = True,
...@@ -447,7 +447,7 @@ class X393McntrlTests(object): ...@@ -447,7 +447,7 @@ class X393McntrlTests(object):
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # False,
extra_pages = extra_pages, extra_pages = extra_pages,
write_mem = False, write_mem = False,
enable = True, enable = True,
...@@ -562,7 +562,7 @@ class X393McntrlTests(object): ...@@ -562,7 +562,7 @@ class X393McntrlTests(object):
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # False,
byte32 = byte32, byte32 = byte32,
keep_open = keep_open, keep_open = keep_open,
extra_pages = extra_pages, extra_pages = extra_pages,
...@@ -705,7 +705,7 @@ class X393McntrlTests(object): ...@@ -705,7 +705,7 @@ class X393McntrlTests(object):
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # False,
byte32 = byte32, byte32 = byte32,
keep_open = keep_open, keep_open = keep_open,
extra_pages = extra_pages, extra_pages = extra_pages,
......
py393/x393_sens_cmprs.py
View file @ 4bb4f227
...@@ -964,6 +964,13 @@ class X393SensCmprs(object): ...@@ -964,6 +964,13 @@ class X393SensCmprs(object):
for i in range(4): for i in range(4):
frames.append (int((status >> (4*i)) & 0xf)) frames.append (int((status >> (4*i)) & 0xf))
return frames return frames
def get_frame_number(self,
channel=0):
"""
@return frame number of the sequencer for the specified channel (4 bits)
"""
status = self.x393_axi_tasks.read_status(address = vrlg.CMDSEQMUX_STATUS)
return int((status >> (4*channel)) & 0xf)
def get_frame_number_i2c(self, def get_frame_number_i2c(self,
channel=0): channel=0):
...@@ -1003,6 +1010,19 @@ class X393SensCmprs(object): ...@@ -1003,6 +1010,19 @@ class X393SensCmprs(object):
break; break;
return frameno # Frame number of the last new frame checked return frameno # Frame number of the last new frame checked
def wait_frame(self,
channel = 0,
frame = 0,
loop_delay = 0.01,
timeout = 2.0):
timeout_time = time.time() + timeout
frameno = -1
while time.time() < timeout_time :
frameno = self.get_frame_number(channel)
if frameno == (frame & 15):
return frameno
return frameno # Frame number of the last new frame checked
def skip_frame_i2c(self, def skip_frame_i2c(self,
channel_mask, channel_mask,
loop_delay = 0.01, loop_delay = 0.01,
...@@ -1828,7 +1848,7 @@ class X393SensCmprs(object): ...@@ -1828,7 +1848,7 @@ class X393SensCmprs(object):
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # False, now start address is only copied at reset_frame
extra_pages = 0, extra_pages = 0,
write_mem = write_mem, write_mem = write_mem,
enable = True, enable = True,
......
py393/x393_sensor.py
View file @ 4bb4f227
...@@ -1928,7 +1928,7 @@ input mem mtd4 ram1 ...@@ -1928,7 +1928,7 @@ input mem mtd4 ram1
stop - stop at the end of the frame (if repetitive), stop - stop at the end of the frame (if repetitive),
single - acquire single frame , single - acquire single frame ,
repetitive - repetitive mode repetitive - repetitive mode
@param reset_frame - reset frame number @param reset_frame - reset frame number. Needed after changing frame start address (i.e. initial set-up) !
@param vebose - verbose level @param vebose - verbose level
""" """
try: try:
...@@ -2005,7 +2005,7 @@ input mem mtd4 ram1 ...@@ -2005,7 +2005,7 @@ input mem mtd4 ram1
disable_need = False, disable_need = False,
repetitive= True, repetitive= True,
single = False, single = False,
reset_frame = False, reset_frame = True, # False,
extra_pages = 0, extra_pages = 0,
write_mem = True, write_mem = True,
enable = True, enable = True,
......
x393.v
View file @ 4bb4f227
...@@ -529,6 +529,7 @@ module x393 #( ...@@ -529,6 +529,7 @@ module x393 #(
// Used withe a single-frame buffers // Used withe a single-frame buffers
wire [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_dst; // input[15:0] number of the current (unfinished ) line in this (compressor) channel wire [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_dst; // input[15:0] number of the current (unfinished ) line in this (compressor) channel
wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_dst; // input[15:0] current frame number (for multi-frame ranges) in this (compressor channel wire [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_dst; // input[15:0] current frame number (for multi-frame ranges) in this (compressor channel
wire [3:0] cmprs_frames_in_sync; // cmprs_frame_number_dst is valid (in bonded mode)
wire [3:0] cmprs_frame_done_dst; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory wire [3:0] cmprs_frame_done_dst; // input single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// use as 'eot_real' in 353 // use as 'eot_real' in 353
wire [3:0] cmprs_suspend; // output suspend reading data for this channel - waiting for the source data wire [3:0] cmprs_suspend; // output suspend reading data for this channel - waiting for the source data
...@@ -1354,6 +1355,8 @@ assign axi_grst = axi_rst_pre; ...@@ -1354,6 +1355,8 @@ assign axi_grst = axi_rst_pre;
.cmprs_frame_done_src (cmprs_frame_done_src), // output[3:0] .cmprs_frame_done_src (cmprs_frame_done_src), // output[3:0]
.cmprs_line_unfinished_dst (cmprs_line_unfinished_dst), // output[63:0] .cmprs_line_unfinished_dst (cmprs_line_unfinished_dst), // output[63:0]
.cmprs_frame_number_dst (cmprs_frame_number_dst), // output[63:0] .cmprs_frame_number_dst (cmprs_frame_number_dst), // output[63:0]
.cmprs_frames_in_sync (cmprs_frames_in_sync), // output[3:0]
.cmprs_frame_done_dst (cmprs_frame_done_dst), // output[3:0] .cmprs_frame_done_dst (cmprs_frame_done_dst), // output[3:0]
.cmprs_suspend (cmprs_suspend), // input[3:0] .cmprs_suspend (cmprs_suspend), // input[3:0]
// .master_follow (cmprs_master_follow), // input[3:0] // .master_follow (cmprs_master_follow), // input[3:0]
...@@ -2090,6 +2093,7 @@ assign axi_grst = axi_rst_pre; ...@@ -2090,6 +2093,7 @@ assign axi_grst = axi_rst_pre;
.frame_done_src (cmprs_frame_done_src), // input[3:0] .frame_done_src (cmprs_frame_done_src), // input[3:0]
.line_unfinished_dst (cmprs_line_unfinished_dst), // input[63:0] .line_unfinished_dst (cmprs_line_unfinished_dst), // input[63:0]
.frame_number_dst (cmprs_frame_number_dst), // input[63:0] .frame_number_dst (cmprs_frame_number_dst), // input[63:0]
.frames_in_sync (cmprs_frames_in_sync), // input[3:0]
.frame_done_dst (cmprs_frame_done_dst), // input[3:0] .frame_done_dst (cmprs_frame_done_dst), // input[3:0]
.suspend (cmprs_suspend), // output[3:0] .suspend (cmprs_suspend), // output[3:0]
......
x393_parallel.bit
View file @ 4bb4f227
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