write leveling done, working on write buffer (4bacb90a) · Commits · Elphel / x393

.settings/com.elphel.vdt.iverilog.prefs

+2 −1

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	com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->
	eclipse.preferences.version=1		eclipse.preferences.version=1
	iverilog_77_Param_Exe=/usr/local/bin/iverilog		iverilog_77_Param_Exe=/usr/local/bin/iverilog
	iverilog_78_VVP_Exe=/usr/local/bin/vvp		iverilog_78_VVP_Exe=/usr/local/bin/vvp
	iverilog_81_TopModulesOther=glbl<-@\#\#@->		iverilog_81_TopModulesOther=glbl<-@\#\#@->
	iverilog_83_ExtraFiles=glbl.v<-@\#\#@->		iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
			iverilog_84_IncludeDir=/data/vdt/vdt-projects/eddr3/ddr3<-@\#\#@->
	iverilog_88_ShowNoProblem=true		iverilog_88_ShowNoProblem=true
	iverilog_99_GrepFindErrWarn=error\|warning\|sorry		iverilog_99_GrepFindErrWarn=error\|warning\|sorry

+3 −3

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	@@ -115,7 +115,7 @@ module ddr3 (
	`elsif den2048Mb		`elsif den2048Mb
	`include "2048Mb_ddr3_parameters.vh"		`include "2048Mb_ddr3_parameters.vh"
	`elsif den4096Mb		`elsif den4096Mb
	`include "ddr3/4096Mb_ddr3_parameters.vh"		`include "4096Mb_ddr3_parameters.vh"
	`else		`else
	// NOTE: Intentionally cause a compile fail here to force the users		// NOTE: Intentionally cause a compile fail here to force the users
	// to select the correct component density before continuing		// to select the correct component density before continuing
	@@ -606,11 +606,11 @@ module ddr3 (
	floor = number;		floor = number;
	endfunction		endfunction

	function integer max( input integer a, b );		function integer max( input integer a, input integer b );
	max = (a < b) ? b : a;		max = (a < b) ? b : a;
	endfunction		endfunction

	function integer min( input integer a, b );		function integer min( input integer a, input integer b );
	min = (a > b) ? b : a;		min = (a > b) ? b : a;
	endfunction		endfunction

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -43,8 +43,8 @@ module ddrc_test01 #(
	parameter SS_EN = "FALSE",		parameter SS_EN = "FALSE",
	parameter SS_MODE = "CENTER_HIGH",		parameter SS_MODE = "CENTER_HIGH",
	parameter SS_MOD_PERIOD = 10000,		parameter SS_MOD_PERIOD = 10000,
	parameter CMD_PAUSE_BITS= 6,		parameter CMD_PAUSE_BITS= 10,
	parameter CMD_DONE_BIT= 6,		parameter CMD_DONE_BIT= 10,
	parameter AXI_WR_ADDR_BITS = 13,		parameter AXI_WR_ADDR_BITS = 13,
	parameter AXI_RD_ADDR_BITS = 13,		parameter AXI_RD_ADDR_BITS = 13,
	parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers		parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
	@@ -92,10 +92,10 @@ module ddrc_test01 #(
	output SDODT, // output ODT port		output SDODT, // output ODT port

	inout [15:0] SDD, // DQ I/O pads		inout [15:0] SDD, // DQ I/O pads
	inout SDDML, // LDM I/O pad (actually only output)		output SDDML, // LDM I/O pad (actually only output)
	inout DQSL, // LDQS I/O pad		inout DQSL, // LDQS I/O pad
	inout NDQSL, // ~LDQS I/O pad		inout NDQSL, // ~LDQS I/O pad
	inout SDDMU, // UDM I/O pad (actually only output)		output SDDMU, // UDM I/O pad (actually only output)
	inout DQSU, // UDQS I/O pad		inout DQSU, // UDQS I/O pad
	inout NDQSU // ~UDQS I/O pad		inout NDQSU // ~UDQS I/O pad
	// AXI write (ps -> pl)		// AXI write (ps -> pl)