Skip to content

X
x393
Commit 4bacb90a authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

write leveling done, working on write buffer

parent 1b719ff1
Show whitespace changes
Inline Side-by-side
Showing with 1066 additions and 399 deletions
.settings/com.elphel.vdt.iverilog.prefs
View file @ 4bacb90a
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@-> com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_77_Param_Exe=/usr/local/bin/iverilog iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_81_TopModulesOther=glbl<-@\#\#@-> iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@-> iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=/data/vdt/vdt-projects/eddr3/ddr3<-@\#\#@->
iverilog_88_ShowNoProblem=true iverilog_88_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry iverilog_99_GrepFindErrWarn=error|warning|sorry
ddr3/ddr3.v
View file @ 4bacb90a
...@@ -115,7 +115,7 @@ module ddr3 ( ...@@ -115,7 +115,7 @@ module ddr3 (
`elsif den2048Mb `elsif den2048Mb
`include "2048Mb_ddr3_parameters.vh" `include "2048Mb_ddr3_parameters.vh"
`elsif den4096Mb `elsif den4096Mb
`include "ddr3/4096Mb_ddr3_parameters.vh" `include "4096Mb_ddr3_parameters.vh"
`else `else
// NOTE: Intentionally cause a compile fail here to force the users // NOTE: Intentionally cause a compile fail here to force the users
// to select the correct component density before continuing // to select the correct component density before continuing
...@@ -606,11 +606,11 @@ module ddr3 ( ...@@ -606,11 +606,11 @@ module ddr3 (
floor = number; floor = number;
endfunction endfunction
function integer max( input integer a, b ); function integer max( input integer a, input integer b );
max = (a < b) ? b : a; max = (a < b) ? b : a;
endfunction endfunction
function integer min( input integer a, b ); function integer min( input integer a, input integer b );
min = (a > b) ? b : a; min = (a > b) ? b : a;
endfunction endfunction
......
ddrc_test01.v
View file @ 4bacb90a
...@@ -43,8 +43,8 @@ module ddrc_test01 #( ...@@ -43,8 +43,8 @@ module ddrc_test01 #(
parameter SS_EN = "FALSE", parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH", parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000, parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 6, parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 6, parameter CMD_DONE_BIT= 10,
parameter AXI_WR_ADDR_BITS = 13, parameter AXI_WR_ADDR_BITS = 13,
parameter AXI_RD_ADDR_BITS = 13, parameter AXI_RD_ADDR_BITS = 13,
parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
...@@ -92,10 +92,10 @@ module ddrc_test01 #( ...@@ -92,10 +92,10 @@ module ddrc_test01 #(
output SDODT, // output ODT port output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads inout [15:0] SDD, // DQ I/O pads
inout SDDML, // LDM I/O pad (actually only output) output SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad inout NDQSL, // ~LDQS I/O pad
inout SDDMU, // UDM I/O pad (actually only output) output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU // ~UDQS I/O pad inout NDQSU // ~UDQS I/O pad
// AXI write (ps -> pl) // AXI write (ps -> pl)
......
ddrc_test01_testbench.sav
View file @ 4bacb90a
[*] [*]
[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI [*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
[*] Wed May 28 07:13:39 2014 [*] Fri May 30 07:35:38 2014
[*] [*]
[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140528005647850.lxt" [dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140530013238993.lxt"
[dumpfile_mtime] "Wed May 28 07:00:13 2014" [dumpfile_mtime] "Fri May 30 07:33:55 2014"
[dumpfile_size] 48289383 [dumpfile_size] 55044338
[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav" [savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"
[timestart] 109441730 [timestart] 117839420
[size] 1920 1180 [size] 1920 1180
[pos] -1920 108 [pos] -1920 108
*-13.962209 109532898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-11.298908 117840830 117826250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddrc_test01_testbench. [treeopen] ddrc_test01_testbench.
[treeopen] ddrc_test01_testbench.ddrc_test01_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.
...@@ -18,14 +18,19 @@ ...@@ -18,14 +18,19 @@
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.oserdes_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.
[treeopen] ddrc_test01_testbench.simul_axi_master_wdata_i. [treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i.
[sst_width] 210 [sst_width] 334
[signals_width] 368 [signals_width] 427
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 820 [sst_vpaned_height] 723
@28 @28
ddrc_test01_testbench.RST[0] ddrc_test01_testbench.RST[0]
ddrc_test01_testbench.CLK[0] ddrc_test01_testbench.CLK[0]
...@@ -786,6 +791,140 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ ...@@ -786,6 +791,140 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_
@1401200 @1401200
-idelay_ctrl_i -idelay_ctrl_i
@c00200 @c00200
-byte_lane0_i
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq_r[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs_r[0]
@c00022
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
@28
(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(3)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(4)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(5)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(6)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(7)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(8)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(9)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
@1401200
-group_end
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dm[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dm_r[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs_r[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_r[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_addr[4:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_data[7:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_data_r[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dm[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dout[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_read[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.inv_clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_delay[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_idly[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_idly_dqs[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly_dm[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly_dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ndqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.set[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.set_r[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq_r[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs_r[3:0]
@1401200
-byte_lane0_i
@c00200
-lane0_dqs
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.d_ser[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dci_disable[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.din[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dly_data[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_data_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_di[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_received_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_tri[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_odelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ndqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_odelay[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.tin[3:0]
@1401200
-lane0_dqs
@c00200
-lane1_dqs
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.d_ser[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dci_disable[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.din[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dly_data[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_data_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_di[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_received_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_tri[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.ld_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.ld_odelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.ndqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.set_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.set_odelay[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.tin[3:0]
@c00200
-oserdes_i
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.clk_div[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.din[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.dout_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.dout_iob[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.rst[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.tin[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.tout_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.tout_iob[0]
@1401200
-oserdes_i
-lane1_dqs
@c00200
-ddrc_control_i -ddrc_control_i
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy[0]
...@@ -845,6 +984,21 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out_r[31:0] ...@@ -845,6 +984,21 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out_r[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wr_en[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wr_en[0]
@1401200 @1401200
-ddrc_control_i -ddrc_control_i
@800200
-ddrc_status
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.busy[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.locked[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_out[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_rdy[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.rdata[31:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.run_busy[0]
@1000200
-ddrc_status
@c00200 @c00200
-fifo_cross_clocks -fifo_cross_clocks
@22 @22
...@@ -878,7 +1032,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.wclk[0] ...@@ -878,7 +1032,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.wclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.we[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.we[0]
@1401200 @1401200
-fifo_cross_clocks -fifo_cross_clocks
@800200 @c00200
-phy_cmd_i -phy_cmd_i
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDRST[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDRST[0]
...@@ -886,9 +1040,27 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSL[0] ...@@ -886,9 +1040,27 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSL[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSU[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSU[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSL[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSL[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSU[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSU[0]
@22 @c00022
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
@28 @28
(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(3)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(4)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(5)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(6)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(7)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(8)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(9)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(10)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(11)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(12)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(13)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(14)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
@1401200
-group_end
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDBA[2:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDBA[2:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCAS[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCAS[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCKE[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCKE[0]
...@@ -934,7 +1106,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r1[0] ...@@ -934,7 +1106,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r1[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r2[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r2[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.mclk[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.mclk[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.pause_len[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr[29:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr[29:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr_in[14:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_bank[5:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_bank[5:0]
...@@ -943,9 +1114,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_bank_in[2:0] ...@@ -943,9 +1114,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_bank_in[2:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_buf_rd[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_buf_rd[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_buf_wr[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_buf_wr[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke[1:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke[1:0]
@29
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke_dis[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke_dis[0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke_in[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke_in[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cmd_nop[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cmd_nop[0]
@22 @22
...@@ -979,7 +1148,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata[63:0] ...@@ -979,7 +1148,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata[63:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata_r[63:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata_r[63:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_sel_in[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_sel_in[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_spare[2:0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ps_out[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ps_out[7:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ps_out_r1[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ps_out_r1[7:0]
...@@ -992,7 +1160,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.rst_in[0] ...@@ -992,7 +1160,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.rst_in[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.sequence_done[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.sequence_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.set[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.set[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.set_r[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.set_r[0]
@1000200 @1401200
-phy_cmd_i -phy_cmd_i
@c00200 @c00200
-ddrc_sequencer -ddrc_sequencer
...@@ -1077,8 +1245,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.locked[0] ...@@ -1077,8 +1245,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.locked[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_len[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd0_word[31:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd0_word[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd1_word[31:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd1_word[31:0]
@28 @28
...@@ -1130,9 +1296,11 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0] ...@@ -1130,9 +1296,11 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0]
@1401200 @1401200
-ddrc_sequencer -ddrc_sequencer
@800200 @c00200
-ddr_sequencer_i_selected -ddr_sequencer_i_selected
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCLK[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCLK[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCKE[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCKE[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDBA[2:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDBA[2:0]
...@@ -1176,8 +1344,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0] ...@@ -1176,8 +1344,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_fetch[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_fetch[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[5:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[9:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_len[5:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_nop[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_nop[0]
@22 @22
...@@ -1192,7 +1359,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_done[0] ...@@ -1192,7 +1359,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq_d[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq_d[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
@1000200 @1401200
-ddr_sequencer_i_selected -ddr_sequencer_i_selected
@c00200 @c00200
-ddrc_test01 -ddrc_test01
...@@ -1338,6 +1505,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0] ...@@ -1338,6 +1505,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty_ready[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty_ready[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr[31:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr[31:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr_out[12:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst[1:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst[1:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst_out[1:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst_out[1:0]
...@@ -1397,7 +1565,74 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb[3:0] ...@@ -1397,7 +1565,74 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb[3:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb_out[3:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb_out[3:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0]
@c00200
-axibram_write_waddr
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_in[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_out[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.inreg[32:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.outreg[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.ra[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.re[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.rem[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.rst[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wa[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wem[0]
@1401200 @1401200
-axibram_write_waddr
@c00200
-axibram_write_wdata
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.ra[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.re[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.rem[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.rst[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wa[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
@1401200
-axibram_write_wdata
-axibram_write_i -axibram_write_i
@c00200 @c00200
-wresp_i -wresp_i
...@@ -1566,6 +1801,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_1[0] ...@@ -1566,6 +1801,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_1[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_w[0] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_w[0]
@1401200 @1401200
-axibram_read_i -axibram_read_i
@c00200
-ddrc_status
@22 @22
ddrc_test01_testbench.registered_rdata[31:0] ddrc_test01_testbench.registered_rdata[31:0]
@28 @28
...@@ -1587,6 +1824,8 @@ ddrc_test01_testbench.ddrc_test01_i.axird_pre_araddr[12:0] ...@@ -1587,6 +1824,8 @@ ddrc_test01_testbench.ddrc_test01_i.axird_pre_araddr[12:0]
ddrc_test01_testbench.ddrc_test01_i.axird_start_burst[0] ddrc_test01_testbench.ddrc_test01_i.axird_start_burst[0]
@22 @22
ddrc_test01_testbench.GLOBAL_WRITE_ID[11:0] ddrc_test01_testbench.GLOBAL_WRITE_ID[11:0]
@1401200
-ddrc_status
@c00200 @c00200
-cmd0_buf_i -cmd0_buf_i
@22 @22
...@@ -1606,15 +1845,187 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.we[0] ...@@ -1606,15 +1845,187 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.web[3:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.web[3:0]
@1401200 @1401200
-cmd0_buf_i -cmd0_buf_i
@c00200
-axi_set_dly_single
@22
ddrc_test01_testbench.axi_set_dly_single.delay[7:0]
ddrc_test01_testbench.axi_set_dly_single.dly[31:0]
@28
ddrc_test01_testbench.axi_set_dly_single.group[2:0]
@22
ddrc_test01_testbench.axi_set_dly_single.i[31:0]
ddrc_test01_testbench.axi_set_dly_single.index[4:0]
@1401200
-axi_set_dly_single
@c00200
-axi_write_single
@22
ddrc_test01_testbench.GLOBAL_WRITE_ID[11:0]
ddrc_test01_testbench.axi_write_single.address[31:0]
ddrc_test01_testbench.axi_write_single.data[31:0]
@1401200
-axi_write_single
@c00200
-axi_write_address_data
@28
ddrc_test01_testbench.DEBUG1[0]
ddrc_test01_testbench.AW_READY[0]
ddrc_test01_testbench.W_READY[0]
@22
ddrc_test01_testbench.WID_IN_r[11:0]
@28
ddrc_test01_testbench.CLK[0]
@22
ddrc_test01_testbench.axi_write_addr_data.addr[31:0]
@28
ddrc_test01_testbench.axi_write_addr_data.burst[1:0]
@22
ddrc_test01_testbench.axi_write_addr_data.data[31:0]
@28
ddrc_test01_testbench.axi_write_addr_data.data_en[0]
ddrc_test01_testbench.axi_write_addr_data.data_sent[0]
@22
ddrc_test01_testbench.axi_write_addr_data.id[11:0]
@28
ddrc_test01_testbench.axi_write_addr_data.last[0]
@22
ddrc_test01_testbench.axi_write_addr_data.len[3:0]
ddrc_test01_testbench.axi_write_addr_data.wstrb[3:0]
@1401200
-axi_write_address_data
@c00200
-simul_axi_master_wdata_i
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.clk[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.ready[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.reset[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.set_cmd[0]
@22
ddrc_test01_testbench.simul_axi_master_wdata_i.wdata[31:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wdata_in[31:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wdata_out[31:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wid[11:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wid_in[11:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wid_out[11:0]
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.wlast[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wlast_in[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wlast_out[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wready[0]
@22
ddrc_test01_testbench.simul_axi_master_wdata_i.wstrb[3:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wstrb_in[3:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wstrb_out[3:0]
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.wvalid[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wvalid_out[0]
@1401200
-simul_axi_master_wdata_i
@c00200
-simul_axi_master_wraddr_i
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.awaddr[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awaddr_in[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awaddr_out[31:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.awburst[1:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awburst_in[1:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awburst_out[1:0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.awcache[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awcache_in[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awcache_out[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awid[11:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awid_in[11:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awid_out[11:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awlen[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awlen_in[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awlen_out[3:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.awprot[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awprot_in[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awprot_out[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awready[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awsize[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awsize_in[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awsize_out[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awvalid[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awvalid_out[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.clk[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.ready[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.reset[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.set_cmd[0]
@1401200
-simul_axi_master_wraddr_i
@c00200
-simul_axi_master_wraddr_fifo
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.clk[0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.data_in[59:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.data_out[59:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.in_address[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.in_count[31:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.input_ready[0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.latency_delay[5:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.latency_delay_r[4:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.load[0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_address[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_count[31:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_inc[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.ready[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.reset[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.valid[0]
@1401200
-simul_axi_master_wraddr_fifo
@800200
-write_block
@28
ddrc_test01_testbench.SDCLK[0]
ddrc_test01_testbench.DQSL[0]
ddrc_test01_testbench.DQSU[0]
@22
ddrc_test01_testbench.SDA[14:0]
@28
ddrc_test01_testbench.SDBA[2:0]
ddrc_test01_testbench.SDRAS[0]
ddrc_test01_testbench.SDCAS[0]
ddrc_test01_testbench.SDWE[0]
ddrc_test01_testbench.SDCKE[0]
ddrc_test01_testbench.SDDML[0]
ddrc_test01_testbench.SDDMU[0]
@22 @22
ddrc_test01_testbench.set_mrs.data[31:0] ddrc_test01_testbench.SDD[15:0]
ddrc_test01_testbench.set_mrs.cmd_addr[31:0]
ddrc_test01_testbench.set_mrs.data[31:0]
ddrc_test01_testbench.set_mrs.mr0[17:0]
ddrc_test01_testbench.set_mrs.mr1[17:0]
ddrc_test01_testbench.set_mrs.mr2[17:0]
ddrc_test01_testbench.set_mrs.mr3[17:0]
@28 @28
ddrc_test01_testbench.set_mrs.reset_dll[0] ddrc_test01_testbench.SDODT[0]
ddrc_test01_testbench.SDRST[0]
@200
-
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_rd[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_page[1:0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_raddr[8:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_rdata[63:0]
@800200
-port1_wr
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_data[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_addr[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_page[1:0]
@29
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_we[0]
@1000200
-port1_wr
-write_block
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
ddrc_test01_testbench.tf
View file @ 4bacb90a
...@@ -43,8 +43,8 @@ module ddrc_test01_testbench #( ...@@ -43,8 +43,8 @@ module ddrc_test01_testbench #(
parameter SS_EN = "FALSE", parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH", parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000, parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 6, parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 6, parameter CMD_DONE_BIT= 10,
parameter AXI_WR_ADDR_BITS = 13, parameter AXI_WR_ADDR_BITS = 13,
parameter AXI_RD_ADDR_BITS = 13, parameter AXI_RD_ADDR_BITS = 13,
parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
...@@ -94,6 +94,51 @@ module ddrc_test01_testbench #( ...@@ -94,6 +94,51 @@ module ddrc_test01_testbench #(
parameter lxtname = "x393.lxt"; parameter lxtname = "x393.lxt";
`endif `endif
`define DEBUG_WR_SINGLE 1 `define DEBUG_WR_SINGLE 1
// SuppressWarnings VEditor
localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000 << 2
// SuppressWarnings VEditor
localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
localparam BASEADDR_CMD0 = CMD0_ADDR << 2; // 'h0800 << 2 = 'h2000
// localparam BASEADDR_CTRL = CONTROL_ADDR << 2;
localparam BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
localparam BASEADDR_STATUS = STATUS_ADDR << 2; // 'h0800 << 2 = 'h2000
localparam BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2); // 'h080, address to generate delay load
localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2); // 'h070, address to generate delay set
localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2); // 'h000, address to set sequnecer channel and run (4 LSB-s - channel)
// S uppressWarnings VEditor
localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
// SuppressWarnings VEditor
localparam BASEADDR_PAGES = BASEADDR_CTRL | (PAGES_REL<<2); // 'h021, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2); // 'h022, address to enable('h823)/disable('h822) command/address outputs
localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory
localparam BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2); //
// SuppressWarnings VEditor
localparam BASEADDR_EXTRA = BASEADDR_CTRL | (EXTRA_REL<<2); // 'h028, address to set extra parameters (currently just inv_clk_div)
localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;
localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);
localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);
localparam BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+('h30<<2);
localparam BASEADDRESS_CMDA = BASEADDR_DLY_LD+('h40<<2);
localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
localparam STATUS_PSHIFTER_RDY_MASK = 'h100;
// SuppressWarnings VEditor - not yet used
localparam STATUS_LOCKED_MASK = 'h200;
localparam STATUS_SEQ_BUSY_MASK = 'h400;
localparam DLY_LANE0_ODELAY= 80'h7574737271706f6e6d6c; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE0_IDELAY= 72'h74737271706f6e6d6c; // idelay dqs, idelay dq[7:0
localparam DLY_LANE1_ODELAY= 80'h7574737271706f6e6d6c; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'h74737271706f6e6d6c; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h5f5e5d5c5b5a59585756555453525150004e4b4c4b4a49484746454443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
localparam WRITELEV_OFFSET='h20; // write leveling start address (in words)
localparam WRITE_BLOCK_OFFSET='h100; // write block sequence start address (in words)
// DDR3 signals // DDR3 signals
wire SDRST; wire SDRST;
wire SDCLK; // output wire SDCLK; // output
...@@ -253,16 +298,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -253,16 +298,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
axi_set_b_lag(0); //(1); axi_set_b_lag(0); //(1);
axi_set_rd_lag(0); axi_set_rd_lag(0);
axi_set_delays; axi_set_delays;
// write memory
// test_axi_1;
// read memory
// test_axi_2;
read_status; // ps ready goes false with some delay read_status; // ps ready goes false with some delay
// read_status;
wait_phase_shifter_ready; wait_phase_shifter_ready;
// repeat (40) begin
// read_status;
// end
enable_cmda(1); enable_cmda(1);
repeat (16) @(posedge CLK) ; repeat (16) @(posedge CLK) ;
activate_sdrst(0); // was enabled at system reset activate_sdrst(0); // was enabled at system reset
...@@ -271,10 +308,38 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -271,10 +308,38 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
enable_cke(1); enable_cke(1);
repeat (16) @(posedge CLK) ; repeat (16) @(posedge CLK) ;
set_mrs(1); set_mrs(1);
set_write_lev(16); // write leveling, 16 times
#100; #100;
// $finish; // $finish;
run_sequence(0); run_sequence(0,0);
//#100; wait_sequencer_ready(16);
axi_write_single(BASEADDR_PATTERNS, 32'h0055); // set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
run_sequence(0,WRITELEV_OFFSET);
wait_sequencer_ready(16);
axi_set_dly_single(0,8,'h80); // was 'h74 dqs lane 0, odelay
axi_set_dly_single(2,8,'hc0); // was 'h74 dqs lane 1, odelay
run_sequence(0,WRITELEV_OFFSET);
#140; // 140 ns delay 30; // 30 ns delay
axi_set_dly_single(2,8,'hb8); // was 'h74 dqs lane 1, odelay
#20
axi_set_dly_single(0,8,'hc0); // was 'h74 dqs lane 0, odelay
wait_sequencer_ready(16);
// test write block;
write_block_buf; // fill block memory
set_write_block(
3'h5, // bank
15'h1234, // row address
10'h100 // column address
);
run_sequence(1,WRITE_BLOCK_OFFSET);
wait_sequencer_ready(16);
#100;
$display("finish testbench 0"); $display("finish testbench 0");
$finish; $finish;
...@@ -289,7 +354,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -289,7 +354,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
// protect from never end // protect from never end
initial begin initial begin
// #10000000; // #10000000;
#110000; #150000;
$display("finish testbench 2"); $display("finish testbench 2");
$finish; $finish;
end end
...@@ -740,49 +805,17 @@ simul_axi_read simul_axi_read_i( ...@@ -740,49 +805,17 @@ simul_axi_read simul_axi_read_i(
// top simulation tasks // top simulation tasks
// base addresses // base addresses
// SuppressWarnings VEditor
localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000 << 2
// SuppressWarnings VEditor
localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
localparam BASEADDR_CMD0 = CMD0_ADDR << 2; // 'h0800 << 2 = 'h2000
// localparam BASEADDR_CTRL = CONTROL_ADDR << 2;
localparam BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
localparam BASEADDR_STATUS = STATUS_ADDR << 2; // 'h0800 << 2 = 'h2000
localparam BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2); // 'h080, address to generate delay load
localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2); // 'h070, address to generate delay set
localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2); // 'h000, address to set sequnecer channel and run (4 LSB-s - channel)
// SuppressWarnings VEditor
localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
// SuppressWarnings VEditor
localparam BASEADDR_PAGES = BASEADDR_CTRL | (PAGES_REL<<2); // 'h021, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2); // 'h022, address to enable('h823)/disable('h822) command/address outputs
localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory
localparam BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2); //
// SuppressWarnings VEditor
localparam BASEADDR_EXTRA = BASEADDR_CTRL | (EXTRA_REL<<2); // 'h028, address to set extra parameters (currently just inv_clk_div)
localparam BASEADDRESS_LANE0 = BASEADDR_DLY_LD;
localparam BASEADDRESS_LANE1 = BASEADDR_DLY_LD+('h20<<2);
localparam BASEADDRESS_CMDA = BASEADDR_DLY_LD+('h40<<2);
localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
localparam PSHIFTER_RDY_MASK = 'h100;
localparam DLY_LANE0= 152'h74737271706f6e6d6c7574737271706f6e6d6c; // idelay dqs, idelay dq[7:0, odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1= 152'h74737271706f6e6d6c7574737271706f6e6d6c; // idelay dqs, idelay dq[7:0, odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_CMDA= 256'h5f5e5d5c5b5a59585756555453525150004e4b4c4b4a49484746454443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// localparam DLY_PHASE= 8'h25; // mmcm fine phase shift
localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
task run_sequence; task run_sequence;
input [7:0] start_addr; // word input [3:0] channel;
input [10:0] start_addr; // word
// BASEADDR_RUN_CHN // BASEADDR_RUN_CHN
begin begin
$display("run_sequence 0 @ %t",$time); $display("run_sequence(%x,%x) 0 @ %t",channel,start_addr,$time);
axi_write_single(BASEADDR_RUN_CHN, {24'h0,start_addr}); axi_write_single(BASEADDR_RUN_CHN+{26'h0,channel,2'h0}, {21'h0,start_addr});
$display("run_sequence 1 @ %t",$time); $display("run_sequence(%x,%x) 2 @ %t",channel,start_addr,$time);
#1000; // 90; // 92 - does not work ? // #1000; // 90; // 92 - does not work ?
$display("run_sequence 2 @ %t",$time); // $display("run_sequence(%x,%x) 2 @ %t",channel,start_addr,$time);
end end
endtask endtask
task enable_cmda; task enable_cmda;
...@@ -816,7 +849,377 @@ simul_axi_read simul_axi_read_i( ...@@ -816,7 +849,377 @@ simul_axi_read simul_axi_read_i(
end end
endtask endtask
task set_mrs; task write_block_buf;
integer i,j;
begin
for (i=0;i<256;i=i+16) begin
axi_write_addr_data(
i, // id
BASEADDR_PORT1_WR+ (i<<2), // addr
i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24),
4'hf, // len
1, // burst type - increment
1'b1, // data_en
4'hf, // wstrb
1'b0 // last
);
for (j=1;j<16;j=j+1) begin
axi_write_data(
i, // id
(i+j) | ((((i+j) + 7) & 'hff) << 8) | ((((i+j) + 23) & 'hff) << 16) | ((((i+j) + 31) & 'hff) << 24),
4'hf, // wstrb
(1==15)?1:0 // last
);
end
end
end
endtask
task set_write_block;
input [ 2:0] ba;
input [14:0] ra;
input [ 9:0] ca;
reg [31:0] cmd_addr;
reg [31:0] data;
integer i;
begin
cmd_addr <= BASEADDR_CMD0 + (WRITE_BLOCK_OFFSET << 2);
// activate
data <= {
ra[14:0],
ba[2:0], //phy_bank_in[2:0],
3'b100, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// see if pause is needed . See when buffer read should be started - maybe before WR command
data <= encode_seq_skip(1,0); // tRCD
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// first write
// write
data <= {
{5'b0,ca[9:0]},
ba[2:0], //phy_bank_in[2:0],
3'b011, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b1, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// nop
data <= {
15'b0, // skip 0
ba[2:0], //phy_bank_in[2:0],
3'b000, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b1, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b1, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
//repeat remaining writes
for (i=1;i<64;i=i+1) begin
// write
data <= {
{5'b0,ca[9:0]} + (i<<3),
ba[2:0], //phy_bank_in[2:0],
3'b011, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b1, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b1, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b1, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// nop
data <= {
15'b0, // skip 0
ba[2:0], //phy_bank_in[2:0],
3'b000, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b1, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b1, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
end
// nop
data <= {
15'b0, // skip 0
ba[2:0], //phy_bank_in[2:0],
3'b000, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b1, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b1, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// nop
data <= {
15'b0, // skip 0
ba[2:0], //phy_bank_in[2:0],
3'b000, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b1, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b1, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// nop
data <= {
15'b0, // skip 0
ba[2:0], //phy_bank_in[2:0],
3'b000, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b1, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(2,0); // tWR = 15ns (6 cycles for 2.5ns) from end of write (not write command)
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// precharge
data <= {
ra[14:0],
ba[2:0], //phy_bank_in[2:0],
3'b101, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(2,0); //
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(0,1); // end of sequence
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
end
endtask
task set_write_lev;
input [CMD_PAUSE_BITS-1:0] nrep;
reg [17:0] mr1_norm;
reg [17:0] mr1_wlev;
reg [31:0] cmd_addr;
reg [31:0] data;
reg [CMD_PAUSE_BITS-1:0] dqs_low_rpt;
begin
dqs_low_rpt <= 8;
mr1_norm <= ddr3_mr1 (
1'h0, // qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
1'h0, // tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
3'h2, // [2:0] rtt; // on-die termination resistance: // 3'b010 - RZQ/2 (120 Ohm)
1'h0, // wlev; // write leveling
2'h0, // ods; // output drive strength: // 2'b00 - RZQ/6 - 40 Ohm
2'h0, // [1:0] al; // additive latency: 2'b00 - disabled (AL=0)
1'b0); // dll; // 0 - DLL enabled (normal), 1 - DLL disabled
mr1_wlev <= ddr3_mr1 (
1'h0, // qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
1'h0, // tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
3'h2, // [2:0] rtt; // on-die termination resistance: // 3'b010 - RZQ/2 (120 Ohm)
1'h1, // wlev; // write leveling
2'h0, // ods; // output drive strength: // 2'b00 - RZQ/6 - 40 Ohm
2'h0, // [1:0] al; // additive latency: 2'b00 - disabled (AL=0)
1'b0); // dll; // 0 - DLL enabled (normal), 1 - DLL disabled
cmd_addr <= BASEADDR_CMD0 + (WRITELEV_OFFSET<<2);
// Enter write leveling mode
@(posedge CLK)
data <= encode_seq_word(
mr1_wlev[14:0], // [14:0] phy_addr_in;
mr1_wlev[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
3'b111, // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
1'b0, // phy_odt_in; // may be optimized?
1'b0, // phy_cke_inv; // may be optimized?
1'b0, // phy_sel_in == 0; // first/second half-cycle,
1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer
1'b0); // phy_buf_rd; // connect to external buffer
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(13,0); // tWLDQSEN=25tCK
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// enable DQS output, keep it low (15 more tCK for the total of 40 tCK
data <= { // encode_seq_skip(nrep,0); // Adjust skip
{15-CMD_DONE_BIT{1'b0}},
dqs_low_rpt, // 16 tCK
3'b0, //phy_bank_in[2:0],
3'b0, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// data <= encode_seq_skip(2,0); // Adjust skip
// @(posedge CLK)
// axi_write_single(cmd_addr, data);
// cmd_addr <= cmd_addr + 4;
// Toggle DQS as needed for write leveling
data <= { // encode_seq_skip(nrep,0); // Adjust skip
{15-CMD_DONE_BIT{1'b0}},
nrep[CMD_PAUSE_BITS-1:0],
3'b0, //phy_bank_in[2:0],
3'b0, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_inv, // may be optimized?
1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_en_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b1, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
2'h0 // Reserved for future use
};
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(2,0); // Adjust skip
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// exit write leveling mode
data <= encode_seq_word(
mr1_norm[14:0], // [14:0] phy_addr_in;
mr1_norm[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
3'b111, // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
1'b0, // phy_odt_in; // may be optimized?
1'b0, // phy_cke_inv; // may be optimized?
1'b0, // phy_sel_in == 0; // first/second half-cycle,
1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer
1'b0); // phy_buf_rd; // connect to external buffer
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(5,0); // tMOD
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// Ready for normal operation
data <= encode_seq_skip(10,1); // sequence done bit, skip length is ignored
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
end
endtask
task set_mrs; // will also calibrate ZQ
input reset_dll; input reset_dll;
// reg [ADDRESS_NUMBER+2:0] mr0; // reg [ADDRESS_NUMBER+2:0] mr0;
// reg [ADDRESS_NUMBER+2:0] mr1; // reg [ADDRESS_NUMBER+2:0] mr1;
...@@ -833,8 +1236,8 @@ simul_axi_read simul_axi_read_i( ...@@ -833,8 +1236,8 @@ simul_axi_read simul_axi_read_i(
1'h0, // pd; // precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit) 1'h0, // pd; // precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit)
3'h2, // [2:0] wr; // write recovery (encode ceil(tWR/tCK)) // 3'b010: 6 3'h2, // [2:0] wr; // write recovery (encode ceil(tWR/tCK)) // 3'b010: 6
reset_dll, // dll_rst; // 1 - dll reset (self clearing bit) reset_dll, // dll_rst; // 1 - dll reset (self clearing bit)
4'h2, // [3:0] cl; // CAS latency: // 0010: 5 4'h4, // [3:0] cl; // CAS latency: // 0100: 6 (time 15ns)
1'h0, // bt; // read burst type: 0 sequential (nibble), 1 - interleaverun_seqd 1'h0, // bt; // read burst type: 0 sequential (nibble), 1 - interleave
2'h0); // [1:0] bl; // burst length: // 2'b00 - fixed BL8 2'h0); // [1:0] bl; // burst length: // 2'b00 - fixed BL8
mr1 <= ddr3_mr1 ( mr1 <= ddr3_mr1 (
...@@ -856,7 +1259,7 @@ simul_axi_read simul_axi_read_i( ...@@ -856,7 +1259,7 @@ simul_axi_read simul_axi_read_i(
1'h0, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR 1'h0, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR
2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101... 2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101...
cmd_addr <= BASEADDR_CMD0; cmd_addr <= BASEADDR_CMD0;
wait (~CLK); @(posedge CLK)
data <= encode_seq_word( data <= encode_seq_word(
mr2[14:0], // [14:0] phy_addr_in; mr2[14:0], // [14:0] phy_addr_in;
mr2[17:15], // [ 2:0] phy_bank_in; //TODO: debug! mr2[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
...@@ -865,20 +1268,18 @@ simul_axi_read simul_axi_read_i( ...@@ -865,20 +1268,18 @@ simul_axi_read simul_axi_read_i(
1'b0, // phy_cke_inv; // may be optimized? 1'b0, // phy_cke_inv; // may be optimized?
1'b0, // phy_sel_in; // first/second half-cycle, oter will be nop (cke+odt applicable to both) 1'b0, // phy_sel_in; // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in; 1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_ddrc_sequenceren_in; 1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer 1'b0, // phy_buf_wr; // connect to external buffer
1'b0); // phy_buf_rd; // connect to external buffer 1'b0); // phy_buf_rd; // connect to external buffer
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK);
// data <= encode_seq_skip(2,0);
data <= encode_seq_skip(1,0); // 6 cycles between mrs commands data <= encode_seq_skip(1,0); // 6 cycles between mrs commands
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK);
data <= encode_seq_word( data <= encode_seq_word(
mr3[14:0], // [14:0] phy_addr_in; mr3[14:0], // [14:0] phy_addr_in;
mr3[17:15], // [ 2:0] phy_bank_in; //TODO: debug! mr3[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
...@@ -886,22 +1287,21 @@ simul_axi_read simul_axi_read_i( ...@@ -886,22 +1287,21 @@ simul_axi_read simul_axi_read_i(
1'b0, // phy_odt_in; // may be optimized? 1'b0, // phy_odt_in; // may be optimized?
1'b0, // phy_cke_inv; // may be optimized? 1'b0, // phy_cke_inv; // may be optimized?
1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both) 1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
1'b0, // phy_dq_eddrc_sequencern_in; 1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in; 1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer 1'b0, // phy_buf_wr; // connect to external buffer
1'b0); // phy_buf_rd; // connect to external buffer 1'b0); // phy_buf_rd; // connect to external buffer
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK); // TODO: function - does not check arguments number
// data <= encode_seq_skip(2,0); // TODO: function - does not check arguments number
data <= encode_seq_skip(0,0); // 5 cycles between mrs commands (next command has phy_sel_in == 1) data <= encode_seq_skip(0,0); // 5 cycles between mrs commands (next command has phy_sel_in == 1)
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK);
data <= encode_seq_word( data <= encode_seq_word(
mr1[14:0], // [14:0] phy_addr_in; mr1[14:0], // [14:0] phy_addr_in;
mr1[17:15], // [ 2:0] phy_bank_in; //TODO: debug! mr1[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
...@@ -911,19 +1311,18 @@ simul_axi_read simul_axi_read_i( ...@@ -911,19 +1311,18 @@ simul_axi_read simul_axi_read_i(
1'b1, // phy_sel_in == 1 (test); // first/second half-cycle, 1'b1, // phy_sel_in == 1 (test); // first/second half-cycle,
1'b0, // phy_dq_en_in; 1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in; 1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer 1'b0, // phy_buf_wr; // connect to external buffer
1'b0); // phy_buf_rd; // connect to external buffer 1'b0); // phy_buf_rd; // connect to external buffer
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK);
data <= encode_seq_skip(2,0); // 7 cycles between mrs commands ( prev. command had phy_sel_in == 1) data <= encode_seq_skip(2,0); // 7 cycles between mrs commands ( prev. command had phy_sel_in == 1)
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK);
data <= encode_seq_word( data <= encode_seq_word(
mr0[14:0], // [14:0] phy_addr_in; mr0[14:0], // [14:0] phy_addr_in;
mr0[17:15], // [ 2:0] phy_bank_in; //TODO: debug! mr0[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
...@@ -933,21 +1332,50 @@ simul_axi_read simul_axi_read_i( ...@@ -933,21 +1332,50 @@ simul_axi_read simul_axi_read_i(
1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both) 1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in; 1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in; 1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer 1'b0, // phy_buf_wr; // connect to external buffer
1'b0); // phy_buf_rd; // connect to external buffer 1'b0); // phy_buf_rd; // connect to external buffer
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
wait (~CLK); data <= encode_seq_skip(5,0); // tMOD = 12 CK or 15ns, (tMOD/2)-1
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_word(
15'h400, // A10 == 1 -> ZQCL
3'h0, // phy_bank_in;
3'b001, // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive - ZQC?
1'b0, // phy_odt_in; // may be optimized?
1'b0, // phy_cke_inv; // may be optimized?
1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr;
1'b0); // phy_buf_rd;
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
data <= encode_seq_skip(256,0); // 512 clock cycles after ZQCL
@(posedge CLK)
axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4;
// Ready for normal operation
data <= encode_seq_skip(10,1); // sequence done bit, skip length is ignored data <= encode_seq_skip(10,1); // sequence done bit, skip length is ignored
wait (CLK); @(posedge CLK)
axi_write_single(cmd_addr, data); axi_write_single(cmd_addr, data);
cmd_addr <= cmd_addr + 4; cmd_addr <= cmd_addr + 4;
// TODO: Function of function does not work - debug // TODO: Function of function does not work - debug
/* /*
axi_write_single(cmd_addr, axi_write_single(cmd_addr,
...@@ -960,11 +1388,13 @@ simul_axi_read simul_axi_read_i( ...@@ -960,11 +1388,13 @@ simul_axi_read simul_axi_read_i(
1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both) 1'b0, // phy_sel_in; // first/second half-cycle, other will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in; 1'b0, // phy_dq_en_in;
1'b0, // phy_dqs_en_in; 1'b0, // phy_dqs_en_in;
1'b0, // phy_dqs_toggle_en;
1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 1'b0, // phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr; // connect to external buffer 1'b0, // phy_buf_wr; // connect to external buffer
1'b0)); // phy_buf_rd; // connect to external buffer 1'b0)); // phy_buf_rd; // connect to external buffer
*/ */
end end
endtask endtask
...@@ -974,9 +1404,10 @@ simul_axi_read simul_axi_read_i( ...@@ -974,9 +1404,10 @@ simul_axi_read simul_axi_read_i(
input [ 2:0] phy_rcw_in; // {ras,cas,we} input [ 2:0] phy_rcw_in; // {ras,cas,we}
input phy_odt_in; // may be optimized? input phy_odt_in; // may be optimized?
input phy_cke_inv; // invert CKE input phy_cke_inv; // invert CKE
input phy_sel_in; // fitst/second half-cycle, oter will be nop (cke+odt applicable to both) input phy_sel_in; // first/second half-cycle, oter will be nop (cke+odt applicable to both)
input phy_dq_en_in; input phy_dq_en_in;
input phy_dqs_en_in; input phy_dqs_en_in;
input phy_dqs_toggle_en;//enable toggle DQS according to the pattern
input phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) input phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input phy_buf_wr; // connect to external buffer input phy_buf_wr; // connect to external buffer
input phy_buf_rd; // connect to external buffer input phy_buf_rd; // connect to external buffer
...@@ -990,10 +1421,11 @@ simul_axi_read simul_axi_read_i( ...@@ -990,10 +1421,11 @@ simul_axi_read simul_axi_read_i(
phy_sel_in, // first/second half-cycle, other will be nop (cke+odt applicable to both) phy_sel_in, // first/second half-cycle, other will be nop (cke+odt applicable to both)
phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_en,//enable toggle DQS according to the pattern
phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr, // connect to external buffer (but only if not paused) phy_buf_wr, // connect to external buffer (but only if not paused)
phy_buf_rd, // connect to external buffer (but only if not paused) phy_buf_rd, // connect to external buffer (but only if not paused)
3'h0 // Reserved for future use 2'h0 // Reserved for future use
}; };
end end
endfunction endfunction
...@@ -1012,13 +1444,14 @@ simul_axi_read simul_axi_read_i( ...@@ -1012,13 +1444,14 @@ simul_axi_read simul_axi_read_i(
3'b0, // phy_rcw_in[2:0], // {ras,cas,we} 3'b0, // phy_rcw_in[2:0], // {ras,cas,we}
1'b0, // phy_odt_in, // may be optimized? 1'b0, // phy_odt_in, // may be optimized?
1'b0, // phy_cke_in, // may be optimized? 1'b0, // phy_cke_in, // may be optimized?
1'b0, // phy_sel_in, // fitst/second half-cycle, oter will be nop (cke+odt applicable to both) 1'b0, // phy_sel_in, // first/second half-cycle, oter will be nop (cke+odt applicable to both)
1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) 1'b0, // phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
1'b0, // phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) 1'b0, // phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
1'b0, //enable toggle DQS according to the pattern
1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 1'b0, // phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused) 1'b0, // phy_buf_wr, // connect to external buffer (but only if not paused)
1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused) 1'b0, // phy_buf_rd, // connect to external buffer (but only if not paused)
3'h0 // Reserved for future use 2'h0 // Reserved for future use
}; };
end end
...@@ -1038,7 +1471,7 @@ simul_axi_read simul_axi_read_i( ...@@ -1038,7 +1471,7 @@ simul_axi_read simul_axi_read_i(
// 3'b110: 12 // 3'b110: 12
// 3'b111: 14 // 3'b111: 14
input dll_rst; // 1 - dll reset (self clearing bit) input dll_rst; // 1 - dll reset (self clearing bit)
input [3:0] cl; // CAS latency: input [3:0] cl; // CAS latency (>=15ns):
// 0000: reserved // 0000: reserved
// 0010: 5 // 0010: 5
// 0100: 6 // 0100: 6
...@@ -1163,11 +1596,17 @@ simul_axi_read simul_axi_read_i( ...@@ -1163,11 +1596,17 @@ simul_axi_read simul_axi_read_i(
task axi_set_delays; task axi_set_delays;
integer i; integer i;
begin begin
for (i=0;i<19;i=i+1) begin for (i=0;i<10;i=i+1) begin
axi_write_single(BASEADDRESS_LANE0 + (i<<2), (DLY_LANE0 >> (i<<3)) & 32'hff); axi_write_single(BASEADDRESS_LANE0_ODELAY + (i<<2), (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<9;i=i+1) begin
axi_write_single(BASEADDRESS_LANE0_IDELAY + (i<<2), (DLY_LANE0_IDELAY >> (i<<3)) & 32'hff);
end end
for (i=0;i<19;i=i+1) begin for (i=0;i<10;i=i+1) begin
axi_write_single(BASEADDRESS_LANE1 + (i<<2), (DLY_LANE1 >> (i<<3)) & 32'hff); axi_write_single(BASEADDRESS_LANE1_ODELAY + (i<<2), (DLY_LANE1_ODELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<9;i=i+1) begin
axi_write_single(BASEADDRESS_LANE1_IDELAY + (i<<2), (DLY_LANE1_IDELAY >> (i<<3)) & 32'hff);
end end
for (i=0;i<32;i=i+1) begin for (i=0;i<32;i=i+1) begin
axi_write_single(BASEADDRESS_CMDA + (i<<2), (DLY_CMDA >> (i<<3)) & 32'hff); axi_write_single(BASEADDRESS_CMDA + (i<<2), (DLY_CMDA >> (i<<3)) & 32'hff);
...@@ -1178,6 +1617,35 @@ simul_axi_read simul_axi_read_i( ...@@ -1178,6 +1617,35 @@ simul_axi_read simul_axi_read_i(
end end
endtask endtask
task axi_set_dly_single;
input [2:0] group; // 0 - lane 0 odelay, 1 - lane0 idelay, 2 - lane 1 odelay, 3 - lane1 idelay, 4 - cmda odelay
input [4:0] index; // 0..7 - DQ, 8 - DQS, 9 DQM (for byte lanes)
input [7:0] delay;
integer i;
integer dly;
begin
i = index;
dly=delay;
if (group == 0) begin
axi_write_single(BASEADDRESS_LANE0_ODELAY + (i<<2), dly & 32'hff);
end else if (group == 1) begin
axi_write_single(BASEADDRESS_LANE0_IDELAY + (i<<2), dly & 32'hff);
end else if (group == 2) begin
axi_write_single(BASEADDRESS_LANE1_ODELAY + (i<<2), dly & 32'hff);
end else if (group == 3) begin
axi_write_single(BASEADDRESS_LANE1_IDELAY + (i<<2), dly & 32'hff);
end else if (group == 4) begin
axi_write_single(BASEADDRESS_CMDA + (i<<2), dly & 32'hff);
end
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays - remove after fixed axi_set_phase
end
endtask
task axi_set_phase; task axi_set_phase;
input [PHASE_WIDTH-1:0] phase; input [PHASE_WIDTH-1:0] phase;
begin begin
...@@ -1191,7 +1659,17 @@ simul_axi_read simul_axi_read_i( ...@@ -1191,7 +1659,17 @@ simul_axi_read simul_axi_read_i(
task wait_phase_shifter_ready; task wait_phase_shifter_ready;
begin begin
read_status; read_status;
while (((registered_rdata & PSHIFTER_RDY_MASK) == 0) || (((registered_rdata ^ {24'h0,target_phase}) & 'hff) != 0)) read_status; while (((registered_rdata & STATUS_PSHIFTER_RDY_MASK) == 0) || (((registered_rdata ^ {24'h0,target_phase}) & 'hff) != 0)) read_status;
end
endtask
task wait_sequencer_ready;
input integer num_skip; //skip this cycles before testing ready (latency from write to busy)
begin
repeat (num_skip) @(posedge CLK);
read_status;
repeat (8) @(posedge CLK); // latency from read command to registered_rdata. TODO: make it certain (read with the same ID)
while ((registered_rdata & STATUS_SEQ_BUSY_MASK) != 0) read_status;
end end
endtask endtask
...@@ -1290,6 +1768,7 @@ simul_axi_read simul_axi_read_i( ...@@ -1290,6 +1768,7 @@ simul_axi_read simul_axi_read_i(
1'b1 // last 1'b1 // last
); );
GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1; GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
#0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
end end
endtask endtask
...@@ -1364,7 +1843,7 @@ simul_axi_read simul_axi_read_i( ...@@ -1364,7 +1843,7 @@ simul_axi_read simul_axi_read_i(
#0.1; #0.1;
end end
endtask endtask
// SuppressWarnings VEditor - not yet used
task axi_write_data; task axi_write_data;
input [11:0] id; input [11:0] id;
input [31:0] data; input [31:0] data;
......
phy/ddrc_sequencer.v
View file @ 4bacb90a
...@@ -59,10 +59,10 @@ module ddrc_sequencer #( ...@@ -59,10 +59,10 @@ module ddrc_sequencer #(
output SDODT, // output ODT port output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads inout [15:0] SDD, // DQ I/O pads
inout SDDML, // LDM I/O pad (actually only output) output SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad inout NDQSL, // ~LDQS I/O pad
inout SDDMU, // UDM I/O pad (actually only output) output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU, // ~UDQS I/O pad inout NDQSU, // ~UDQS I/O pad
// clocks, reset // clocks, reset
...@@ -164,7 +164,8 @@ module ddrc_sequencer #( ...@@ -164,7 +164,8 @@ module ddrc_sequencer #(
always @ (posedge mclk or posedge rst) begin always @ (posedge mclk or posedge rst) begin
if (rst) cmd_busy <= 0; if (rst) cmd_busy <= 0;
else if (sequence_done) cmd_busy <= 0; // else if (sequence_done) cmd_busy <= 0;
else if (sequence_done && cmd_busy[2]) cmd_busy <= 0;
else cmd_busy <= {cmd_busy[1:0],run_seq | cmd_busy[0]}; else cmd_busy <= {cmd_busy[1:0],run_seq | cmd_busy[0]};
// Pause counter // Pause counter
if (rst) pause_cntr <= 0; if (rst) pause_cntr <= 0;
...@@ -213,7 +214,7 @@ module ddrc_sequencer #( ...@@ -213,7 +214,7 @@ module ddrc_sequencer #(
else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge
if (rst) run_chn_d <= 0; if (rst) run_chn_d <= 0;
else run_chn_d <= run_chn; else if (run_seq) run_chn_d <= run_chn;
if (rst) run_seq_d <= 0; if (rst) run_seq_d <= 0;
else run_seq_d <= run_seq; else run_seq_d <= run_seq;
......
phy/phy_cmd.v
View file @ 4bacb90a
...@@ -45,8 +45,8 @@ module phy_cmd#( ...@@ -45,8 +45,8 @@ module phy_cmd#(
parameter SS_EN = "FALSE", parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH", parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000, parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 6, // numer of (address) bits to encode pause parameter CMD_PAUSE_BITS= 10, // numer of (address) bits to encode pause
parameter CMD_DONE_BIT= 6 // bit number (address) to signal sequence done parameter CMD_DONE_BIT= 10 // bit number (address) to signal sequence done
)( )(
// DDR3 interface // DDR3 interface
output SDRST, // DDR3 reset (active low) output SDRST, // DDR3 reset (active low)
...@@ -61,10 +61,10 @@ module phy_cmd#( ...@@ -61,10 +61,10 @@ module phy_cmd#(
output SDODT, // output ODT port output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads inout [15:0] SDD, // DQ I/O pads
inout SDDML, // LDM I/O pad (actually only output) output SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad inout NDQSL, // ~LDQS I/O pad
inout SDDMU, // UDM I/O pad (actually only output) output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU, // ~UDQS I/O pad inout NDQSU, // ~UDQS I/O pad
// clocks, reset // clocks, reset
...@@ -121,6 +121,7 @@ module phy_cmd#( ...@@ -121,6 +121,7 @@ module phy_cmd#(
wire phy_dqs_tri_in; // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) wire phy_dqs_tri_in; // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
wire phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) wire phy_dci_en_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
wire phy_dci_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) wire phy_dci_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
wire phy_dqs_toggle_en; //enable toggle DQS according to the pattern
wire phy_buf_wr; // connect to extrenal buffer wire phy_buf_wr; // connect to extrenal buffer
wire phy_buf_rd; // connect to extrenal buffer wire phy_buf_rd; // connect to extrenal buffer
wire cmda_tri; wire cmda_tri;
...@@ -152,9 +153,14 @@ module phy_cmd#( ...@@ -152,9 +153,14 @@ module phy_cmd#(
reg [PHASE_WIDTH-1:0] ps_out_r1,ps_out_r2; reg [PHASE_WIDTH-1:0] ps_out_r1,ps_out_r2;
wire [63:0] phy_rdata; // data read from ddr3 iserdese2 at posedge clk_div wire [63:0] phy_rdata; // data read from ddr3 iserdese2 at posedge clk_div
reg [63:0] phy_rdata_r; // registered @ posedge mclk reg [63:0] phy_rdata_r; // registered @ posedge mclk
reg [ADDRESS_NUMBER-1:0] phy_addr_prev;
reg [ 2:0] phy_bank_prev;
wire [ADDRESS_NUMBER-1:0] phy_addr_calm;
wire [ 2:0] phy_bank_calm;
// output [63:0] buf_wdata, // data to be written to the buffer (from DDR3) // output [63:0] buf_wdata, // data to be written to the buffer (from DDR3)
// SuppressWarnings VEditor // SuppressWarnings VEditor
(* keep = "true" *) wire [2:0] phy_spare; (* keep = "true" *) wire [1:0] phy_spare;
assign { assign {
phy_addr_in, phy_addr_in,
phy_bank_in, phy_bank_in,
...@@ -164,6 +170,7 @@ module phy_cmd#( ...@@ -164,6 +170,7 @@ module phy_cmd#(
phy_sel_in, // fitst/second half-cycle, oter will be nop (cke+odt applicable to both) phy_sel_in, // fitst/second half-cycle, oter will be nop (cke+odt applicable to both)
phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_en, //enable toggle DQS according to the pattern
phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
// phy_buf_addr, // connect to external buffer (is it needed? maybe just autoincrement?) // phy_buf_addr, // connect to external buffer (is it needed? maybe just autoincrement?)
phy_buf_wr, // connect to external buffer (but only if not paused) phy_buf_wr, // connect to external buffer (but only if not paused)
...@@ -179,12 +186,16 @@ module phy_cmd#( ...@@ -179,12 +186,16 @@ module phy_cmd#(
assign sequence_done= phy_cmd_nop && phy_addr_in[CMD_DONE_BIT]; assign sequence_done= phy_cmd_nop && phy_addr_in[CMD_DONE_BIT];
assign pause_len= phy_addr_in[CMD_PAUSE_BITS-1:0]; assign pause_len= phy_addr_in[CMD_PAUSE_BITS-1:0];
assign phy_addr_calm= phy_cmd_nop ? phy_addr_prev : phy_addr_in;
assign phy_bank_calm= phy_cmd_nop ? phy_bank_prev : phy_bank_in;
// assign buf_addr = phy_buf_addr; // assign buf_addr = phy_buf_addr;
assign buf_wr = phy_buf_wr; assign buf_wr = phy_buf_wr;
assign buf_rd = phy_buf_rd; assign buf_rd = phy_buf_rd;
assign phy_addr= {phy_addr_in,phy_addr_in}; // also provides pause length when the command is NOP // assign phy_addr= {phy_addr_in,phy_addr_in}; // also provides pause length when the command is NOP
assign phy_bank= {phy_bank_in,phy_bank_in}; // assign phy_bank= {phy_bank_in,phy_bank_in};
assign phy_addr= {phy_addr_calm,phy_addr_calm}; // also provides pause length when the command is NOP
assign phy_bank= {phy_bank_calm,phy_bank_calm};
assign phy_rcw= {phy_sel_in?phy_rcw_in:3'h7, phy_sel_in?3'h7:phy_rcw_in}; // {ras,cas,we} assign phy_rcw= {phy_sel_in?phy_rcw_in:3'h7, phy_sel_in?3'h7:phy_rcw_in}; // {ras,cas,we}
assign phy_odt= {phy_odt_in,phy_odt_in}; // may be optimized? assign phy_odt= {phy_odt_in,phy_odt_in}; // may be optimized?
assign phy_cke= {phy_cke_in,phy_cke_in}; // may be optimized? assign phy_cke= {phy_cke_in,phy_cke_in}; // may be optimized?
...@@ -211,6 +222,17 @@ module phy_cmd#( ...@@ -211,6 +222,17 @@ module phy_cmd#(
dq_tri_prev <= phy_dq_tri_in; dq_tri_prev <= phy_dq_tri_in;
end end
always @ (posedge mclk or posedge rst_in) begin
if (rst_in) begin
phy_addr_prev <= 0;
phy_bank_prev <= 0;
end else if (!phy_cmd_nop) begin
phy_addr_prev <= phy_addr_in;
phy_bank_prev <= phy_bank_in;
end
end
// cross clock boundary posedge mclk -> posedge clk_div (mclk is later than clk_div) // cross clock boundary posedge mclk -> posedge clk_div (mclk is later than clk_div)
always @ (posedge clk_div or posedge rst_in) begin always @ (posedge clk_div or posedge rst_in) begin
if (rst_in) begin if (rst_in) begin
...@@ -259,7 +281,8 @@ phy_rdata ...@@ -259,7 +281,8 @@ phy_rdata
*/ */
wire [7:0] dqs_data;
assign dqs_data=phy_dqs_toggle_en?dqs_pattern[7:0]:8'h0;
phy_top #( phy_top #(
.IOSTANDARD_DQ ("SSTL15_T_DCI"), .IOSTANDARD_DQ ("SSTL15_T_DCI"),
.IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"), .IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"),
...@@ -327,7 +350,7 @@ phy_rdata ...@@ -327,7 +350,7 @@ phy_rdata
.din (buf_rdata[63:0]), // input[63:0] .din (buf_rdata[63:0]), // input[63:0]
.din_dm (dqm_pattern[7:0]), // input[7:0] .din_dm (dqm_pattern[7:0]), // input[7:0]
.tin_dq (phy_dq_tri[7:0]), // input[7:0] .tin_dq (phy_dq_tri[7:0]), // input[7:0]
.din_dqs (dqs_pattern[7:0]), // input[7:0] .din_dqs (dqs_data), // input[7:0]
.tin_dqs (phy_dqs_tri[7:0]), // input[7:0] .tin_dqs (phy_dqs_tri[7:0]), // input[7:0]
.dout (phy_rdata[63:0]), // output[63:0] @posedge clk_div .dout (phy_rdata[63:0]), // output[63:0] @posedge clk_div
.inv_clk_div (inv_clk_div), // input .inv_clk_div (inv_clk_div), // input
......
phy/phy_top.v
View file @ 4bacb90a
...@@ -64,10 +64,10 @@ module phy_top #( ...@@ -64,10 +64,10 @@ module phy_top #(
output ddr3_odt, // output ODT port output ddr3_odt, // output ODT port
inout [15:0] dq, // DQ I/O pads inout [15:0] dq, // DQ I/O pads
inout dml, // LDM I/O pad (actually only output) output dml, // LDM I/O pad (actually only output)
inout dqsl, // LDQS I/O pad inout dqsl, // LDQS I/O pad
inout ndqsl, // ~LDQS I/O pad inout ndqsl, // ~LDQS I/O pad
inout dmu, // UDM I/O pad (actually only output) output dmu, // UDM I/O pad (actually only output)
inout dqsu, // UDQS I/O pad inout dqsu, // UDQS I/O pad
inout ndqsu, // ~UDQS I/O pad inout ndqsu, // ~UDQS I/O pad
......
phy/test_phy_top_01.v deleted 100644 → 0
View file @ 1b719ff1
/*******************************************************************************
* Module: test_phy_top_01
* Date:2014-05-14
* Author: Andrey Filippov
* Description: minimal instance of phy_top to test synthesis
*
* Copyright (c) 2014 Elphel, Inc.
* test_phy_top_01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* test_phy_top_01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module test_phy_top_01#(
parameter ADDRESS_NUMBER = 15,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKFBOUT_PHASE = 0.000,
parameter ICLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 0.000,
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000
)
(
output SDCLK, // DDR3 clock differential output, positive
output SDNCLK,// DDR3 clock differential output, negative
output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
output [2:0] SDBA, // output bank address ports
output SDWE, // output WE port
output SDRAS, // output RAS port
output SDCAS, // output CAS port
output SDCKE, // output Clock Enable port
output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads
inout SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad
inout SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad
inout NDQSU, // ~UDQS I/O pad
input clk_in, // master input clock, initially assuming 100MHz
input rst_in, // reset delays/serdes\
input fake_din,
input fake_en,
input fake_oe,
output fake_dout
);
// SuppressWarnings VEditor
(* keep = "true" *) wire clk; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire clk_div; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire mclk; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire [63:0] dout; // output[63:0]
// SuppressWarnings VEditor
(* keep = "true" *) wire locked; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire ps_rdy; // output
// SuppressWarnings VEditor
(* keep = "true" *) wire [7:0]ps_out;// output[7:0]
reg [2*ADDRESS_NUMBER-1:0] in_a; // input address, 2 bits per signal (first, second) (29:0) for 4Gb device
reg [5:0] in_ba; // input bank address, 2 bits per signal (first, second)
reg [1:0] in_we; // input WE, 2 bits (first, second)
reg [1:0] in_ras; // input RAS, 2 bits (first, second)
reg [1:0] in_cas; // input CAS, 2 bits (first, second)
reg [1:0] in_cke; // input CKE, 2 bits (first, second)
reg [1:0] in_odt; // input ODT, 2 bits (first, second)
// reg [1:0] in_tri; // tristate command/address outputs - same timing, but no odelay
reg in_tri; // tristate command/address outputs - same timing, but no odelay
reg [63:0] din; // parallel data to be sent out (4 bits per DG I/))
reg [7:0] din_dm; // parallel data to be sent out over DM
reg [7:0] tin_dq; // tristate for data out (sent out earlier than data!) and dm
reg [7:0] din_dqs; // parallel data to be sent out over DQS
reg [7:0] tin_dqs; // tristate for DQS out (sent out earlier than data!)
reg inv_clk_div; // invert clk_div for R channels (clk_div is shared between R and W)
reg dci_disable_dqs; // disable DCI termination during writes and idle for dqs
reg dci_disable_dq; // disable DCI termination during writes and idle for dq and dm signals
reg [7:0] dly_data; // delay value (3 LSB - fine delay)
reg [6:0] dly_addr; // select which delay to program
reg ld_delay; // load delay data to selected iodelayl (clk_div synchronous)
reg set; // clk_div synchronous set all delays from previously loaded values
reg [63:0] dout_r;
reg locked_r;
reg [ 7:0] ps_out_r;
// Create fake data sources for all input
assign fake_dout= locked_r;
always @ (posedge mclk) begin
if (!fake_oe) begin
dout_r <= dout;
locked_r <=locked;
ps_out_r <=ps_out;
end else if (fake_en) begin
{locked_r,dout_r,ps_out_r} <= {dout_r,ps_out_r,1'b0};
end
if (fake_en)
{
in_a,
in_ba,
in_we,
in_ras,
in_cas,
in_cke,
in_odt,
in_tri,
din,
din_dm,
tin_dq,
din_dqs,
tin_dqs,
inv_clk_div,
dci_disable_dqs,
dci_disable_dq,
dly_data,
dly_addr,
ld_delay,
set
} <= {
fake_din,
in_a,
in_ba,
in_we,
in_ras,
in_cas,
in_cke,
in_odt,
in_tri,
din,
din_dm,
tin_dq,
din_dqs,
tin_dqs,
inv_clk_div,
dci_disable_dqs,
dci_disable_dq,
dly_data,
dly_addr,
ld_delay
};
end
phy_top #(
.IOSTANDARD_DQ ("SSTL15_T_DCI"),
.IOSTANDARD_DQS ("DIFF_SSTL15_T_DCI"),
.IOSTANDARD_CMDA ("SSTL15"),
.IOSTANDARD_CLK ("DIFF_SSTL15"),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
.SLEW_CMDA (SLEW_CMDA),
.SLEW_CLK (SLEW_CLK),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IODELAY_GRP (IODELAY_GRP),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.PHASE_WIDTH (8),
.BANDWIDTH ("OPTIMIZED"),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.ICLK_PHASE (ICLK_PHASE),
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
.REF_JITTER1 (REF_JITTER1),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD)
) phy_top_i (
.ddr3_clk (SDCLK), // output
.ddr3_nclk (SDNCLK), // output
.ddr3_a (SDA[14:0]), // output[14:0]
.ddr3_ba (SDBA[2:0]), // output[2:0]
.ddr3_we (SDWE), // output
.ddr3_ras (SDRAS), // output
.ddr3_cas (SDCAS), // output
.ddr3_cke (SDCKE), // output
.ddr3_odt (SDODT), // output
.dq (SDD[15:0]), // inout[15:0]
.dml (SDDML), // inout
.dqsl (DQSL), // inout
.ndqsl (NDQSL), // inout
.dmu (SDDMU), // inout
.dqsu (DQSU), // inout
.ndqsu (NDQSU), // inout
.clk_in (clk_in), // input
.clk (clk), // output
.clk_div (clk_div), // output
.mclk (mclk), // output
.rst_in (rst_in), // input
.in_a (in_a), // input[29:0]
.in_ba (in_ba), // input[5:0]
.in_we (in_we), // input[1:0]
.in_ras (in_ras), // input[1:0]
.in_cas (in_cas), // input[1:0]
.in_cke (in_cke), // input[1:0]
.in_odt (in_odt), // input[1:0]
.in_tri (in_tri), // input[1:0]
.din (din), // input[63:0]
.din_dm (din_dm), // input[7:0]
.tin_dq (tin_dq), // input[7:0]
.din_dqs (din_dqs), // input[7:0]
.tin_dqs (tin_dqs), // input[7:0]
.dout (dout[63:0]), // output[63:0]
.inv_clk_div (inv_clk_div), // input
.dci_disable_dqs (dci_disable_dqs), // input
.dci_disable_dq (dci_disable_dq), // input
.dly_data (dly_data), // input[7:0]
.dly_addr (dly_addr), // input[6:0]
.ld_delay (ld_delay), // input
.set (set), // input
.locked (locked), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]) // output[7:0]
);
endmodule
util_modules/fifo_same_clock.v
View file @ 4bacb90a
...@@ -38,12 +38,13 @@ module fifo_same_clock ...@@ -38,12 +38,13 @@ module fifo_same_clock
); );
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1; localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
reg [DATA_DEPTH :0] fill=0; reg [DATA_DEPTH :0] fill=0;
reg just_one=0; reg just_one,two_or_less;
reg [DATA_WIDTH-1:0] inreg; reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg; reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra; reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa; reg [DATA_DEPTH-1:0] wa;
wire [DATA_DEPTH :0] next_fill; wire [DATA_DEPTH :0] next_fill;
wire outreg_use_inreg;
reg wem; reg wem;
wire rem; wire rem;
reg out_full=0; //output register full reg out_full=0; //output register full
...@@ -52,12 +53,13 @@ module fifo_same_clock ...@@ -52,12 +53,13 @@ module fifo_same_clock
// assign data_out = just_one?inreg:outreg; // assign data_out = just_one?inreg:outreg;
assign data_out = out_full?outreg:inreg; assign data_out = out_full?outreg:inreg;
assign rem = (!out_full || re)&& (just_one? wem : re); assign rem = (!out_full || re)&& (just_one? wem : re);
assign outreg_use_inreg=(out_full && two_or_less) || just_one;
// assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000)); // assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000));
// TODO: verify rem is not needed instead of re // TODO: verify rem is not needed instead of re
assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000)); assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
always @ (posedge clk or posedge rst) begin always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0; if (rst) fill <= 0;
else if (we && ~re) fill <= fill+1; else if (we && ~re) fill <= fill+1;
...@@ -79,10 +81,12 @@ module fifo_same_clock ...@@ -79,10 +81,12 @@ module fifo_same_clock
always @ (posedge clk) begin always @ (posedge clk) begin
if (wem) ram[wa] <= inreg; if (wem) ram[wa] <= inreg;
just_one <= (next_fill == 1); just_one <= (next_fill == 1);
two_or_less <= (next_fill == 1) | (next_fill == 2);
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0; half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
full <= (fill & (1<< DATA_DEPTH ))!=0; full <= (fill & (1<< DATA_DEPTH ))!=0;
if (we) inreg <= data_in; if (we) inreg <= data_in;
if (rem) outreg <= just_one?inreg:ram[ra]; // if (rem) outreg <= just_one?inreg:ram[ra];
if (rem) outreg <= outreg_use_inreg ? inreg : ram[ra];
wem <= we; wem <= we;
end end
endmodule endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment