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Commit 429b228d authored by Andrey Filippov's avatar Andrey Filippov
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HISPI: added per-lane line-sync monitoring, TRIG as programmable option 

for GP0 and GP1
parent a238c147
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Showing with 109 additions and 29 deletions
fpga_version.vh
View file @ 429b228d
......@@ -36,8 +36,9 @@
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300fb; // serial - 17.4 - serial, adding trigger control, lanes_alive (violated xclk by 0.004)
// parameter FPGA_VERSION = 32'h039300fa; // serial - 15.3 - serial, modifying lens_flat - timing met
parameter FPGA_VERSION = 32'h039300f4; //parallel - 17.4 - , modifying lens_flat - timing met
// parameter FPGA_VERSION = 32'h039300f4; //parallel - 17.4 - , modifying lens_flat - timing met
// parameter FPGA_VERSION = 32'h039300f9; // serial - 17.4 - serial, modifying lens_flat - timing met
// parameter FPGA_VERSION = 32'h039300f8; // serial - 17.4 - failed pclk by 0.122
// parameter FPGA_VERSION = 32'h039300f3; //parallel - 17.4 - adding buffer frame number to status (no debug)
......
includes/x393_parameters.vh
View file @ 429b228d
......@@ -478,8 +478,8 @@
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......
py393/x393_export_c.py
View file @ 429b228d
......@@ -322,7 +322,7 @@ class X393ExportC(object):
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = self._enc_status_sens_io(),
data = [self._enc_status_sens_io(),self._enc_status_sens_io_hispi()],
name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs)
......@@ -1835,7 +1835,7 @@ class X393ExportC(object):
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling (N/A for HiSPI"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
......@@ -1844,6 +1844,23 @@ class X393ExportC(object):
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_io_hispi(self):
dw=[]
dw.append(("ps_out", 0, 8,0, "Sensor MMCM current phase"))
dw.append(("ps_rdy", 8, 1,0, "Sensor MMCM phase ready"))
dw.append(("xfpgadone", 9, 1,0, "Multiplexer FPGA DONE output"))
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
dw.append(("lanes_alive", 14, 4,0, "Per-line HACT toggling (reset by changing DLL delays)"))
# dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
# dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -2056,10 +2073,10 @@ class X393ExportC(object):
dw.append(("ign_embed", vrlg.SENS_CTRL_IGNORE_EMBED, 1, 0, "Ignore embedded data (non-image pixel lines"))
dw.append(("ign_embed_set",vrlg.SENS_CTRL_IGNORE_EMBED + 1,1,0, "Set mode to 'ign_embed' field"))
dw.append(("set_dly", vrlg.SENS_CTRL_LD_DLY, 1, 0, "Set all pre-programmed delays to the sensor port input delays"))
dw.append(("gp0", vrlg.SENS_CTRL_GP0, 1, 0 , "GP0 multipurpose signal to the sensor"))
dw.append(("gp0_set", vrlg.SENS_CTRL_GP0 + 1, 1, 0, "Set GP0 to 'gp0' value"))
dw.append(("gp1", vrlg.SENS_CTRL_GP1, 1, 0 , "GP1 multipurpose signal to the sensor"))
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 1, 1, 0, "Set GP1 to 'gp1' value"))
dw.append(("gp0", vrlg.SENS_CTRL_GP0, 2, 0 , "GP0 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp0_set", vrlg.SENS_CTRL_GP0 + 2, 1, 0, "Set GP0 to 'gp0' value"))
dw.append(("gp1", vrlg.SENS_CTRL_GP1, 2, 0 , "GP1 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
return dw
def _enc_sensio_jtag(self):
......
sensor/sens_10398.v
View file @ 429b228d
......@@ -63,8 +63,10 @@ module sens_10398 #(
parameter SENS_CTRL_IGNORE_EMBED = 8, // 9: 8
parameter SENS_CTRL_LD_DLY= 10, // 10
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
// parameter SENS_CTRL_GP0= 12, // 13:12
// parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP1= 15, // 17:15 00 - float, 01 - low, 10 - high, 11 - trigger
// parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
// parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
......@@ -190,7 +192,8 @@ module sens_10398 #(
reg ld_idelay=0;
reg ignore_embed=0; // do not process sensor data marked as "embedded"
wire [14:0] status;
// wire [14:0] status;
wire [19:0] status;
wire cmd_we;
wire [2:0] cmd_a;
......@@ -206,17 +209,22 @@ module sens_10398 #(
reg xfpgatms=0; // TMS to be sent to external FPGA
reg xfpgatdi=0; // TDI to be sent to external FPGA
reg [1:0] gp_r; // sensor GP0, GP1. For now just software control, later use for something else
/// reg [1:0] gp_r; // sensor GP0, GP1. For now just software control, later use for something else
reg [3:0] gp_r; // sensor GP0, GP1. 2 bits per port : 00 - float, 01 - low, 10 - high , 11 - trigger
reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
reg hact_r;
wire hact_mclk;
reg hact_alive;
assign status = { locked_pxd_mmcm,
wire [HISPI_NUMLANES-1:0] monitor_pclk;
wire [HISPI_NUMLANES-1:0] monitor_mclk;
reg [HISPI_NUMLANES-1:0] lanes_alive;
assign status = {lanes_alive,
hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
ps_rdy, ps_out,
xfpgatdo, senspgmin};
assign iaro = trigger_mode? ~trig : iaro_soft;
......@@ -281,15 +289,25 @@ module sens_10398 #(
if (mrst) ld_idelay <= 0;
else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];
if (mrst) gp_r[0] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 1]) gp_r[0] <= data_r[SENS_CTRL_GP0];
/// if (mrst) gp_r[0] <= 0;
/// else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 1]) gp_r[0] <= data_r[SENS_CTRL_GP0];
/// if (mrst) gp_r[1] <= 0;
/// else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 1]) gp_r[1] <= data_r[SENS_CTRL_GP1];
if (mrst) gp_r[1:0] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 2]) gp_r[1:0] <= data_r[SENS_CTRL_GP0+:2];
if (mrst) gp_r[3:2] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 2]) gp_r[3:2] <= data_r[SENS_CTRL_GP1+:2];
if (mrst) gp_r[1] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 1]) gp_r[1] <= data_r[SENS_CTRL_GP1];
if (mrst || set_iclk_phase || set_idelays) hact_alive <= 0;
else if (hact_mclk) hact_alive <= 1;
if (mrst || set_iclk_phase || set_idelays) lanes_alive <= 0;
else lanes_alive <= lanes_alive | monitor_mclk;
end
......@@ -330,7 +348,7 @@ module sens_10398 #(
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15+1) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+1+HISPI_NUMLANES) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
......@@ -338,7 +356,7 @@ module sens_10398 #(
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
// .status ({status_alive,status}), // input[25:0]
.status ({hact_alive,status}), // input[15:0]
.status (status), // input[19:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......@@ -406,9 +424,23 @@ module sens_10398 #(
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pxd_mmcm), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output
.monitor_pclk (monitor_pclk) // output reg[3:0] // for monitoring: each bit contains single cycle @pclk line starts
);
dly_16 #(
.WIDTH(HISPI_NUMLANES)
) dly_16_monitor_i (
.clk (pclk), // input
.rst (1'b0), // input
.dly (4'h0), // input[3:0]
.din (monitor_pclk), // input[3:0]
.dout (monitor_mclk) // output[3:0]
);
/*
output reg [HISPI_NUMLANES-1:0] monitor_pclk // for monitoring: each bit contains single cycle @pclk line starts
obufds #(
.CAPACITANCE("DONT_CARE"),
.IOSTANDARD(PXD_IOSTANDARD), // not diff, just opposite phase signals
......@@ -506,6 +538,7 @@ module sens_10398 #(
. I(imrst) // input
);
/*
// generate GP0/TDI
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
......@@ -527,6 +560,31 @@ module sens_10398 #(
.O (sns_gp1), // output
.I (gp_r[1]) // input
);
*/
// generate GP0/TDI
obuft #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_gp0_tdi_i (
.O (sns_gp0_tdi), // output
.I (xpgmen? xfpgatdi : ((&gp_r[3:2])? iaro: gp_r[3])), // input
.T (xpgmen? 1'b0 : ~|gp_r[1:0])
);
// generate GP1
obuft #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_gp1_i (
.O (sns_gp1), // output
.I ((&gp_r[3:2])? iaro: gp_r[3]), // input
.T (~|gp_r[3:2])
);
// READ TDO (and flash)
ibuf_ibufg #(
.CAPACITANCE (PXD_CAPACITANCE),
......
sensor/sens_hispi12l4.v
View file @ 429b228d
......@@ -112,7 +112,8 @@ module sens_hispi12l4#(
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
output clkfb_pxd_stopped_mmcm, // output
output reg [HISPI_NUMLANES-1:0] monitor_pclk // for monitoring: each bit contains single cycle @pclk line starts
);
wire ipclk; // re-generated half HiSPi clock (165 MHz)
......@@ -331,6 +332,9 @@ module sens_hispi12l4#(
vact_pclk <= {vact_pclk[0],vact_pclk_strt [0] || hact_r};
eof <= vact_pclk[1] && !vact_pclk[0];
// vact_out <= vact_pclk_strt [0] || hact_r;
monitor_pclk <= rd_run & ~rd_run_d;
end
dly_16 #(
......
sensor/sensor_channel.v
View file @ 429b228d
......@@ -171,8 +171,8 @@ module sensor_channel#(
`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......
sensor/sensors393.v
View file @ 429b228d
......@@ -170,8 +170,8 @@ module sensors393 #(
`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
......
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